KR100263483B1 - Fast phase lock circuit and phase locking method thereof - Google Patents

Abstract

PURPOSE: A high-speed phase-locked loop is provided to prevent errors in an initial operation by using a feedback loop and a self-delay time measuring route. CONSTITUTION: A high-speed phase-locked circuit has a measurement controller(40) with a self-phase measure circuit(42) and a measure delay array(43); and a register controller(41) with a phase detecting block(44), a shift register array(45), a variable delay array(46) and a delay compensating block(47). The self-phase measure circuit(42) measures phases of an RCLK signal and an RCLK signal to latch an enable signal in a rising edge of the RCLK signal to output an MB(Measure Begin) signal, and outputs an ME(measure End) signal. The measure delay array(43) includes n number of measure delay units, and outputs delay time compensation cycle determining signals(MQ1,...,MQn). The phase detecting block(44) outputs an SHR(shift right) signal, an SHL(shift left) signal, a clock lock signal and two-division clock signal. The shift register array(45) outputs delay time compensating signals(Q1,...,Qn). The variable delay array(46) is delayed by the delay time compensating signals(Q1,...,Qn). The delay compensating block(47) receives a delayed clock(DCLK) to carry out feedback of an FCLK.

Description

High speed phase synchronization circuit and phase synchronization method using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase synchronization circuit of a semiconductor integrated circuit, and more particularly, to a high speed phase synchronization circuit having a feedback loop and self delay time measurement path suitable for delay compensation and power consumption reduction, and a phase synchronization method using the same. will be.

In a synchronous circuit operating at a high speed with respect to an external clock, a clock used in an internal circuit drives a high load capacitance, and as a way to compensate for the delay time caused by a PLL (PLL) circuit and a DL ( Use DLL (Delay-Locked Loop) circuit.

Hereinafter, a high speed phase synchronization circuit according to the related art will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram of a prior art ALDL, and Fig. 2A is a block diagram of an ALDL delay line. FIG. 2B is a block diagram and an operation timing diagram of RDL's phase comparator. FIG.

PIEL and DL use analog circuits such as charge pump circuits and voltage controlled oscillators (VCOs) to achieve phase-locked operation of the input and internal clocks.

Therefore, in case of active mode (Read / Write operation) and ready mode (Standby or Refresh) while operating synchronized with the input clock like SDRAM, the input clock is cut off for low power operation in the ready mode. Fast phase synchronization cannot be achieved when switching operation.

That is, the low power operation is difficult because the input clock cannot be cut off for switching the fast operation mode. This takes a long time to synchronize the phase, which also increases power consumption.

In order to solve the problem of time and power consumption required for phase synchronization, the digital DL is designed by digitally adjusting the delay time and using phase synchronization information stored in a register during phase synchronization after initial synchronization. This is the circuit of FIG.

FIG. 1 illustrates a configuration of a registered controlled delay lock loop (LDL) capable of stably supplying an operation clock without being affected by temperature, voltage, and process variables in 256Mb synchronous DRAM (SDRAM).

First, a clock buffer 1 for buffering an external clock Ext-CLK, a 1/8 divider 4 for dividing the buffered external clock at a constant ratio (1/8), and the 1/8 divider ( A phase comparator 8 for comparing and outputting the output signal of 4) and a clock signal input again through the repeat circuits 10, and a shift signal with respect to a clock delay by the comparison signal of the phase comparator 8; A shift register 9 for outputting a delay signal; a delay line 5 for variably outputting a clock signal divided by 1/8 by the shift signal; and a logic gate chain; And a delay line 2 for variable delay outputting the clock signal output from the delay signal, and an output buffer 3 for buffering and outputting the clock signal output for the variable delay output in the delay line 2.

Replica circuits (10) is a dummy output buffer (6) for buffering and outputting the clock signal output by being delayed by the shift signal in the delay line (5), and the signal of the dummy output buffer (6) It consists of a dummy clock buffer 7 input to the phase comparator 8.

FIG. 2A shows the configuration of the delay line of AlDLEL configured as a logic gate chain, and FIG. 2B shows the configuration and operation timing diagram of the phase comparator.

AlDiel can represent the time required for phase synchronization as follows.

The minimum delay time of the _loop can be represented by T _{min, loop} = t _D + t _CLKBUF + t _REF .

Here, t _D is a delay time, t _CLKBUF is a time required for clock buffering, and t _REF is a cycle time of a reference clock.

At this time, the stage number N of the unit delay time required until the phase synchronization and the time T _LOCK until the phase synchronization can be expressed as follows.

N = (T _CLKR -T _{min, loop} ) / t _D , T _LOCK = CLKS * N

Here, CLKS is a trigger pulse of the data flip-flop, and _CLKR is frequency-divided into two or more frequencies so as to satisfy the cycle tCLKS = M * T _CLKR > T _{min, loop} + t _D .N _LOCK of CLKS. M represents the frequency of division.

Therefore, when T _CLKR -T _{min, loop} > 0 is satisfied, T _LOCK = M * T _CLKR * (T _CLKR -T _{min, loop} ) / t _D. The synchronization time is proportional to the square of T _CLK , and if T _{min, loop} is determined, the synchronization setup time can be very long at low frequencies, i.e. large clock cycle times.

Also, at higher frequencies, the M value must be large to ensure one delay increase during the loop delay, resulting in longer time to phase synchronization.

In order to solve this problem, the clock synchronization delay circuit that monitors the delay time in the clock driving buffer without a feedback loop and measures it through the unit delay time chain shows a phase synchronization in two cycles. 3.

3A and 3B are block diagrams and operation timing diagrams of a conventional SMD circuit.

Synchronous Mirror Delay (SMD) phase-synchronization circuitry uses an external clock (External CLK) input through an input buffer to delay monitor circuits (DMC), forward delay array (FDA), backward delay array (BDA), and mirror control circuits (MCC). And the like, as shown in FIG. 3B, phase synchronization is performed in two cycles.

Such a SMD phase-lock circuitry takes two cycles to complete phase synchronization.

However, because there is no loop to compensate for the delay time in unit delay devices such as FDA, BDA, etc. due to external factors such as power voltage, temperature change, and process, skew of the input clock at the final synchronous clock. May occur.

Because of this skew, it can be difficult to compensate for the delay time of the internal clock buffer in the phase-lock circuit, so care must be taken to ensure that the delay times of the FDA and BDA unit delay elements match.

Such a high speed phase locked circuit of the prior art has the following problems.

First of all, the prior art AlDL has a problem of increasing power consumption due to a long synchronization time.

Second, when the phase-lock circuit is switched from non-operation to normal operation, it cannot be used as the internal clock of the circuit until the clock is stabilized, so the phase-lock circuit continues to operate even when the input clock is blocked, such as in a low power operation mode. Power consumption in the synchronization circuit cannot be prevented.

Third, if the data flip-flop stores the initial synchronization information, it may take one cycle until the phase synchronization occurs again. However, if the initial synchronization information is out of phase due to external factors such as power voltage, temperature change, and phase change of the input clock, The clock synchronization operation is unstable because the synchronization operation must be performed.

SMD phase-lock circuitry can monitor the clock input buffer delay and clock buffer delay time to be compensated for (by DMC block), but the results will vary depending on the sensitivity of the clock input buffer and the waveform of the input clock. Flies a lot

That is, the timing error of the clock synchronized through the synchronization process is large.

In addition, if the period of the input clock is greater than the delay time of the monitor circuit, an error occurs in the initial operation and limits the use of the clock frequency.

The present invention has been made to solve the problems of the prior art phase synchronization circuit and the synchronization method, a high speed phase synchronization circuit having a feedback loop and self delay time measurement path suitable for delay compensation and reduction of power consumption. And to provide a method.

1 is a block diagram of a conventional ALDL

Figure 2a is a block diagram of the delay line of Alielel

Fig. 2B is a block diagram and operation timing diagram of RDL's phase comparator

3A and 3B are block diagrams and operation timing diagrams of a conventional SMD circuit.

4 is a block diagram of a high speed phase synchronization device according to the present invention;

5 is a block diagram of a self phase measuring circuit according to the present invention;

6 is a block diagram of a measurement delay array according to the present invention.

7A and 7B illustrate a configuration of a variable delay array and a shift register array according to the present invention.

8 is a block diagram of a phase detection unit according to the present invention;

9 is a flowchart of a phase locked operation according to the present invention.

10 is a phase locked clock waveform diagram according to the present invention.

11 is a clock timing diagram illustrating a phase comparison detection interval according to the present invention.

12A and 12B are phase comparison detection logic and simulation diagrams according to the present invention.

Explanation of symbols for main parts of the drawings

40. Measurement control section 41. Register control section

42. Magnetic phase measurement circuitry 43. Measurement delay array

44. Phase Detector 45. Shift Register Array

46. Variable Delay Array 47. Delay Compensation Section

48. Clock Driver

The fast phase synchronization circuit of the present invention having a feedback loop and self delay time measurement path suitable for delay compensation and power consumption reduction measures a measurement start signal (MB) by measuring a phase of an input RCLK and a feedback FCLK. Measurement Controlled Delay-Locked Loop Part that generates an end signal ME and outputs the delay time compensation cycle determination signals MQ1, MQ2, ... MQn in units of measurement delay units using these two signals. And RCLK inputted by generating delay time compensation signals Q1, Q2, ..., Qn according to the delay time compensation cycle determination signal by receiving the divided RCLK, the fed back FCLK, RCLK signal, and the enable signal. And a Register Controlled Delay-Locked Loop Part for outputting a phase-locked clock signal QCLK with a variable delay. When the enable signal is input, the self phase measurement start pulse is started to form a phase locked loop to feed back the input RCLK in the first stage, and the enable signal is edged at the rising edge of the FCLK to measure the measurement start signal (MB). ) And outputting the measured phase difference by using the RCLK as the measurement end signal (ME), and setting the delay compensation cycle determination signal (MQs) after the phase difference measuring operation of the RCLK and FCLK is completed, Loading the delay time compensation cycle determination signals (MQ1, MQ2, ... MQn) and starting the magnetic phase measurement end pulse; starting the phase detection operation when the magnetic phase measurement end pulse starts; Within 2 cycles of the delay time to be compensated for in the phase detection interval corresponding to 1.5 times the delay time (tUNIT) in one variable delay stage or one measurement delay stage. Determining a phase and maintaining phase synchronization without changing the loop phase formed when the relative signal between the FCLK and the detection feedback clock DFCLK is in the phase detection period to generate the synchronization signal LOCK. It is characterized by.

Hereinafter, a high speed phase synchronization circuit and a method of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a configuration of a fast phase synchronizer according to the present invention.

The high-speed phase synchronization circuit of the present invention includes a measurement control section 40 consisting of a magnetic phase measurement circuit section 42 and a measurement delay circuit section 43, a phase detection section 44, a shift register array 45, and a variable delay array 46. And a register controller 41 composed of a delay compensator 47.

The configuration will be described in more detail as follows.

First, the measurement control unit 40 measures the phase of the RCLK inputted through the input buffer and the FCLK fed back by the input enable signal and latches the enable signal at the rising edge of the FCLK to measure the measurement start signal (MB). ) And a self phase measure circuit (SPMC) 42 for outputting a measurement end signal ME by a clock of RCLK and n measurement delay units connected in series. Unit) to receive two signals of MB and ME output from the magnetic phase measurement circuit unit 42 and output delay compensation cycle determination signals MQ1, MQ2, ... MQN in units of measurement delay units. It consists of a measurement delay array 43.

The register controller 41 first receives two divided RCLKs, a fed back FCLK, an RCLK signal, and an enable signal and corresponds to 1.5 times the delay time tUNIT in one variable delay step or one measurement delay step. Phase detection unit 44 for outputting shift right (SHR), shift left (SHFt), clock sync signal (LOCK), and two-division clock (SCLK) signal for shift adjustment by performing phase detection and comparison operation during the interval. And n unit shift register units are connected in series to receive the SHR, SHL, LOCK, and SCLK signals of the phase detector 44, and delay time compensation cycle determination signals MQ1, MQ2, and the like. A shift register array 45 for outputting delay time compensation signals Q1, Q2, ..., Qn in accordance with .MQn, and delay time compensation signals Q1, Q2, ... of the shift register array 45; Variable delay of RCLK input by .., Qn) A variable delay array 46, a delay compensator 47 for receiving and compensating for the delay clock DCLK of the variable delay array 46 and feeding back the FCLK, and a delay clock of the variable delay array 46 And a clock driver 48 that receives the DCLK and outputs the phase-locked clock signal QCLK.

A detailed configuration of each component block of the high speed phase synchronizing circuit of the present invention configured as described above is as follows.

5 is a block diagram of a self phase measuring circuit according to the present invention, and FIG. 6 is a block diagram of a measurement delay array according to the present invention.

First, the detailed configuration of the self-phase measurement circuit section 42 of the measurement control unit 40 of the present invention, as shown in Figure 5, by latching the enable signal at the rising edge of each clock measurement start signal (MB), measurement end signal It is to output (ME).

The first DF / F 50 which latches the enable signal and outputs the measurement start signal MB at the rising edge of the feedback clock FCLK compensated for the delay time for phase synchronization, and the input clock RCLK rises. The second DF / F 51 that latches and outputs the enable signal at the edge and the latch signal of the second DF / F 51 are received and latched at the rising edge of the input clock RCLK to measure the measurement end signal ME. It consists of a third DF / F (52) for outputting.

The measurement delay array 43 which outputs the delay time compensation cycle determination signals MQ1, MQ2, ... MQn in units of each measurement delay unit includes n measurement delay units connected in series. The configuration is as follows.

As shown in FIG. 6, a first NAND gate 60 NAND-operates and outputs a measurement start signal MB and a Vcc signal from the magnetic phase measurement circuit unit 42, and an output of the first NAND gate 60. A second NAND gate 61 for NAND-operating the signal and the Vcc signal, and inverting the output signal of the second NAND gate 61 and the measurement end signal ME from the magnetic phase measurement circuit section 42. The third NAND gate 62 outputs a delay time compensation cycle determination signal MQ by performing a NAND operation on the / measurement end signal / ME.

Here, the first measurement delay unit receives the measurement start signal MB in the magnetic phase measurement circuit section 42, but the measurement start signal MB from the second NAND gate of the previous measurement delay unit from the next measurement delay unit. Receive.

The measurement delay units at each stage output delay time compensation cycle determination signals MQ1, MQ2, ... MQN, respectively.

The detailed configuration of each configuration block of the register controlled DLL part is as follows.

7A and 7B are block diagrams illustrating a variable delay array and a shift register array according to the present invention, and FIG. 8 is a block diagram illustrating a phase detection unit according to the present invention.

First, the phase detector 44 latches and outputs a feedback clock signal FCLK fed back from the delay compensator 46 by the input clock RCLK and one variable delay step. Or a second DF / F 81 for latching and outputting a delayed feedback clock signal Delayed FCLK by an input clock RCLK, the section corresponding to 1.5 times the delay time tUNIT in one measurement delay step; A first NAND gate 86a for performing NAND operation on the output signal Q of the first DF / F 80 and the output signal Q of the second DF / F 81, and a first NAND gate 86a. A second NAND gate 86b for NAND operation of the computed signal and the reverse feedback signal, and a third signal for latching and outputting the output signal of the second NAND gate 86b by the input clock RCLK. DF / F 82, the inverted output signal / Q of the first DF / F 80, the inverted output signal / Q of the second DF / F 81, and the third DF / F 82. Output signal (Q) A third NAND gate 86c for NAND operation and output; a fourth NAND gate 86d for NAND operation and outputting an operation signal and an enable signal of the third NAND gate 86c; and a fourth NAND gate 86d. Of the first inverter 87a for inverting the output signal of the first inverter 87a and the inverted output signal / Q of the second DF / F 81 and the third DF / F 82. A second NAND gate 86e for NAND-operating the output signal Q and the enable signal, and a second inverter for inverting the operation signal of the fifth NAND gate 82 to output a shift left (SHL) signal ( 87b), the sixth NAND gate 86f for performing NAND operation on the shift write and shift left signals, and the sixth NAND gate 86f inverted by the third inverter 87c are divided into two divisions. The fourth DF / F 83 which latches by the input clock RCLK to output the synchronization signal LOCK, and NA and the synchronization signal and the enable signal are NA. A seventh NAND gate 86g output by performing an ND operation, a fourth inverter 87d that inverts and outputs an operation signal of the seventh NAND gate 86g, and a two-division input clock RCLK delayed by the Delay 84. / 2) and a ground signal are multiplexed using the output signal of the fourth inverter 87d as a switching signal to output a two-division clock SCLK for shift adjustment.

In addition, the shift register array 45 may perform delay compensation signals Q1 and Q2 in units of shift register units according to the delay compensation cycle determination signals MQ1, MQ2,... MQn output from the measurement delay array 40. , ..., Qn) is output block and its configuration is as follows.

As shown in FIG. 7B, the shift register unit includes: a first NAND gate 74 for performing NAND operation on the shift write signal of the phase detector 44 and the delay time compensation signal Q (i + 1) of the next stage; A second NAND gate 75 for performing a NAND operation on the shift left signal of the phase detector 44 and the delay time compensation signal Q (i-1) of the front end, and the first and second NAND gates 74 ( The third NAND gate 76 performs a switching operation by the third NAND gate 76 for NAND calculating the arithmetic signal of 75), the dividing clock SCLK for shift adjustment, and the inverted shift clock dividing clock SCLK. The output signal of the first transmission gate 77 for switching and outputting the operation signal of the first transmission gate 77 and the output signal of the first transmission gate 77 that is output by being delayed by a predetermined clock is divided into two division clocks SCLK for shift adjustment and two division clocks for inversion control. Of the second transmission gate 78 switching output by the SCLK and the measurement delay array 43 A NAND operation for outputting the time compensation cycle determination signals (MQ1, MQ2, ... MQn) and the output signal of the second transfer gate 78 to output delay time compensation signals (Q1, Q2, ..., Qn). It consists of four NAND gates 79.

In the variable delay array 46, n variable delay units are connected in series, and each variable delay unit configuration is as shown in FIG. 7A.

A first NAND gate 71 (RCLK is inputted to the first unit, but the output of the preceding unit is input from the next unit after receiving the delay compensation signals Q1, Q2, ..., Qn) and the input clock RCLK. Signal is input.), And a second NAND which performs NAND operation on the output signal X of the first NAND gate 71 and the inversion delay time compensation signals / Q1, / Q2, ..., / Qn. A gate 72, and a third NAND gate 73 for performing a NAND operation on the operation signal of the second NAND gate 72 and the feedback signal Y fed back from the next stage.

The phase synchronization operation of the high speed phase synchronization circuit of the present invention configured as described above is as follows.

9 is a flowchart of a phase locked operation according to the present invention, and FIG. 10 is a phase locked clock waveform diagram according to the present invention.

11 is a clock timing diagram illustrating a phase comparison detection interval according to the present invention, and FIGS. 12A and 12B are a phase comparison detection logic diagram and a simulation diagram according to the present invention.

9 illustrates a phase-lock operation sequence of the present invention. First, when an enable signal is input, the self phase measurement start pulse is started.

That is, when the enable signal becomes HIGH, the input clock RCLK is input to the phase lock circuit. At this time, Q (i) of the shift register array 45 is high only Q (1) and the rest is LOW state.

In addition, since the variable delay array 46 forms a loop in the stage where the Q (i) value is HIGH, the input RCLK is fed back in the first stage. This is called FCLK.

When the magnetic phase measurement start pulse starts, the magnetic phase measurement circuit section 42 measures the phase difference between RCLK and FCLK.

The magnetic phase measurement circuit part 42 outputs the measurement start signal MB by edge- ting the enable signal at the rising edge of the FCLK, and outputs the RCLK as the measurement end signal ME via two flip flops.

At this time, the phase difference between the measurement start signal and the measurement end signal is equal to the phase difference between the rising edge of the first FCLK to be fed back and the rising edge of the second RCLK after being enabled.

This phase difference is equal to the delay time to be compensated for.

After the phase difference measurement operation of RCLK and FCLK is completed, the delay time compensation cycle determination signal of the measurement delay array 43 is set.

The measurement start signal MB of the magnetic phase measurement circuit section 42 is inverted (/ MB) and commonly input to each measurement delay unit, and the measurement end signal ME is passed through two NAND gates in each measurement delay unit. It is passed to the next measurement delay unit.

At this time, until the measurement start signal is HIGH, that is, the inversion measurement start signal (/ ME) becomes LOW, each measurement delay unit receives a low pulse MQ through the remaining NAND gates by the measurement end signal MB (i). (i) occurs. At this time, the propagation time in each measurement delay unit is equal to the variable delay time.

When MQs are set in this manner, the delay register array 45 loads the delay compensation cycle determination signals MQ1, MQ2, ... MQn and starts the self phase measurement end pulse.

As such, when the magnetic phase measurement end pulse is started, the operation of the magnetic phase measurement circuit section 42 and the measurement delay array 43 is stopped and the phase detection section 44 is enabled.

If each generated low pulse (MQ (i)) is inputted to the corresponding shift register unit to activate Q (i) HIGH to become high up to the i th, it forms a phase locked loop in step i and FLCK The signal is delayed by a delay time and input to the phase detector 44.

This sets the delay time to be compensated within two cycles, which corresponds to FCLK (2) in FIG.

The phase detector 44 has a phase detection section as shown in FIG. 11 and performs phase detection by the comparison detection logic of FIG. 12A.

In this case, the phase detection interval corresponds to 1.5 times the delay time tUNIT in one variable delay step or one measurement delay step.

The relative of the FCLK and the detection feedback clock DFCLK with respect to the RCLK is in the phase detection period to generate the synchronization signal LOCK.

The synchronization signal causes the output of the MUX 85 of the phase detector 44 to be LOW.

The output of the MUX 85 becomes LOW so that the shift-controlled dividing clock SCLK is not input to the shift register array 45.

Therefore, the shift register array 45 remains in the same state and does not change the formed loop stage, thereby maintaining phase synchronization.

At this time, the jitter is not generated because the variable delay step is not changed back and forth to maintain the phase locked state.

If, for some reason, the phase measurement interval does not coincide with the delay time to compensate, the phase synchronization is achieved within 2 cycles because the FCLK is already approaching the phase synchronization detection region.

When the phase synchronization is completed and the enable signal becomes LOW, the shift register array 45 returns to the initial state and waits for the next phase synchronization operation command.

Fig. 12B shows the result of such phase synchronization operation simulation.

The high-speed phase synchronization circuit of the present invention has the following effects by having a feedback loop and its own delay time measurement path suitable for delay compensation and power consumption reduction.

First, synchronization proceeds quickly by the self-delay time measurement path, resulting in phase-lock operation at low power. This reduces the power consumption of the entire integrated circuit and has the effect of enabling a high speed access operation.

Second, since the transition from the non-operation of the phase synchronization circuit to the normal operation can be performed within several cycles, there is an effect of improving memory performance when applied to synchronous memory such as SDRAM or SGRAM.

Third, since the self-delay time measurement circuit has a phase synchronization operation within 2 cycles even if the initial synchronization information is shifted, the clock synchronization operation is stable. In this case, even if the timing error of the clock synchronized through the synchronization process is small and the period of the input clock is large, no error occurs in the initial operation, thereby effectively accessing the device.

Claims (5)

Magnetic phase measurement circuit unit for measuring the phase of the RCLK inputted by the enable signal and the fed back FCLK, outputting the measurement start signal MB at the rising edge of the FCLK, and outputting the measurement end signal ME by the clock of the RCLK. (SPMC), It is composed of n measurement delay units connected in series, and receives two signals of MB and ME outputted from the magnetic phase measurement circuit unit, and delay time compensation cycle determination signals (MQ1, MQ2, ... MQn) in units of measurement delay units. A measurement delay array for outputting Phase detection unit that outputs the shifted light (SHR), the shift left (SHL), the clock sync signal (LOCK), and the two-division clock (SCLK) signal for shift control by receiving two divided RCLK and RCLK signals, feedback FCLK and enable signals. Wow, a shift register array in which n unit shift register units are connected in series and receive SHR, SHL, LOCK, and SCLK signals and output delay compensation signals (Q1, Q2, ..., Qn) according to the delay compensation cycle determination signal; , A variable delay array configured to variably delay and output RCLK input by the delay time compensation signals Q1, Q2, ..., Qn of the shift register array; A delay compensator for feeding back the FCLK by receiving and compensating the delay clock DCLK of the variable delay array; And a clock driver for outputting a phase-locked clock signal (QCLK) to the delay clock (DCLK) of the variable delay array. The self-phase measuring circuit unit of claim 1, further comprising: a first flip-flop for latching the enable signal at the rising edge of the feedback clock FCLK, in which the delay time for phase synchronization is compensated, and outputting a measurement start signal MB; A second flip-flop that latches and outputs an enable signal at a rising edge of the input clock RCLK; And a third flip-flop which receives the latch signal of the second flip-flop and latches it at the rising edge of the input clock RCLK to output the measurement end signal ME. The method of claim 1, wherein the measurement delay array comprises: a first NAND gate configured to perform a NAND operation on a measurement start signal MB and a Vcc signal; A second NAND gate performing NAND operation on the output signal and the Vcc signal of the first NAND gate; A measurement delay consisting of a third NAND gate configured to output a delay time compensation cycle determination signal (MQ) by performing an NAND operation on the output signal of the second NAND gate and the measurement termination signal (ME) inverting the measurement termination signal (ME) A high speed phase locked circuit characterized in that the units are connected in series. When the enable signal is input, starting a magnetic phase measurement start pulse to form a phase locked loop to feedback the input RCLK in the first step (FCLK), Measuring the phase difference by outputting the measurement start signal (MB) by edge of the enable signal at the rising edge of the FCLK, and outputting the measurement signal (ME) through the two flip-flops; Setting delay time compensation cycle determination signals (MQs) after the phase difference measurement operation between RCLK and FCLK is completed; Loading the delay compensation cycle determination signals (MQ1, MQ2, ... MQn) and starting the self phase measurement end pulse when MQs are set, Starting a phase detection operation when the self phase measurement end pulse is started; Determining a delay time to be compensated in two cycles in a phase detection interval corresponding to 1.5 times the delay time tUNIT in one variable delay step or one measurement delay step; When the relative of the FCLK and the detection feedback clock (DFCLK) relative to the RCLK is in the phase detection interval to generate a synchronization signal (LOCK), the phase synchronization is maintained without changing the loop stage formed Phase locked method. 5. The method of claim 4, wherein the phase difference between the measurement start signal and the measurement end signal is equal to the phase difference between the rising edge of the first FCLK to be fed back and the rising edge of the second RCLK after being enabled.