KR20030049303A - Register Controlled DLL Circuit - Google Patents

Abstract

PURPOSE: A register controlled DLL(Delay Locked Loop) is provided to reduce the amount of consumed current by reducing a delay line by 1/3 and the number of clock buffers. CONSTITUTION: A register controlled DLL includes a clock buffer(110), the first divider(120), a delay line(150), the second divider(160), and a DLL driver(180). The clock buffer buffers an external clock and outputs a buffered clock having an internal level. The first divider generates a reference clock which is synchronized by the first period. The delay line includes a plurality of unit delay elements to delay the buffered clock as much as the first delay time according a delay control signal. The second divider(160) outputs a delay monitoring signal which is synchronized by the second period of an output clocks of the delay line. A DLL driver received the output clocks of the delay line and outputs a plurality of DLL clocks.

Description

Register-controlled delay locked loop circuit

The present invention relates to a register controlled delay locked loop and a control method thereof.

In general, a clock is used as a reference for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) caused by an internal circuit occurs, and a DLL is used to compensate for this time delay so that the internal clock has the same phase as the external clock. have.

Important elements for a DLL include small area, small jitter, and fast locking time. This is a performance that is still required in future semiconductor memory devices that become low voltage and become high speed. However, the prior arts have disadvantages that satisfy only some of these elements or are limited to low voltage high speed operation.

On the other hand, DLL has the advantage of being less affected by noise compared to the conventional phase locked loop (PLL), which is widely used in synchronous semiconductor memory including DDR Double Data Rate Synchronous DRAM (SDRAM). Among them, a register controlled DLL is most widely used, for example, to specifically examine the problems of the prior art.

1 is a block diagram of a register controlled DLL of a DDR SDRAM according to the prior art.

The register-controlled DLL of the DDR SDRAM according to the prior art has a first clock for generating an internal clock (fall_clk) generated in synchronization with a falling edge of the external clock signal (clk) by inputting an external clock inversion signal (/ clk). A second clock buffer 12 and an internal clock rise_clk for generating an internal clock rise_clk generated in synchronization with the rising edge of the external clock clk by using the buffer 11, the external clock clk as an input; ) Is divided into 1 / n (n is a positive integer, typically n = 8), and a clock divider 13 outputting a delay monitoring clock dly_in and a reference clock ref, and an internal clock fall_clk. A first delay line 14 having an input as an input, a second delay line 15 having an internal clock rise_clk as an input, a third delay line 16 having a delay monitoring clock dly_in as an input, A shift register 17 for determining delay amounts of the first, second and third delay lines 14, 15, and 16, and a first edge The first DLL driver 20 for driving the output ifclk of the consecutive line 14 to generate the DLL clock fclk_dll, and the DLL clock rclk_dll by driving the output irclk of the second delay line 15. Delay model 22 configured to pass through the same delay condition as the actual clock path by inputting the second DLL driver 21 for generating the first delay signal and the output of the third delay line 16 as feedback_dly. ), A phase comparator 19 for comparing the output of the delay model 22 and the phase of the reference clock ref, and a phase comparison signal PC <0: 4> output from the phase comparator 19. Delay indicating that the shift control signal (SR, SL) and the delay lock (locking) has been made to shift the clock phase of the first to third delay line based on the value stored in the shift register 17 in response to A shift controller 18 for outputting a fixed signal dll_lockb is provided.

The delay model 22 here includes a dummy clock buffer, a dummy output buffer and a dummy load, also called a replica circuit.

Hereinafter, the operation of the conventional register control DLL configured as described above will be described.

First, the first clock buffer 11 receives the falling edge of the external clock clk to generate a synchronized internal clock fall_clk, and the second clock buffer 12 receives the rising edge of the external clock clk and receives the internal clock. Generate a clock (rise_clk). The clock divider 13 divides the internal clock rise_clk synchronized to the rising edge of the external clock clk by 1 / n to generate a clock (ref, dly_in) that is synchronized with the external clock clk once every nth clock. .

In the initial operation, the divided clock dly_in passes through only one unit delay element of the third delay line 16 of the delay unit 10 and is output as a feedback_dly clock, which is fed back through the delay model 22 and fed back. The output is delayed by a clock.

Meanwhile, the phase comparator 19 generates a phase comparison signal PC <0: 4> by comparing the rising edge of the reference clock ref, which is the reference clock, with the rising edge of the feedback clock, and the shift controller 18. ) Outputs shift control signals SR and SL for controlling the shift direction of the shift register 17 in response to the phase comparison signals PC <0: 4>. The shift register 17 determines the delay amounts of the first, second and third delay lines 14, 15, and 16 in response to the shift control signals SR and SL. At this time, when the shift right signal SR is inputted, the register is shifted to the right, and when the shift left signal SL is shifted, the register is shifted to the left.

After that, the delay lock is performed at the moment when the two clocks have the minimum jitter while comparing the delayed feedback feedback and the reference clock ref. The delay lock signal dll_lockb is output to drive the first and second DLL drivers 20 and 21 to obtain DLL clocks fclk_dll and rclk_dll having the same phase as the external clock clk.

In the above operation, the internal clock (fall_clk) and the divided clock (dly_in) have a constant time by receiving the falling edge of the external clock (clk) and the rising clock of the synchronized internal clock (fall_clk) and the external clock (clk). Each of the above signals must have a delay line. As a result, the first delay line, the second delay line, and the third delay line in the DLL have a serious problem of increasing the area of the layout and the elements consuming the most current in the DLL.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a resistor-controlled delayed fixed loop and a control method thereof which significantly reduce the amount of current consumed.

Another object of the present invention is to provide a register controlled delayed fixed loop having a reduced layout area and a control method thereof.

1 is a block diagram of a register controlled DLL of a DDR SDRAM according to the prior art,

2 is a timing diagram of a register controlled DLL according to the prior art;

3 is a block diagram of a register controlled DLL according to the present invention;

4 is a timing diagram of a register controlled DLL in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

110: clock buffer 120: first divider

130: phase comparator 140: delay control signal generator

141: shift register 143: shift controller

150: delay line 160: second divider

170: Delay Model 180: DLL Driver

In order to achieve the above object, the register controlled delay locked loop circuit of the present invention has a clock buffering means, a divider means, a phase comparison means, a delay control signal generating means, a delay line, a delay model, a delay to synchronize an external clock and an internal clock. CLAIMS 1. A delay locked loop having a fixed loop driver, comprising: clock buffering means for buffering an external clock and outputting a buffered clock having a level used internally; First dividing means for generating a reference clock that is synchronized once every first period of the buffered clock; A delay line including a plurality of unit delay elements configured to delay and output the buffered clock by a first delay time according to the delay control signal; Second dividing means for outputting a delay monitoring clock synchronized with each second period of the clock output from the delay line; And delay locked loop driving means for receiving a clock output from the delay line and outputting a plurality of delay locked loop clocks.

Further, the first period of the first dispensing means and the second period of the second dispensing means are the same.

The delay locked loop driving means may receive a rising edge and a falling edge of the clock output from the delay line and output a plurality of delay locked loop clocks having opposite phases.

In addition, the reference clock is characterized in that the opposite of the phase of the buffered clock.

In addition, the phase of the clock output from the delay line and the phase of the delay monitoring clock is characterized in that the opposite.

In addition, the register-controlled delay locked loop control method of the present invention is a delay locked loop control method for synchronizing the external clock and the internal clock, the clock buffering for buffering the external clock and outputting the buffered clock having a level used internally step; A first division step of generating a reference clock synchronized once every first period of the buffered clock; Delaying and outputting the buffered clock by a first delay time according to the delay control signal; A second division step of generating a delay monitoring clock synchronized with the outputted clock by being delayed by the first delay time once every second period; And receiving a clock output by being delayed by the first delay time and outputting a plurality of delay locked loop clocks.

Conventionally, a plurality of delay lines are required by delaying a clock that is unrelated to division and a divided clock through a separate delay line. However, in the present invention, the same result is obtained by only one delay line by dividing a clock that passes through a delay line. It is characterized by being able to.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a block diagram of a register-controlled DLL according to the present invention, and each part operates as follows.

The clock buffer 110 is a circuit for buffering the external clock CLK into a buffered clock clkd2, which is a signal of a level used internally. The clock buffer 110 has a high pulse width and a low width of the external clock CLK and the buffered clock clkd2. Make the pulse widths the same.

The first divider 120 generates a reference clock ref that is synchronized once in every nth clock of the buffered clock clkd2 and is out of phase, and compares the phases of the external clock and the internal clock with each other. In the external clock is a reference clock (ref) output from the first divider, the inner clock is a feedback clock (feedback) through the delay line 150, the second divider 160 and the delay model 170, The shift register 141 which displays the optimal timing of the delay to generate the delay operates by receiving the shift write signal SR and the shift left signal SL from the shift controller 143. Meanwhile, in order to reduce jitter, the delay line 150 including a plurality of unit delay elements having the shortest delay time is the same as the external clock signal CLK according to the signal output from the shift register 141. It is used to adjust the delay time of the buffered clock clkd2 having the pulse width. In addition, the delay line 150 is configured such that the rising time and the falling time have the same delay time, so that the external clock CLK and the pulse width of the output signal iclk of the delay line 150 are the same. The second divider 160 outputs a delay monitoring clock dly_in that is synchronized with each other and is in phase with each of the nth clocks of the output signal iclk of the delay line 150, and the delay model 170 receives an external clock. In order to compensate the time difference between the clock and the actual internal clock, a feedback clock delayed by a predetermined time rather than the delay monitoring clock dly_in is generated. The DLL driver 180 is a buffer that sends the DLL clock to the internal circuit. The DLL driver 180 receives the rising edge and the falling edge of the output signal iclk of the delay line 150 to create the DLL clocks rclk_dll and fclk_dll.

The shift register 141 and the shift controller 143 in the DLL circuit are referred to as a delay control signal generator 140 for controlling the delay line 150.

4 is a timing diagram of a register controlled DLL according to the present invention.

In order to receive the external clock (CLK) to make the DLL clocks (cclk_dll and rclk_dll) that compensate for the time difference between the external clock and the internal clock, only the buffering is performed through the clock buffer 110 and the high of the external clock CLK is applied. Take the same pulse width and low pulse width. That is, the rising edge and the falling edge of the outer clock CLK are received to form a buffered clock clkd2 having the same delay time. The buffered clock clkd2 having the same pulse width as the external clock CLK is input to the first divider 120 and used to make a reference clock ref which is used as a reference for comparing phases, and the delay line 150. Also used as input. The DLL driver 180 receives a rising edge of the output signal iclk of the delay line 150 to generate a pulse to generate a rising DLL clock, and receives a falling edge of the output signal iclk of the delay line 150 to generate a pulse. To generate a polling DLL clock, and the second divider 160 divides the output signal iclk of the delay line 150 by 1 / n to output a delay monitoring clock dly_in that is synchronized once every nth time. The delayed monitoring clock (dly_in), which is the divided signal, is partially delayed through the delay model 170 to become a feedback clock, and the feedback clock is compared with the reference clock (ref) in the phase comparator 130. do.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to.

By reducing the delay line, which consumes the most current in the DLL circuit, to 1/3, and reducing the number of clock buffers, the amount of current consumed can be significantly reduced, and the layout area can be reduced.

Claims (10)

A delay locked loop circuit comprising a clock buffering means, a frequency division means, a phase comparing means, a delay control signal generating means, a delay line, a delay model, and a delay locked loop driver to synchronize an external clock with an internal clock, Clock buffering means for buffering an external clock and outputting a buffered clock having a level used internally; First dividing means for generating a reference clock that is synchronized once every first period of the buffered clock; A delay line including a plurality of unit delay elements configured to delay and output the buffered clock by a first delay time according to the delay control signal; Second dividing means for outputting a delay monitoring clock synchronized once every second period of the clock output from the delay line; And A delay locked loop driving means for receiving a clock output from the delay line and outputting a plurality of delay locked loop clocks Register controlled delay locked loop comprising a. The method of claim 1, And a first period of the first dispensing means and a second period of the second dispensing means are the same. The method according to claim 1 or 2, The delay locked loop driving means receives a rising edge and a falling edge of the clock output from the delay line and outputs a plurality of delay locked loop clocks of opposite phases. The method according to claim 1 or 2, And the phase of the reference clock is opposite to the phase of the buffered clock. The method according to claim 1 or 2, And the phase of the clock output from the delay line is the same as the phase of the delay monitoring clock. In the delay locked loop control method for synchronizing the external clock and the internal clock, A clock buffering step of buffering an external clock and outputting a buffered clock having a level used internally; A first division step of generating a reference clock synchronized once every first period of the buffered clock; Delaying and outputting the buffered clock by a first delay time according to the delay control signal; A second division step of generating a delay monitoring clock synchronized with the outputted clock by being delayed by the first delay time once every second period; And Receiving a clock output by being delayed by the first delay time and outputting a plurality of delay locked loop clocks Register controlled delay locked loop control method comprising a. The method of claim 6, And a first period of the first division step and a second period of the second division step are the same. The method according to claim 6 or 7, And a plurality of delay locked loop clocks receiving a rising edge and a falling edge of a clock outputted by delaying the buffered clock by a first delay time, and having a reverse phase. The method according to claim 6 or 7, The phase of the reference clock is a register controlled delay locked loop control method, characterized in that the opposite of the phase of the buffered clock. The method according to claim 6 or 7, And a phase of the clock delayed by the first delay time is the same as the phase of the delay monitoring clock.