JPH10187300A - Power supply control circuit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more reduce the power consumption of a module. SOLUTION: A clock controller 7 or 8 detects the processing state of a module 4 or 6 based on the data storage capacity of a first in first out(FIFO) memory 3 or 5, and when load to the module 4 or 6 is not so large, the frequency of a system clock supplied to the module 4 or 6 is continuously reduced and power supply voltage is continuously dropped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control circuit and a power supply control method, and more particularly to, for example, continuously changing the frequency of a system clock and a power supply voltage supplied to a module constituting a one-chip semiconductor circuit or the like. The present invention relates to a power supply control circuit and a power supply control method capable of reducing power consumption of the module.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration of an example of a conventional semiconductor circuit.

In this semiconductor circuit, a buffer 2,
Modules 4, 6, controller 21, AND gate 2
2 and 23 are contained in one chip, and predetermined processing is performed according to a system clock generated by an external clock generator 1.

That is, the clock generator 1 generates a clock having a predetermined constant frequency, and this clock is used as a system clock as the buffer 2 and further as a system clock.
The signal is supplied to the module 4 or 6 via the AND gate 22 or 23, respectively.

The module 4 is supplied with data from the outside. The module 4 performs predetermined processing in synchronization with a system clock supplied via an AND gate 22, and as a processing result, Data
Output to module 6. The module 6 performs a predetermined process on the data output from the module 4 in synchronization with the system clock supplied via the AND gate 23, and outputs the data obtained as a result, similarly to the module 4.

On the other hand, the controller 21 has a control signal for controlling on / off of the supply of the system clock to the modules 4 and 6 from a predetermined application (either hardware or software). (Application control signal), and the controller 21 according to the control signal
An L or H level is output to AND gates 22 and 23.

That is, normally, the controller 21
The H level is output to the D gates 22 and 23, whereby the system clock is supplied to the module 4 or 6 via the AND gates 22 or 23, respectively. On the other hand, for example, on the application side, the processing state of the subsequent module 6 of the modules 4 or 6 is predicted or detected by some method, and data to be processed there has arrived at the module 6. If not, a control signal for instructing to stop supplying the clock to the module 6 is supplied to the controller 21. In this case, the controller 21
Outputs the L level to the AND gate 23, thereby stopping the supply of the system clock to the module 6.

Thereafter, when the application detects that data has been input to the module 6,
A control signal instructing to start supplying a clock to the module 6 is supplied to the controller 21. In this case, the controller 21 outputs an H level to the AND gate 23, thereby outputting the system clock to the module 6. Supply is started.

[0009] Regarding the supply of the clock to the module 4, the same on / off control as in the module 6 is performed by changing the input level to the AND gate 22.

[0010] By performing the on / off control of the supply of the system clock as described above, the module does not operate while the system clock is turned off. Thus, power consumption in the semiconductor circuit can be reduced.

[0011]

However, in recent years,
There is a demand for further reducing power consumption in semiconductor circuits.

The present invention has been made in view of such a situation, and aims to further reduce the power consumption.

[0013]

According to a first aspect of the present invention, there is provided a power supply control circuit for detecting a processing state of a module, and continuously changing a frequency of a system clock and a power supply voltage in accordance with a detection result of the detection means. And a control means for changing the temperature.

According to a fifth aspect of the present invention, in the power supply control method, the processing state of the module is detected, and the frequency of the system clock and the power supply voltage are continuously changed according to the detection result of the processing state of the module. And

In the power supply control circuit according to the first aspect, the detection means detects the processing state of the module, and the control means continuously changes the frequency of the system clock and the power supply voltage in accordance with the detection result of the detection means. It is made to change.

In the power supply control method according to the fifth aspect, the processing state of the module is detected, and the frequency of the system clock and the power supply voltage are continuously changed according to the detection result of the processing state of the module. It has been done.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, the correspondence between each means of the invention described in the claims and the following embodiments will be clarified. For this reason, the features of the present invention are described as follows by adding the corresponding embodiment (however, an example) in parentheses after each means.

That is, the power supply control circuit according to the first aspect comprises:
A power supply control circuit that controls a power supply voltage supplied to a module that performs a predetermined process in synchronization with a predetermined system clock, and includes a detection unit that detects a processing state of the module (for example, a processing step of the program illustrated in FIG. 3). S1 and S3) and control means (for example, processing steps S2 and S4 of the program shown in FIG. 3) for continuously changing the frequency of the system clock and the power supply voltage according to the detection result of the detection means. It is characterized by having.

According to a third aspect of the present invention, in the power supply control circuit, a storage device for storing data to be processed by the module is provided at a preceding stage of the module, and the detecting means corresponds to a storage amount of data in the storage device. Then, a counting means (for example, an up / down (U / D) counter 12 shown in FIG. 4 or the like) shown in FIG. 4 is provided to detect the processing state of the module based on the counting value of the counting means. Features.

Of course, this description does not mean that each means is limited to those described above.

FIG. 1 shows a configuration of an embodiment of a semiconductor circuit to which the present invention is applied. In the figure, the same reference numerals are given to portions corresponding to those in FIG. That is, in this semiconductor circuit, the AND gates 22 and 23 are deleted, and the clock controllers 7 and 8 are provided instead of the controller 21.
The configuration is basically the same as that of the semiconductor circuit of FIG. 6 except that FIFO (First In First Out) memories 3 and 5 and voltage control circuits 9 and 10 are newly provided.

The FIFO memory 3 or 5 is provided at the preceding stage of the module 4 or 6, respectively. Here, the input stage and the output stage operate in synchronization (asynchronously) with different clocks. ing.

That is, a clock is supplied to the input stage of the FIFO memory 3 from the clock generator 1 via the buffer 2, and data is stored in synchronization with the clock. . further,
A clock output from the clock controller 7 is supplied to an output stage of the FIFO memory 3, and data is read out in synchronization with the clock.

The clock output from the clock controller 7 is supplied not only to the output stage of the FIFO memory 3 but also to the module 4.
Reading of data from the FO memory 3 is performed by the module 4
Is performed in synchronization with the operation timing. Further, the clock output from the clock controller 7 is also supplied to the input stage of the FIFO memory 5. Therefore, the writing of data to the FIFO memory 5 is also performed in synchronization with the operation timing of the module 4. Has been made to be done.

The clock output from the clock controller 8 is supplied to the output stage of the FIFO memory 5, and data is read from the FIFO memory 5 in synchronization with the clock. It has been made like that. The clock output from the clock controller 8 is supplied to the module 6 in addition to the output stage of the FIFO memory 5.
The reading of data from the IFO memory 5 is performed in synchronization with the operation timing of the module 6.

Further, when the amount of data stored in the FIFO memory 3 or 5 becomes equal to or less than 1/2 of the storage capacity, the FIFO memory 3 or 5 is likely to overflow with a half empty flag as a flag indicating that. , An allmost full flag as a flag indicating that is output to the clock controller 7 or 8 respectively.

The clock controller 7 or 8 has the FI
The processing state of the module 4 or 6 is detected based on the flag supplied from the FO memory 3 or 5, and corresponding to the detection result, the FIFO memory 3, the module 4,
The frequency of the clock supplied to the FIFO memory 5 and the module 6 is controlled. further,
The clock controller 7 or 8 also controls the voltage control circuit 9 or 10, respectively, in response to the detection of the processing state of the module 4 or 6.

The voltage control circuit 9 or 10 controls the power supply voltage supplied to the module 4 or 6 under the control of the clock controller 7 or 8 respectively.

In the semiconductor circuit configured as described above, the clock generated by the clock generator 1 is supplied to the buffer 2 via the buffer 2 as a system clock.
It is supplied to the input stage of the IFO memory 3 and the clock controllers 7 and 8. The clock controller 7 generates a clock of a predetermined frequency from the clock supplied via the buffer 2 and uses the generated clock as a system clock.
The output is supplied to the output stage of the O memory 3, the module 4, and the input stage of the FIFO memory 5. Similarly, the clock controller 8 generates a clock having a predetermined frequency from the clock supplied via the buffer 2 and supplies the generated clock to the output stage of the FIFO memory 5 and the module 6 as a system clock.

In the FIFO memory 3, data supplied from the outside is stored in synchronization with the system clock supplied to the input stage, and is also synchronized with the system clock supplied to the output stage. Thus, the data already stored is read. This data is supplied to the module 4, where the data read from the FIFO memory 3 is processed in synchronization with the same system clock as the system clock supplied to the output stage. Then, data obtained as a result of the processing is supplied to the FIFO memory 5.

In the FIFO memory 5, the data from the module 4 is stored at the timing of the system clock to which the module 4 is synchronized, and is synchronized with the system clock supplied to the output stage. The data already stored is read. This data is supplied to the module 6, where the data read from the FIFO memory 5 is processed and output in synchronization with the same system clock as the system clock supplied to the output stage. .

As described above, the data processed by the modules 4 and 6 is output from the semiconductor circuit.

On the other hand, the clock controller 7
On the basis of the flag from the O memory 3, the processing state of the module 4 is detected, that is, when the data storage amount in the FIFO memory 3 is large or small, the module 4
It recognizes that the load on the memory is large or small, and controls the frequency of the clock supplied to the output stage of the FIFO memory 3, the module 4, and the input stage of the FIFO memory 5 correspondingly. Further, the clock controller 7 also controls the voltage control circuit 9 according to the magnitude of the load on the module 4 to control the power supply voltage supplied to the module 4.

Specifically, when the load on the module 4 is large, that is, when it is necessary to increase the operation speed of the module 4, the clock controller 7 continuously (gradually) changes the frequency of the system clock output therefrom. ) And the power supply voltage supplied to the module 4 is continuously increased. When the load of the module 4 is small, that is, when the operation speed of the module may be low,
The clock controller 7 continuously lowers the frequency of the system clock output therefrom and continuously lowers the power supply voltage supplied to the module 4.

The clock controller 8 also performs
The magnitude of the load on the module 6 is detected based on the flag from the O memory 5, and the FIFO
The frequency of the clock supplied to the output stage of the memory 5 and the module 6 and the power supply voltage supplied to the module 6 are controlled.

FIG. 2 shows the relationship between the frequency of the system clock supplied to the module 4 or 6 and the power supply voltage.

As shown in the figure, when the frequency of the system clock is lowered, the power supply voltage is reduced accordingly. Further, the frequency of the system clock is increased as the power supply voltage is increased.

Next, referring to the flowchart of FIG.
The control of the clock frequency and the power supply voltage in the clock controller 7 of FIG. 1 will be further described.

First, the clock controller 7 determines whether or not the half empty flag has been received from the FIFO memory 3 in step S1. If it is determined that the half empty flag has been received, that is, the storage capacity of the FIFO memory 3 If there is a margin, and the module 4 does not need to operate so fast, the process proceeds to step S2, where the frequency of the system clock output therefrom is reduced by a predetermined frequency Δf, and then the voltage control circuit 9 is controlled. As a result, the power supply voltage supplied to the module 4 is reduced by the predetermined voltage ΔE, and the process proceeds to step S3.

If it is determined in step S1 that the half-empty flag has not been received, step S2 is skipped and the process proceeds to step S3, where the FIFO
It is determined whether or not the almost full flag has been received from the O memory 3, and if it has been determined that the flag has been received, that is, F
There is no room in the storage capacity of the IFO memory 3 and the module 4
If it is necessary to operate the power supply quickly, the process proceeds to step S4, where the voltage control circuit 9 is controlled to increase the power supply voltage supplied to the module 4 by a predetermined voltage ΔE. Is raised by a predetermined frequency Δf, and the process returns to step S1.

On the other hand, if it is determined in step S3 that the all-most full flag has not been received from the FIFO memory 3, step S4 is skipped and the process returns to step S1.

Accordingly, when the FIFO memory 3 keeps outputting the half empty flag, the processing of steps S1 to S3 is repeated, so that the frequency of the system clock supplied to the module 4 becomes the predetermined frequency △
The power supply voltage continuously decreases in units of f, and the power supply voltage continuously decreases in units of a predetermined voltage ΔE. On the other hand, when the FIFO memory 3 keeps outputting the almost full flag, the processing of steps S1, S3, and S4 is repeated, so that the frequency of the system clock supplied to the module 4 becomes a predetermined frequency Δf unit. , And the power supply voltage continuously increases in units of a predetermined voltage ΔE.

Similarly, the clock controller 8 controls the frequency of the system clock supplied to the module 6 and the power supply voltage.

FIG. 4 shows an example of the configuration of the clock controller 7. Note that the clock controller 8 is similarly configured.

The clock supplied from the clock generator 1 via the buffer 2 is supplied to frequency dividers 11 and 13. The frequency divider 11 divides the clock by 1 / A (where A is a positive integer) and outputs the clock to the clock terminal of the up / down (U / D) counter 12.

The up-down counter 12 is supplied with an almost full flag and a half empty flag. When the up / down counter 12 receives the all-most full flag or the half empty flag at the timing when the output of the frequency divider 11 is supplied to its clock terminal, it decrements or increments the count value, respectively. Then, the count value is supplied to the frequency divider 13 and the voltage control circuit 9 as a control signal.

Therefore, in the up / down counter 12,
At an A-times cycle of the clock output from the clock generator 1, it is detected whether the almost full flag or the half empty flag is received, and if the almost full flag or the half empty flag is received, The count value is decremented or incremented.

After the count value becomes zero, the up-down counter 12 keeps the count value at zero even if it receives the almost full flag. Further, the count value has a predetermined upper limit, and after reaching the upper limit value, the count value is maintained at the upper limit value even if a half empty flag is received.

Here, in the voltage control circuit 9 of FIG. 1, the power supply voltage supplied to the module 4 is controlled in accordance with the count value as a control signal from the up / down counter 12. That is, the voltage control circuit 9 decreases the power supply voltage when the count value from the up / down counter 12 is large, and increases the power supply voltage when the count value is small.

On the other hand, the frequency divider 13 and the phase comparator (PD) 1
4, loop filter (LF) 15, voltage controller (VC
O) 16 and the frequency divider 17 are provided with a PLL (Phase Lock L).
oop) circuit, and the frequency divider 13 divides the clock input thereto into 1 / M when the count value from the up / down counter 12 is M, Supply. The output of the frequency divider 17 is also supplied to the phase comparator 14. The phase comparator 14 detects the phase difference between the outputs of the frequency dividers 13 and 17 and supplies the phase difference to the line filter 15. The line filter 15 removes high-frequency components of the phase comparator 14 and outputs the result to the voltage controller 16. The voltage controller 16 generates a voltage corresponding to the output of the line filter 15, outputs this as a system clock, and outputs it to the frequency divider 17. In the frequency divider 17, the output of the voltage controller 16 is frequency-divided by 1 / N (N is a positive integer) and supplied to the phase comparator 14.

In the above-described PLL circuit, a clock having a frequency N / M times that of the clock input thereto is output. Accordingly, the clock controller 7 outputs a clock having a frequency at most N (= N / 1) times the clock input thereto. The count value M supplied from the up / down counter 12 to the frequency divider 13 is 0.
In this case, the PLL circuit stops its operation. In this case, the clock controller 7 outputs
The clock is not output.

As described above, by continuously changing the frequency of the system clock and the power supply voltage, the power consumption of the modules 4 and 6 can be reduced as compared with the conventional case.

That is, for example, assuming that the loads on the modules 4 and 6 are gradually reduced, the semiconductor circuit in FIG. 6 may have a reduced load as shown in FIG. Until a command is received from the application, the frequency of the system clock supplied to the modules 4 and 6 does not change, and the supply is suddenly stopped at the time specified by the application. On the other hand, in the semiconductor circuit of FIG. 1, as shown in FIG. 5B, as the load decreases, the frequency of the system clock also decreases.

In the semiconductor circuit shown in FIG.
As shown in (C), while the system clock is being supplied to the modules 4 and 6, a predetermined power supply voltage is supplied, and when the supply of the system clock is stopped, the power supply voltage drops at a stretch. On the other hand, in the semiconductor circuit of FIG. 1, the power supply voltage is as shown in FIG.
With the frequency of the system clock.

As a result, since the power consumption is proportional to the square of the power supply voltage, the power consumption is as shown in FIGS. 5 (E) and 5 (F). That is, in the semiconductor circuit of FIG. 6, while a predetermined power supply voltage is supplied, a predetermined constant power is consumed, and when the supply is stopped, the power consumption is reduced at a stretch. On the other hand, in the semiconductor circuit of FIG. 1, the power consumption decreases in proportion to the square of the power supply voltage.

In the semiconductor circuit of FIG. 1, since the system clock is changed together with the power supply voltage supplied to the modules 4 and 6, for example, the power supply voltage is reduced by half.
Then, the operating speeds of the modules 4 and 6 are also halved. Accordingly, the work load of the modules 4 and 6 is also reduced to １ ／, but the power consumption is reduced to ４ (= １ ／ ² ) because the power consumption is proportional to the square of the power supply voltage. That is, power consumption for the same amount of work can be reduced as compared with the case where the power supply voltage and the system clock are not changed.

In the semiconductor circuit shown in FIG. 6, AND is added to the system clock system (clock net).
Since the gates 22 and 23 are inserted, it is necessary to provide extra wiring for delaying the clock, so that it is difficult to control the clock skew.

Further, in order to suppress the skew without arranging wiring for delay, it is necessary to make the clock nets as equipotential as possible. In this case, power consumption in the clock net can be reduced. However, when a gate is provided in the clock net, it is difficult to make the whole of the gate equal potential.

Further, in a large-scale semiconductor circuit including many modules, since the entire capacity of the clock net becomes large, it is difficult to make the entire clock net equipotential. It is necessary to route the wiring. Then, the data processed by the semiconductor circuit is
In the case where the data is temporarily stored in the register and then output, it takes time to output the data to the outside due to a clock delay.

On the other hand, in the semiconductor circuit of FIG. 1, since no gate is provided in the clock net, it is possible to make the whole of the circuit relatively equipotential relatively easily.

In the semiconductor circuit of FIG. 1, the clock output from the clock generator 1 is only supplied to the FIFO memories 3 and the clock controllers 7 and 8 via the buffer 2, so that the load on the buffer 2 is reduced. The clock skew can be reduced. That is, in a case where a plurality of modules are connected in series and pipeline processing is performed, a multistage flip-flop may be provided at a preceding stage of the modules to connect the modules. In this case, 1
The chip may require tens of thousands of flip-flops, making skew control very difficult. On the contrary,
As shown in FIG. 1, before the module 4 or 6,
When the I / O memories 3 or 5 are provided and the modules 4 and 6 are connected and the system clocks are supplied from the clock controllers 7 and 8, even if the number of modules increases, the number generally increases Since it is expected to be about 10, the skew of the clock can be reduced as compared with the case where the clock is supplied to tens of thousands of flip-flops.

The case where the present invention is applied to a one-chip semiconductor circuit has been described above, but such a semiconductor circuit can be applied to, for example, a processor for processing graphic and audio data and the like. .

The frequency divider 11 in FIG.
For example, a so-called loadable device that can read the frequency division ratio so that the frequency division ratio 1 / A can be set to be programmable (programmable) from the outside can be used. is there. In this case, the change rate of the system clock frequency or the power supply voltage shown in FIG. 5B or FIG.
External control is possible.

In this embodiment, when the up-down counter 12 (FIG. 4) receives the almost full flag or the half empty flag, the count value is decremented or incremented, respectively. In addition, for example, only the half-empty flag is supplied to the up / down counter 12, and when the half-empty flag is received or not received, the count value is decremented or incremented, respectively. Is also possible.

Further, in the present embodiment, a PLL circuit is built in clock controller 7 (8), whereby a system clock having a higher frequency than the clock generated by clock generator 1 can be obtained. However, when it is not necessary to operate the modules 4 and 6 with a system clock having a higher frequency than the clock generated by the clock generator 1, the PLL circuit in FIG. It is possible to

In the present embodiment, two modules 4 and 6 are provided in the semiconductor circuit (FIG. 1). However, the number of modules provided in the semiconductor circuit may be one. Or three or more.

Further, in the present embodiment, in the semiconductor circuit, the FIs are provided before the module 4 or 6 respectively.
Although the FO memory 3 or 5 is provided, it is also possible to configure a semiconductor circuit without providing the FIFO memory 3 or 5. However, in this case, it is necessary to detect the processing state of the modules 4 and 6 by some method.

Generally, a module can operate at a higher speed as the power supply voltage is higher. Therefore, the power supply voltage is dropped after lowering the frequency of the system clock. It is desirable to increase the power supply voltage.

[0069]

According to the power supply control circuit according to the first aspect and the power supply control method according to the fifth aspect, the processing state of the module is detected, and the frequency of the system clock and the power supply are determined in accordance with the detection result. The voltage is changed continuously. Therefore, it is possible to further reduce the power consumption of the module.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a semiconductor circuit to which the present invention is applied.

FIG. 2 is a diagram showing a relationship between a frequency of a system clock controlled by clock controllers 7 and 8 in FIG. 1 and a power supply voltage.

FIG. 3 is a flowchart illustrating a control process of a system clock frequency and an electric voltage by clock controllers 7 and 8 in FIG. 1;

FIG. 4 is a block diagram showing a configuration example of a clock controller 7 (8) of FIG. 1;

FIG. 5 shows the frequency of the system clock when the load on modules 4 and 6 gradually decreases,
FIG. 3 is a diagram illustrating a change over time in a power supply voltage and power consumption.

FIG. 6 is a block diagram showing a configuration of an example of a conventional semiconductor circuit.

[Explanation of symbols]

1 clock generator, 2 buffers, 3F
IFO memory, 4 modules, 5 FIFO memory, 6 modules, 7,8 clock generator, 9,10 voltage control circuit, 11 frequency divider, 1
2 Up / down counter, 13 divider, 14
Phase comparator, 15 line filter, 16 voltage controller, 17 divider

Claims (5)

[Claims] 1. A power supply control circuit that controls a power supply voltage supplied to a module that performs a predetermined process in synchronization with a predetermined system clock, wherein the detection unit detects a processing state of the module, and the detection unit Control means for continuously changing the frequency of the system clock and the power supply voltage in accordance with the detection result of the power supply control circuit. 2. The control means according to claim 1, wherein, when lowering the power supply voltage, the frequency of the system clock is lowered, and then the power supply voltage is changed. 2. The power supply control circuit according to claim 1, wherein the frequency of the system clock is changed after increasing the power supply voltage. 3. A storage device for storing data to be processed by the module is provided at a preceding stage of the module, and the detecting means corresponds to a storage amount of the data in the storage device,
2. The power supply control circuit according to claim 1, further comprising: a counting unit configured to increase and decrease a count value, and detecting a processing state of the module based on the count value of the counting unit. 3. 4. A phase lock loop (PLL) circuit that operates in synchronization with the system clock, wherein the control unit changes a frequency division ratio in the PLL circuit in accordance with a count value of the counting unit. 4. The power supply control circuit according to claim 3, wherein the frequency of the system clock is changed. 5. A power supply control method for controlling a power supply voltage supplied to a module that performs a predetermined process in synchronization with a predetermined system clock, comprising: detecting a processing state of the module; A power supply control method characterized by continuously changing the frequency of the system clock and the power supply voltage in accordance with the detection result.