JP2009141881A - Portable electronic device and operation clock control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out proper control of an operation clock frequency to achieve less power consumption in a battery-driven portable electronic device. <P>SOLUTION: According to an operation clock control method for a portable electronic device having a first component circuit, a second component circuit exchanging data with the first component circuit, and an FIFO disposed in a path for data exchange, the number of times the FIFO is filled up or emptied within a unit time is counted, and the frequency of an operation clock for the first component circuit is changed according to a count value given by the counting. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a portable electronic device such as a digital camera or a mobile phone and an operation clock control method thereof, and more particularly to a portable electronic device suitable for reducing power consumption by controlling an operation clock in real time according to a load condition. And an operation clock control method.

  A portable electronic device such as a digital camera or a mobile phone needs to reduce power consumption because it uses a battery as a drive source. For this reason, for example, in the conventional technique described in Patent Document 1 below, in a personal computer including a CPU and a DMA controller, the CPU operation clock is stopped under the situation where the DMA controller is in an operating state and the CPU is in a non-operating state. Low power consumption is achieved. However, when the CPU operating clock cannot be stopped, the power consumption cannot be reduced.

  For this reason, it has been conventionally practiced to reduce the power consumption by individually changing the operating frequencies of various components constituting the electronic device. In order to perform this control, conventionally, whether or not the processing of each component ends within a unit time is obtained in advance by experiment or calculation or simulation, and the operating frequency of each component is defined by software.

JP-A-8-83133

  When controlling each component of an electronic device in software, the load status of the electronic device cannot be monitored in real time, so the operating frequency must be determined in advance for each large processing unit, function, or operation mode. However, there is a problem that it is not possible to achieve a fine reduction in power consumption and further reduction in power consumption.

  In addition, since it is necessary to determine the operating frequency through experiments and simulations, there is a problem that trial and error are repeated until the final determination, which increases the man-hours for developing an electronic device.

  An object of the present invention is to provide a portable electronic device and an operation clock control method that require a small number of development steps and can achieve further reduction in power consumption.

  An operation clock control method for a portable electronic device according to the present invention includes a first component circuit, a second component circuit that transmits and receives data to and from the first component circuit, and a first-in first-out provided in a path for transmitting and receiving the data. In a method for controlling an operation clock of a portable electronic device including a buffer memory (hereinafter referred to as a FIFO), the number of times the FIFO becomes full or empty within a unit time is counted, and the first component circuit is counted according to the count value. The operation clock frequency is changed.

  The operation clock control method for a portable electronic device according to the present invention is characterized in that a change state of the count value within the unit time is recorded, and the frequency of the operation clock is changed according to the change state.

  According to the operation clock control method of the portable electronic device of the present invention, the path is constituted by a plurality of DMA channels, the FIFO is provided for each DMA channel, the number of times for each FIFO is counted, and the count value The priority of the DMA channel is changed according to the above.

  The operation clock control method for a portable electronic device according to the present invention is characterized in that when the frequency of the operation clock is changed, the word length of data transfer using the DMA channel is also changed.

  The operation clock control method of the portable electronic device of the present invention counts the remaining time of the reference period when the FIFO is used for each reference period, and calculates the frequency of the operation clock from the remaining time and the count value of the number of times. It is characterized by making a change.

  The operation clock control method for a portable electronic device according to the present invention provides the operation clock for transmitting / receiving one of data inside and outside the predetermined range when a predetermined range is set for the data to be transmitted / received. The frequency of the operation clock when the other data is exchanged is changed according to the count value of the number of times.

  The operation clock control method for a portable electronic device according to the present invention is characterized in that when the frequency of the operation clock is changed based on a predetermined function, the predetermined function is determined as a function using the count value as a variable. .

  The operation clock control method for a portable electronic device according to the present invention is configured so that each of the operation clock inside the LSI having the FIFO and the operation clock of the first component circuit outside the LSI is separately counted according to the count value. It is characterized by changing the frequency.

  The operation clock control method for a portable electronic device according to the present invention is characterized in that when the frequency change is performed, a time point at which the frequency change point is reached is counted by a pre-read timer, and the frequency change is performed immediately when the timer expires. .

  The operation clock control method for a portable electronic device according to the present invention is characterized in that the portable electronic device is a digital camera and the range of the predetermined range is changed according to a pressed state of a shutter button.

  The operation clock control method for a portable electronic device according to the present invention is characterized in that the portable electronic device is a digital camera and the range of the predetermined range is changed according to a detection signal of a touch sensor provided on a shutter button. .

  The operation clock control method for a portable electronic device according to the present invention is characterized in that the portable electronic device is a digital camera and the range of the predetermined range is changed in accordance with a detection signal of an eye sensor provided in a viewfinder.

  A portable electronic device according to the present invention includes a portable electronic device including a first component circuit, a second component circuit that exchanges data with the first component circuit, and a FIFO provided in a path for exchanging the data. The apparatus includes a control circuit that executes any one of the operation clock control methods described above by hardware.

  According to the present invention, part of the clock control is implemented as hardware, and the operation clock control is performed according to the load status monitored in real time, so that the development man-hours can be shortened and the software becomes complicated. Therefore, it is possible to further reduce the power consumption.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a functional block diagram of a portable electronic device, in the illustrated example, a digital camera according to an embodiment of the present invention. The digital camera 10 includes a photographic lens 11, a solid-state imaging device (for example, a CCD solid-state imaging device) 12 installed on the back of the photographic lens 11, and a preprocessing unit (analogue) that processes an output signal of the solid-state imaging device 12. Front end (AFE), analog-to-digital conversion (A / D, etc.) 13, digital still camera (DSC) LSI 14 placed in the subsequent stage, and ROM 16 and DRAM (SDRAM) 17 connected to LSI 14 via bus 15 And a rechargeable battery 18 that supplies power to each part of the digital camera 10.

  The DSC LSI 14 includes an image signal processing unit 21 that captures captured image data output from the preprocessing unit 13 and processes the image, a CPU 22 that performs overall control of the entire digital camera 10, and a memory control circuit 23 that will be described in detail later. And a clock control circuit 24 and a DMA controller (DMAC) 29.

  The image signal processing unit 21, CPU 22, and DMA controller 29 are interconnected by a DMA bus 25, the DMA controller 29 and memory control circuit 23 are connected by a signal line 25a, and the memory control circuit 23 is also connected to the bus 15 described above. Is done. The clock control circuit 24 is connected to the memory control circuit 23 and also to the CPU 22.

  The DMA bus 25 further includes an image compression / decompression processing unit 27, a media interface unit 28 for interfacing with an external storage medium, and an external communication control unit (USB) connected to an external personal computer (PC) or a printer. ) 30, an encoder / LCD signal processing unit 31 connected to a television monitor, a liquid crystal display unit, and the like, and an I / O port 32 are connected.

  The I / O port 32 is connected to a drive unit (not shown) of the photographic lens 11 and a drive unit (not shown) of the solid-state imaging device 12, and these are controlled by a drive signal from the CPU 22. The preprocessing unit 13 is connected to the CPU 22 via the serial I / O 33 and is driven and controlled by the CPU 22. Further, an I / O port 34 is connected to the CPU 22, for example, an instruction input signal from a user is taken into the CPU 22 through the I / O port 34.

  In the digital camera 10 having such a configuration, the CPU 22 reads and executes a program stored in the ROM 16, and the image signal processing unit (DSP) 21 performs image processing using the DRAM 17 serving as a main memory. The details of these image processes are the same as those in an ordinary digital camera.

  When each processing unit 21, 22, 27, 28, 30, 31 connected to the DMA bus 25 requires image data, a large amount of image data is transmitted and received between each processing unit and the DRAM 17. And the memory control circuit 23. At this time, the memory control circuit 23 monitors the load state of the bus 15 as will be described in detail later, and controls the clock control circuit 24 according to the monitoring result, so that the operation clock of each part, particularly the DRAM 17 in the present embodiment, is controlled. Control the frequency. That is, the operation clock is increased only when necessary, and the frequency of the operation clock is decreased when unnecessary to reduce power consumption.

  FIG. 2 is a configuration diagram of the memory control circuit (memory controller) 23. The memory control circuit 23 includes a large number of FIFOs (first-in first-out buffer memories) 41 and 42. As the digital camera has more functions, the number of FIFOs 41 and 42 is increased. Each FIFO 41 and 42 is connected to a selector (SEL) 43, and the selector 43 is connected to the DRAM 17 via the bus 15. The selector 43 is connected to a bus arbiter 44 that selects a FIFO to be connected to the DRAM 17.

  In the illustrated example, three FIFOs 41, that is, three channel (CH) buffer memories 41 are connected to a dedicated bus 47 (this dedicated bus 47 is not shown in FIG. 1), and three FIFOs 42, that is, three channels (CH ) Is connected to the DMA controller 29 by the data connection line 25a.

  The memory control circuit 23 of this embodiment is provided with a counter / sequencer 45 for monitoring the status of each FIFO 42, and the frequency of the operation clock supplied to each unit by the clock control circuit 24 is controlled by the monitoring result of the counter / sequencer 45. It is like.

  The FIFO 42 is a FIFO connected to the DMA controller 29, whereas the FIFO 41 is a FIFO connected to a dedicated bus 47. Data transmission / reception performed via the dedicated bus 47 is data transmission / reception via the CPU 22, and data transmission / reception performed via the DMA controller 29 is data transmission / reception not via the CPU 22. In the present embodiment, data transmission / reception without the CPU 22 is monitored, and the clock frequency of each unit is controlled according to the load status of the bus 15.

  In the example shown in FIG. 2, the counter / sequencer 45 shown in FIG. 2 includes a flag counter that counts the number of transitions to the full state or the number of transitions to the empty state of the 3CH FIFO 42, and according to the count result. A clock control unit that outputs a command to the clock control circuit 24. The count result of the flag counter is a measure of the degree of congestion of access to the memory (DRAM) 17 and represents the load on the bus 15.

  FIG. 3 is a flowchart showing a processing procedure performed by the counter / sequencer 45 shown in FIG. This flowchart is started each time various modes are selected or switched, such as whether the digital camera is powered on and set to a shooting mode or a playback mode.

  When activated, first, in step S1, initial setting of the memory drive mode, drive speed, drive timing, reference value, etc. of the DRAM 17 is performed. The reference value is a value used as a criterion for determining whether the DMA transfer task can be processed within the reference time or whether it is delayed without being processed. The value varies depending on the mode and also depends on the destination of the transfer request. change.

  In the next step S2, acceptance of a memory access request to the DRAM 17 by the CPU 22 or the DMA controller 29 is started, and in step S3, whether or not there is an actual request is waited.

  Hereinafter, the memory access from the CPU is performed through the FIFO 41 and the memory access from the DMA controller 29 is performed through the FIFO 42. Since the frequency of the memory access is higher from the DMA controller 29, the counter / sequencer 45 is The state of the FIFO 42 is monitored, and the operation clock of the DRAM 17 is controlled.

  If there is a request in step S3, it is first determined whether or not there is an empty channel in the three-channel FIFO 42 (step S4). If there is no empty channel, the process waits until an empty channel is created. If there is an empty channel, the process proceeds to step S5, and access to the FIFO 42 of the empty channel is started.

  Next, it is determined whether or not the access has been completed (step S6). If the access has been completed, the process returns to step S3. If not, the process proceeds to step S7 to determine whether or not the FIFO is full. If the FIFO is not full (determination result is NO), the process returns to step S5 to continue the memory access. If the FIFO is full (determination result is YES), the process proceeds to step S8, where the flag counter Count up the count value.

  After step S8, it is determined whether or not the FIFO is empty (step S9). If it is not empty, the process waits for a predetermined time (step S10) and then returns to step S9 again. Return to step S5.

  In steps S7 and S8, the number of transitions in which the FIFO is full (full) is counted. However, even if the number of transitions in which the FIFO is empty is counted, the count value is the memory access frequency, that is, the load on the bus Since it represents the situation, either may be counted.

  FIG. 4 is a flowchart showing a processing procedure performed by the clock control unit of the counter / sequencer 45. First, in step S11, the reference value is set to the initial setting value set in step S1 of FIG. 3, and in the next step S12, the count value n counted in step S8 is read.

  Then, it is determined whether or not the counted value n is “2” or more (step S13). If 2 ≦ n, it is determined that the access frequency is high, and the process proceeds to the next step S14 to reduce standby data. Accordingly, the operation clock frequency of the memory 17 is increased, and then in step S15, it is determined whether or not the reference period has expired, that is, whether or not the DMA transfer by the memory access is completed.

  In this way, the amount of standby data is determined in real time using the count value of the counter, and the clock frequency is controlled according to the amount of standby data, so control by software created based on prior experimental results, etc. Data transfer can be performed more quickly and efficiently.

  If the reference period has not expired as a result of the determination in step S15, it can be determined that the DMA transfer is in progress (using the FIFO 42), and the process returns to step S12. If the result of determination in step S13 is negative (NO), the process skips step S13 to step S14 and proceeds to step S15, and control for increasing the clock frequency is not performed.

  As a result of the determination in step S15, if it is determined that the reference period has expired and the current DMA transfer has been completed, the process proceeds to step S16, where the counter is reset to 0 (zero) and the clock frequency is returned to the original value. Proceed to step S11.

  In step S13, “2” is used as a criterion for the presence / absence of standby data. Needless to say, the value “2” can be changed as appropriate depending on the number of FIFOs 42 and the operation mode. The same applies to the following embodiments.

  FIG. 5 is a diagram when the operation clock frequency of the memory 17 is changed by applying the above-described control. In the example shown in the figure, the frequency of the operation clock of the DRAM 17 shown at the bottom is increased from a low frequency to a high frequency when one FIFO is full, and remains high when two FIFOs are full. When all three FIFOs become full, the frequency is further increased from the high frequency to the highest frequency, and when all the FIFOs are not full, the original low frequency is restored.

  In this way, by increasing the frequency of the operating clock only when it can be determined that the amount of standby data has increased, and by reducing the frequency of the operating clock when there is no or no standby data, low power consumption is achieved. Can be achieved.

(Second Embodiment)
FIG. 6 is a configuration diagram of the memory control circuit 23 according to the second embodiment of the present invention. Also in this embodiment, the basic control procedure is the same as in FIGS.

  In this embodiment, as in the embodiment of FIG. 2, the counter / sequencer 45 sends a clock control signal to the clock control circuit 24 based on the count value of the flag counter to control the clock frequency. The counter / sequence unit 45 holds the change width and the upper and lower limits as table data 51, and the clock control is performed with reference to the table data 51. Thereby, in this embodiment, optimization of a clock frequency becomes easy compared with 1st Embodiment.

  In the illustrated example, the table data 51 includes envelope data and clock frequency change parameter data, which will be described later in detail, and when the envelope data reaches a predetermined clock frequency change condition, the clock frequency is increased by a required value. Or to lower. The envelope data uses a default value immediately after the operation, but obtains the actual envelope data every predetermined period, overwrites the table data 51, and saves it as a log file. Used as default value in control.

  FIG. 7 is a flowchart showing an acquisition process procedure of envelope data actually created every predetermined period. First, in step S21, a reference period T is detected. The reference period T is, for example, the horizontal synchronization period HD or the vertical synchronization period VD shown in FIG.

  Next, a timer that counts the time t for dividing the reference period T into, for example, 10 is started (step S22) and waits for the timer to finish counting (step S23). While the timer counts the time t, the count value n of the flag counter counted up in step S8 of FIG. 3 is read (step S24), and this count value n is recorded as table data (step S25).

  In the next step S26, it is determined whether or not the reference period T has ended. If not, the above steps S22 to S25 are repeated, that is, the flag counter for each time t shown in FIG. The envelope data A in the reference period T can be obtained by obtaining the count value n.

  The envelope data A is created as a log file (step S27), stored, and rewritten with the above default values, thereby performing clock control that accurately and in detail reflects the actual bus congestion in the system operation. Is possible.

(Third embodiment)
FIG. 9 is a configuration diagram of the memory control circuit 23 according to the third embodiment of the present invention. In this embodiment, the basic control procedure is the same as in FIGS.

  The channels used for DMA transfer are 3 channels (CH) in the illustrated example, the counter / sequencer 45 also counts the individual access frequency for each channel, and the DMA controller 29 is instructed by the counter / sequencer 45. The channel priority is changed based on the access frequency for each channel. That is, as shown in FIG. 10A, when the access frequency of the second CH with the second highest priority is reached, the priority of the second CH is also 1 as shown in FIG. Change to number.

  FIG. 11 is a flowchart illustrating a processing procedure for changing the priority order. First, in step S31, the reference value initially set in step S1 of FIG. 3 is detected. In the next step S32, the count value n of the flag counter counted up in step S8 in FIG. 3 is read, and then the access frequency for each DMA channel is recorded (step S33).

  In the next step S34, it is determined whether or not the counter count value n is 2 ≦ n. If the determination is negative (NO), the process returns to step S32. If the determination is affirmative (YES), the clock frequency is increased in step S14 in FIG. 4, and the priority of the DMA channel is changed in accordance with the access frequency in step S35 in FIG.

  In the next step S36, it is determined whether or not the DMA transfer is completed. If the DMA transfer is not completed, it is determined whether or not the reference period corresponding to the reference value detected in the next step S31 has expired. (Step S37).

  If the DMA transfer has not been completed (determination result in step S36 is negative) and the reference period has not expired (determination result in step S37 is negative), the process returns to step S32. If the DMA transfer is not completed (determination result in step S36 is negative) and the reference period has expired (determination result in step S37 is affirmative), the process proceeds to step S38, and the flag counter is reset. At the same time, the DMA priority is returned to the default value, and then the process returns to step S31. If the result of determination in step S36 is that DMA transfer is complete, step S37 is skipped and processing proceeds to step S38.

  According to this embodiment, when the count value n of the flag counter becomes “2” or more, the clock frequency is changed, and the priority is changed in accordance with the access frequency of the DMA channel issuing the request. Therefore, further optimization can be achieved.

  In addition, since the clock is restored to the original time when the DMA transfer is completed, it is possible to save power consumption. Furthermore, when a plurality of DMA transfers are operating, the higher frequency setting is used. In addition, by providing a table for each combination of channels during a plurality of operations (for example, table data as in the second embodiment), the responsiveness can be further improved.

(Fourth embodiment)
FIG. 12 is a configuration diagram of the memory control circuit 23 according to the fourth embodiment of the present invention. The basic control procedure is the same as in FIG. 3, but in this embodiment, the processing procedure of FIG. 13 is used instead of FIG.

  The present embodiment shown in FIG. 12 includes a timer counter 53 that starts by acquiring the DMA transfer start timing from a timing generator (timing generator that generates the driving timing of the digital camera) 52 (not shown in FIG. 1). The counter / sequencer 45 is configured to output a clock control command to the clock control circuit 24 in accordance with the count value of the flag counter and the count value of the timer counter 53.

  In FIG. 13, first, in step S41, the reference value initialized in step S1 of FIG. 3 is acquired, and the timer counter 53 is started from the DMA transfer start timing. In the next step S42, the count value n of the flag counter is read, and in the next step S43, it is determined whether or not the count value n is 2 or more.

  If 2 ≦ n is not satisfied, the process proceeds to step S47. If 2 ≦ n is satisfied, the process proceeds from step S43 to step S44. This time, the count value Timer of the timer counter is equal to or greater than a predetermined set time K / 2. It is determined whether or not there is.

  When 2 ≦ n is satisfied, standby data is generated, and the timer count value does not count the predetermined set time, the process proceeds to step S45, where it is determined that time still remains and the clock The frequency is increased by one stage to increase the speed, and the process proceeds to step S47.

  When 2 ≦ n is satisfied, the standby data is generated, and the timer count value counts the predetermined set time, the process proceeds to step S46, and it is determined that the remaining time is short. The clock frequency is increased by two to increase the speed, and the process proceeds to step S47.

  That is, in this embodiment, when the FIFO standby state continues after a preset time, the clock frequency is further increased to a high speed, and DMA transfer is completed within a certain time to prevent processing failure. .

  In the next step S47, it is determined whether or not the DMA transfer is completed. If the DMA transfer is not completed, it is determined whether or not the reference period corresponding to the reference value detected in the next step S41 has expired. (Step S48).

  If the DMA transfer has not been completed (determination result in step S47 is negative) and the reference period has not expired (determination result in step S48 is negative), the process returns to step S42.

  When the DMA transfer is completed (the determination result in step S47 is affirmative) or the reference period has expired (the determination result in step S48 is affirmative), the process proceeds to step S49, where the flag counter is reset. The clock frequency is returned to the default value, and the process returns to step S41.

(Fifth embodiment)
FIG. 14 is a configuration diagram of a memory control circuit according to the fifth embodiment of the present invention. In the present embodiment, the counter / sequencer 45 counts the clock signal using a timing signal output from the timing generator 52, for example, a signal indicating the DMA transfer start timing as a trigger, and a frequency determination function (for example, FIG. 15) according to the counted value. And the clock frequency is controlled by this function and the count value n of the flag counter.

  For this reason, in this embodiment, a function determination circuit 54 is provided in the memory control circuit 23 and an output signal of the timing generator 52 is supplied to the counter / sequencer 45 and the function determination circuit 54.

  For example, when the function determination circuit 54 sets n1 to [flag counter count value + 1], n2 to the current clock number, N to the number of clocks in the reference period, fmax to the maximum frequency, and fmin to the minimum frequency, the graph of FIG. The frequency determination function is obtained by the mathematical formula described below.

  According to this embodiment, the clock control can be finely performed, the frequency can be changed smoothly, and electromagnetic radiation (EMI: Electro Magnetic Interference) can be reduced in addition to low power consumption.

(Sixth embodiment)
FIG. 16 is a configuration diagram of a memory control circuit according to the sixth embodiment of the present invention. The memory control circuit 23 of the present embodiment includes a window generation circuit 55 that takes in the horizontal synchronization signal (HD) and the vertical synchronization signal (VD) output from the timing generator 52, generates a window signal, and outputs the window signal to the counter / sequencer 45. Prepare.

  According to the present embodiment, when a television synchronization signal is applied as the reference value signal, the operation clock frequency can be changed between the blanking period of the horizontal synchronization signal and the vertical synchronization signal and the video period.

  As a result, high-speed processing can be concentrated on a specific two-dimensional area with low power consumption, and the peak of power consumption can be suppressed. In addition, the processing can be distributed in a space outside the image area, and noise can be reduced.

(Seventh embodiment)
FIG. 17 is a configuration diagram of a memory control circuit according to the seventh embodiment of the present invention. The memory control circuit 23 of this embodiment includes a CPU clock mode table 56 and an SDRAM clock mode table 57 in addition to the embodiment of FIG. 16, and the window generation circuit 55 outputs a window signal to the tables 56 and 57. The counter / sequencer 45 refers to the tables 56 and 57.

  In this embodiment, two systems of sequencers are provided so that the operation clock frequency supplied to the SDRAM 17 provided outside the LSI 14 and the operation clock frequency of the CPU 22 provided inside the LSI 14 can be independently controlled and output. .

  By setting the CPU clock frequency and SDRAM clock frequency to 1: 1 or 1: 2 inside and outside the window generated by the window generation circuit 55, for example, as shown in FIG. In this image processing mode and the image processing mode centered on data transfer, it is possible to finely change the control, further improving the image processing efficiency and reducing the power consumption.

  For example, when the window indicating the entire range of the subject image (the entire range including the vertical blanking period and the horizontal blanking period) is the first window, the range displayed on the liquid crystal display unit provided on the back of the camera or the like, The range to be displayed is not the entire first window but only a narrow range (a range excluding the blanking period or a range narrower than that: the second window). In this case, only data processing inside the second window, that is, data transfer is performed at high speed, and data transfer outside the second window is performed at low speed.

(Eighth embodiment)
FIG. 18 is a configuration diagram of a memory control circuit according to the eighth embodiment of the present invention. The memory control circuit 23 of the present embodiment includes a window generation circuit 55, and is configured to receive a switch signal of the shutter button 59 of the digital camera as an input signal to the window generation circuit 55.

  In this embodiment, a half-pressed state of the shutter button 59 that performs focus lock, exposure control, and the like is detected, and the parameter table to be used is changed before and after that. In the conventional digital camera, such control is performed by the CPU 22 by software control. However, by performing this control by hardware, a high-speed response can be achieved, and the feeling of camera operation can be eliminated.

  FIG. 19 is a flowchart illustrating a processing procedure of the control described above. First, in step S51, a clock is set for each default window, then an initial reference signal is detected (step S52), and the count value n of the flag counter is read (step S53).

  In the next step S54, it is determined whether the shutter button is in a half-pressed state, a fully-pressed state, or a non-pressed state. If not, the process returns to step S53.

  In the case of the half-pressed state, the process proceeds from step S54 to step S55, where the window is changed to the half-pressing window and changed to the clock frequency of the half-pressing window. In the fully-pressed state, the process proceeds from step S54 to step S56, where the window is changed to the fully-pressing window, and the clock frequency is changed according to the fully-pressing window.

  After steps S55 and S56, the process proceeds to step S57 to determine whether or not the DMA transfer is completed. If the DMA transfer has not been completed, it is next determined whether or not the period of the reference signal detected in step S52 has expired (step S58).

  If the DMA transfer has not been completed (determination result in step S57 is negative), and if the reference period has not expired (determination result in step S58 is negative), the process returns to step S57. When the DMA transfer is completed (the determination result in step S57 is affirmative) or the reference period has expired (the determination result in step S58 is affirmative), the process proceeds to step S59, where the flag counter is reset and the clock is transferred. The frequency is returned to the default value, and the process returns to step S51.

  As described above, since the clock frequency is changed by hardware depending on whether the shutter button is half-pressed or fully pressed, the response of the camera is improved.

(Ninth embodiment)
FIG. 20 is a flowchart showing an operation procedure of the memory control circuit according to the ninth embodiment. This embodiment is a modification of the eighth embodiment. In the eighth embodiment, the clock frequency is changed in the state of the shutter button, but in this embodiment, the clock frequency is changed in the detection state of the eye sensor provided in the finder.

  An eyepiece sensor is provided in the finder of the camera, and the clock frequency when processing inside the display window in the finder is changed depending on whether or not the user has looked into the finder.

  First, in step S61, the initial setting value of the reference signal is detected, and in the next step S62, the count value n of the flag counter is read. In the next step S63, it is determined whether or not the eyepiece sensor has detected the eyepiece state. If the eyepiece sensor is in the eyepiece state, the process proceeds to step S64, the operation clock frequency is increased, and then the process proceeds to step S65. Skips step S64 and proceeds to step S65.

  In step S65, it is determined whether or not the DMA transfer is completed. If the DMA transfer has not been completed, it is next determined whether or not the period of the reference signal detected in step S61 has expired (step S66).

  If the DMA transfer has not been completed (determination result in step S65 is negative), and if the reference period has not expired (determination result in step S66 is negative), the process returns to step S62. When the DMA transfer is completed (the determination result in step S65 is affirmative) or the reference period has expired (the determination result in step S66 is affirmative), the process proceeds to step S67, where the flag counter is reset and the clock is transferred. The frequency is returned to the default value, and the process returns to step S61.

  In this embodiment, an eye sensor is used as an example. However, a touch sensor may be provided on the shutter button, and different windows may be set depending on whether or not the touch sensor detects a touch of a finger.

  Although various embodiments have been described above, these embodiments can be applied in various ways. For example, it is possible to improve the data transfer efficiency by changing the word length during DMA transfer together with the change of the clock frequency from the access frequency for each DMA channel and the count value of the flag counter.

  Furthermore, although it has been explained that the clock frequency is changed when the change point of the window or the change point of the function is reached, when approaching these change points, the time point at which the change point is reached is predicted using a prefetch timer or the like, It is also possible to adopt a configuration in which the frequency is changed immediately without a time lag when the change point is reached.

  The operation clock control method and the like according to the present invention are useful when applied to a battery-driven portable electronic device because the operation state is detected in real time by hardware and the clock frequency is controlled.

1 is a functional block diagram of a digital camera according to a first embodiment of the present invention. FIG. 2 is a configuration diagram of a memory control circuit shown in FIG. 1. 3 is a flowchart showing an operation procedure of a counter / sequencer of the memory control circuit shown in FIG. 3 is a flowchart showing a frequency change processing procedure executed by a counter / sequencer of the memory control circuit shown in FIG. It is a figure explaining the mode of the frequency change of an operation clock. It is a block diagram of the memory control circuit which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement procedure which concerns on 2nd Embodiment of this invention. It is explanatory drawing of envelope data. It is a block diagram of the memory control circuit which concerns on 3rd Embodiment of this invention. It is explanatory drawing of the priority change of a DMA channel. It is a flowchart which shows the operation | movement procedure which concerns on 3rd Embodiment of this invention. It is a block diagram of the memory control circuit which concerns on 4th Embodiment of this invention. It is a flowchart which shows the operation | movement procedure which concerns on 4th Embodiment of this invention. It is a block diagram of the memory control circuit which concerns on 5th Embodiment of this invention. It is explanatory drawing of the function which concerns on 5th Embodiment of this invention. It is a block diagram of the memory control circuit which concerns on 6th Embodiment of this invention. It is a block diagram of the memory control circuit which concerns on 7th Embodiment of this invention. It is a block diagram of the memory control circuit which concerns on 8th Embodiment of this invention. It is a flowchart which shows the operation | movement procedure which concerns on 8th Embodiment of this invention. It is a flowchart which shows the operation | movement procedure which concerns on 9th Embodiment of this invention.

Explanation of symbols

14 LSI for digital still cameras
17 SDRAM
18 Rechargeable battery 22 CPU
23 Memory control circuit 24 Clock control circuit 25 DMA bus 29 DMA controller 41, 42 FIFO
43 selector 45 counter / sequencer 51 envelope data table 53 timer counter 54 function generator 55 window generation circuit

Claims (13)

  A portable device comprising a first component circuit, a second component circuit that exchanges data with the first component circuit, and a first-in first-out buffer memory (hereinafter referred to as FIFO) provided in a path for exchanging data. In the operation clock control method of an electronic device, the number of times the FIFO becomes full or empty within a unit time is counted, and the frequency of the operation clock of the first component circuit is changed according to the count value. An operation clock control method for a portable electronic device.   2. The operation clock control method for a portable electronic device according to claim 1, wherein a change state of the count value within the unit time is recorded, and the frequency of the operation clock is changed according to the change state. .   The path is composed of a plurality of DMA channels, the FIFO is provided for each DMA channel, the number of times for each FIFO is counted, and the priority of the DMA channel is changed according to the counted value. The operation clock control method for a portable electronic device according to claim 1, wherein:   4. The operation clock control method for a portable electronic device according to claim 3, wherein when changing the frequency of the operation clock, the word length of data transfer using the DMA channel is also changed.   2. The method according to claim 1, wherein when the FIFO is used for each reference period, the remaining time of the reference period is counted, and the frequency of the operation clock is changed based on the remaining time and the counted value. Item 5. The operation clock control method for a portable electronic device according to any one of Items 4 to 6.   When a predetermined range is set for the data to be exchanged, the operation clock for exchanging either the data inside or outside the predetermined range and the operation clock for exchanging the other data 6. The operation clock control method for a portable electronic device according to claim 1, wherein the frequency is changed according to the count value of the number of times.   7. When changing the frequency of the operation clock based on a predetermined function, the predetermined function is determined as a function using the count value as a variable. An operation clock control method for a portable electronic device.   2. The frequency of the internal operation clock of the LSI having the FIFO and the operation clock of the first component circuit that is external to the LSI are separately changed according to the count value of the number of times. Item 8. The operation clock control method for a portable electronic device according to any one of Items 7 to 8.   9. The frequency change according to claim 1, wherein when the frequency change is performed, a time point at which the frequency change point is reached is counted by a look-ahead timer, and the frequency change is immediately performed when the timer expires. An operation clock control method for a portable electronic device.   7. The operation clock control method for a portable electronic device according to claim 6, wherein the portable electronic device is a digital camera, and the range of the predetermined range is changed according to a pressed state of a shutter button.   7. The operation clock control of the portable electronic device according to claim 6, wherein the portable electronic device is a digital camera, and the range of the predetermined range is changed according to a detection signal of a touch sensor provided on a shutter button. Method.   7. The operation clock control method for a portable electronic device according to claim 6, wherein the portable electronic device is a digital camera, and the range of the predetermined range is changed in accordance with a detection signal of an eye sensor provided in a finder. .   A portable electronic device comprising: a first component circuit; a second component circuit that exchanges data with the first component circuit; and a FIFO provided in a path for exchanging the data. Item 13. A portable electronic device comprising a control circuit that executes the operation clock control method according to any one of Items 12 by hardware.

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