JPH1091268A - Clock frequency control method for semiconductor circuit and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the quantitative control of power consumption by calculating the power consumption corresponding to the clock frequency for control of the total power consumption of a system. SOLUTION: The A, B and C modules 3, 5 and 7 are connected together via the FIFO memories 2. 4, 6 and 8 which operate by different clocks whose input and output are asynchronous with each other. Then the clock frequency CLKA, CLKB and CLKC of modules 3, 5 and 7 are controlled by a clock control means 10. A power consumption calculation/comparison means 14 of the means 10 multiplies the frequency CLKA to CLKC supplied to the modules 2 to 8 by the table value corresponding to every module. These results of multiplication are added together for calculation of the total power consumption of a system. Thus, the quantitative control of power consumption is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method and a device for controlling a clock frequency of a semiconductor circuit, and more particularly to a method and a device for controlling a system clock for controlling power consumption in a semiconductor circuit.

[0002]

2. Description of the Related Art As a conventional system clock control technique, a configuration shown in FIGS. 6 and 7 can be considered. The data processing circuit 101 shown in FIG. 6 has a configuration in which input data D1 is processed in order by the A module 104 and the B module 105, and the processed data is sent out as output data D2, and the system clock is always constant. And a constant supply to all the modules at the same frequency (that is, the system clock is simply dripped).

That is, in FIG. 6, a clock signal SCK having a constant frequency generated by a clock generator 102 is shown.
Is connected to the A module 10 via the clock buffer 103.
4. Always supplied to the B module 105. Therefore, in this configuration, for example, the B module 10
Even if there is room for the processing in step 5, the clock is continuously supplied to the B module 105 unnecessarily, and as a result, there is a disadvantage that unnecessary power is consumed in the B module 105. As described above, the configuration in FIG. 6 does not include the function of reducing power consumption.

Therefore, as an improvement, FIG.
A configuration for performing system clock control based on an application mechanism as shown in FIG. That is, in the data processing circuit 110 shown in FIG. 7, the clock supply to the A module 104 and the B module 105 can be cut by the gate circuits 112 and 113. Further, the control of these gate circuits is performed by a control device (control circuit) 111 that operates based on a control signal A1 input from an external application mechanism (not shown), and applies gate circuit control signals GT1 and GT2 to the gate circuits 112 and 113, respectively. It is done by giving to. In such a configuration, if an external application mechanism predicts, for example, the state of the B module 105 or detects the state by some means, and data to be processed has not arrived at the B module 105,
The gate circuit 113 is stopped to stop the clock supply to the B module 105.

With the above-described configuration, unnecessary power consumption can be reduced by controlling the stop of the supply of the system clock as needed. When the gate circuits 112 and 113 are interposed in the transmission path, it becomes impossible to set the transmission path of the system clock to the same potential.
As a result, various problems such as waveform deterioration and delay of the system clock occur.

[0006] When the waveform of the system clock is degraded in this way, it takes time to take measures against it. Further, since the delay of the system clock increases in response to the increase in the load of the system clock accompanying the increase in the scale of the system, the transmission path of the system clock is variously changed in order to eliminate the delay. , And extra settings are required. Further, in a register arranged at an output stage of each operation module, a processing result is output in synchronization with a delayed system clock, and a problem that data is delayed correspondingly occurs. In addition to the problem that an expensive application mechanism is required and that the power consumption of the application mechanism itself occurs, there is a disadvantage that the load on the application program increases due to the prediction of the processing state of each module.

[0007] Therefore, an asynchronous FI is used between a plurality of modules.
Attempts have been made to connect with FO memories, control the frequency of the system clock for each module, and further provide a clock control circuit using an up / down counter for control. FIG. 8 shows a conventional example having such a configuration.
Shown in

[0008] The data processing device 120 shown in FIG.
Between the external input data D1 and the A module 104,
And between the A module 104 and the B module 105,
FIF whose input and output operate with separate asynchronous clocks
O memory (First InFirst Out Me)
memory) 121 and 122 are inserted. In the following, the FIFO memory is simply described as FIFO.
A clock CLK synchronized with the input data D1 is supplied from the clock generator 102 to the input clock of the FIFO 122.
It is supplied via a clock driver 103. FIFO1
22 output data clock terminal and A module 104
The clock CLK1 is supplied by the first clock control circuit 123 to the clock input terminal of the FIFO 122 and the input data clock terminal of the FIFO 122.

Further, separately from the clock CLK1, the clock CLK2 from the second clock control circuit 124
O122 output data clock terminal and B module 1
05 is supplied to the clock input terminal. Also FIFO1
21 and 122, a flag signal f1, such as a half empty flag, indicating the amount of data inside the FIFO,
f2 is output, the flag signal f1 is input to the first clock control circuit 123, and the flag signal f2 is input to the second clock control circuit 124.

In the case of such a configuration, an external clock passes through the clock driver 103, and receives the FIFO 121, the first clock control circuit 123, and the second clock control circuit 1.
24, the burden is light, and the skew can be reduced. This means that even when the number of modules increases, the number of clocks is higher than when clocks are supplied to all FFs (flip-flops).
This is due to the extremely small number (at most several tens).

On the other hand, the first clock control circuit 123 and the second
In the clock control circuit 124, each F signal is controlled by flag signals f1 and f2 (empty information) from the FIFO.
If the IFO is not in the full state, the clock frequency currently output is gradually reduced. As a result, the processing speed of the subsequent stage is reduced, the data stored in the FIFO is increased, and the power consumption in the subsequent stage during this period is reduced. When the data accumulated in the FIFO increases and approaches a full state, the clock frequency currently output is gradually increased to increase the processing speed of the subsequent stage.

As a clock control circuit, for example, the inside of the first clock control circuit 123 is configured as shown in FIG. The check cycle of the frequency conversion check for determining the response speed of the first clock control circuit 123 is performed at a frequency obtained by dividing the external clock by the frequency divider 220. Here, the frequency divider 220 can be a loadable frequency divider because the frequency division ratio can be programmably controlled from the outside.

The clock divided by the frequency divider 220 is input to a clock terminal of an up / down counter 221, and further, as a signal for controlling the up / down of the up / down counter 221, a half empty signal from the FIFO is sent. A signal comes in. Where half
Empty is a signal indicating that more than half of the data area of the FIFO is empty. Then, half-empty is checked at intervals of the cycle of the input clock cycle / frequency-divider of the frequency divider 220, and if it is half-empty, it counts up, and if it is not half-empty, it counts down. However, the down counter stops when the output becomes 0 for countdown, and stops when the output reaches the maximum value for countup.

The up / down output of the up / down counter 221 is provided by a PLL (phase locked loop).
This is input as the frequency division ratio of the frequency divider 222 which is the frequency divider of the input clock of the circuit. The PD 223 is a phase detector, the LF 224 is a loop filter, the VCO 225 is a voltage controlled oscillator, and the frequency divider 226 is a loop counter, constituting a series of PLL circuits. In particular, the output of the frequency divider 222 stops when the input of the frequency division ratio becomes a value 0. Here, the clock-out frequency is obtained by multiplying the clock-in frequency by the ratio between the frequency division ratio of the frequency divider 222 and the frequency division ratio of the frequency divider 226. At a minimum, control up to the stop is possible.

[0015]

In using a semiconductor device, it may be desirable to control power consumption suitable for various use situations. For example, when a notebook computer or the like is driven by a battery and the remaining amount of the battery becomes low, there is a case where it is desired to provide an environment that can be used for as long as possible even if the processing capacity is slightly reduced or reduced. Alternatively, instead of simply reducing power consumption, conversely, it is limited to short-time use, but when maximum function is required at the highest speed, maximum function is realized even at high power consumption Sometimes you want to. Further, for example, when the temperature of the system rises to a specified temperature or higher, it may be necessary to reduce the processing power and the power consumption to protect the system, thereby suppressing the temperature rise.

As described above, in spite of a demand to quantitatively control the power consumption in accordance with various purposes and applications according to the use conditions, the above-described conventional system clock control technique has the following problems. Such power consumption could not be quantitatively controlled to suit the purpose and application. The present invention has been made in order to solve such problems in the related art, and provides a clock frequency control method and apparatus capable of performing high-efficiency quantitative power consumption control suitable for the purpose and application in a semiconductor circuit. The purpose is to do.

[0017]

According to the present invention, there is provided a clock frequency control method for connecting a plurality of modules by an asynchronous FIFO and dynamically changing a system clock for each module. A method applied to a control system, the method including a step of calculating power consumption corresponding to a clock frequency for controlling power consumption of the entire system. With this configuration, quantitative control of power consumption according to the purpose and application is performed.

Alternatively, in the clock frequency control method according to the present invention, when the step of calculating the power consumption corresponding to the clock frequency in the clock control circuit is performed by multiplying a constant by the clock frequency, high-speed processing is performed. Becomes possible.

Alternatively, in the clock frequency control method according to the present invention, the step of calculating the power consumption corresponding to the clock frequency in the clock control circuit is performed by referring to a power consumption value table using the clock frequency as an address. In the case of the configuration, the access speed is increased, and the contents can be easily changed and updated.

Further, the frequency control method according to the present invention is applied to a system in which the remaining battery level is monitored, and has a step of defining an upper limit of power consumption when the remaining battery level becomes lower than a set value. In such a case, the power consumption is reduced by reducing the processing speed, so that the battery life is suppressed and the usable time is extended.

Further, the frequency control method according to the present invention is applied to a system whose temperature is monitored, and includes a step of defining an upper limit of power consumption when the system temperature exceeds a set temperature. The system is automatically protected by keeping the temperature below the specified value.

In the data processing apparatus according to the present invention, a clock control means for connecting a plurality of modules by an asynchronous FIFO and dynamically changing a system clock for each module controls power consumption of the entire system. And a means for calculating power consumption corresponding to the clock frequency. With this configuration, quantitative control of power consumption according to the purpose and application can be performed.

In the data processing apparatus according to the present invention, when the clock control means is configured to calculate power consumption corresponding to a clock frequency by multiplying a constant by a clock frequency, high-speed processing is performed. Done.

In the data processing apparatus according to the present invention, the means for calculating the power consumption corresponding to the clock frequency provided in the clock control means is constituted by a referenceable power consumption value table using the clock frequency as an address. Access speed will be faster,
Updates are easier.

Further, the data processing apparatus according to the present invention includes a battery remaining amount monitoring unit, and the clock control unit includes a power consumption upper limit setting unit, and when the battery remaining amount becomes smaller than the set value, the power consumption becomes lower. In the case where the upper limit setting means updates the upper limit of the power consumption, the clock frequency is reduced to reduce the power consumption, so that the battery consumption is suppressed and the usable time is extended.

Further, the data processing apparatus according to the present invention includes a temperature monitoring means, and the clock control means includes a power consumption upper limit setting means. In the case of updating the upper limit, the clock frequency is reduced, the temperature is kept below the specified value, and the device is automatically protected.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The main point of the clock frequency control method according to the present invention is that a plurality of modules are connected by an asynchronous FIFO, and the FIFO status is monitored by checking the FIFO empty state.
And controls the frequency of the system clock of each module connected to the output side of the system. In a system having a clock control circuit using an up / down counter,
When a target reduction in power consumption is given, the clock frequency is controlled by controlling an up / down counter to realize the reduction in power consumption.

Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a block diagram of an embodiment of a data processing device according to the present invention. FIG. 2 is a block diagram of an embodiment (power consumption calculation by constant multiplication) of the power consumption calculation / comparison means shown in FIG. FIG. 3 is an operation timing chart of the power consumption calculation / comparison means of FIG.

As shown in FIG. 1, a data processing apparatus 1 according to the present invention has a FIFO memory (hereinafter, referred to as FIFO) in which input and output are operated by different asynchronous clocks.
A module 3, B module 5, and C module 7 are connected by using 2, 4, 6, and 8,
Controls the clock frequencies CLKA, CLKB, and CLKC of the A module 3, the B module 5, and the C module 7.

The input data D1 from the outside is stored in the FIFO2
Clock C supplied to the input data clock terminal of
After being stored in the FIFO 2 in synchronization with the LKI, it is released to the A module 3, processed by the A module 3, stored in the FIFO 4, then released to the B module 5, and processed by the B module 5. The data is stored in the FIFO 6 and then released to the C module 7, processed in the C module 7, stored in the FIFO 8, and finally stored in the FIFO 8.
From FO8, the output data D is synchronized with the clock CLKO.
Sent as 2.

A clock terminal for the output data of the FIFO 2, a clock input terminal of the A module 3,
A clock CLK for the input data clock terminal of O4
A is supplied by an A clock control circuit (ACLKG) 11.

Further, a clock terminal for output data of the FIFO 4, a clock input terminal of the B module 5,
The clock C for the input data clock terminal of the FIFO 6
LKB is supplied by a B clock control circuit (BCLKG) 12, and a clock terminal for output data of the FIFO 6, a clock input terminal of the C module 7, and an FI
The clock terminal for input data of FO8 has a clock CL
KC is supplied by a C clock control circuit (CCLKG) 13.

From the FIFOs 2, 4, 6, and 8, flag signals g2 to g8 indicating the amount of data in the FIFO, such as a half empty flag, are output and input to the clock control means 10.

In the case of such a configuration, the external clock CLKI is supplied to the FIFO 2 and the A clock control circuits 11 to 11.
Since it is only supplied to the C clock control circuit 13, the burden is light, and thus the skew can be suppressed.

On the other hand, in the A clock control circuit 11 to the C clock control circuit 13, if each FIFO is not in the full state, the clock frequency currently output is gradually reduced according to the empty information from the FIFO. . As a result, the processing speed of the subsequent stage is reduced, the data stored in the FIFO is increased, and the power consumption in the subsequent stage during this period is reduced. When the data accumulated in the FIFO increases and approaches a full state, the clock frequency currently output is gradually increased to increase the processing speed of the subsequent stage. The A clock control circuit 11 to the C clock control circuit 13 have a configuration as shown in FIG.

FIG. 2 is a block diagram of an embodiment (calculation of power consumption by constant multiplication) of the power consumption calculation and comparison means shown in FIG. FIG. 3 is an operation timing chart of the power consumption calculation / comparison means of FIG. The power consumption calculation / comparison means 14 having the configuration shown in FIG. 2 includes tables 35 and 36 in which the ratios of the operating frequencies CLKA, CLKB, and CLKC of each module and the power consumption of each module are entered.
37, the clock frequency supplied to each module is multiplied by a table value corresponding to each module, and all the multiplication results of each module are added to obtain the power consumption of the entire system.

First, the outputs of the tables 35, 36, and 37 holding the ratio of the power consumption to the clock frequencies CLKA, CLKB, and CLKC for each of the A to C modules enter the MUX (multiplexer) 39. Furthermore, A
To the clock frequency CLK for each of the C modules
A, CLKB, CLKC are MUX (multiplexer) 3
Enter 8. From the input values to these MUXs 38 and 39, only the signal of the corresponding module among A, B and C is selectively output by the sel signal. This MU
The outputs of X38 and X39 are multiplied by a multiplier (MPY) 40, and the multiplication result and 0 when the control signal zero is 1
The output from the Zero circuit 41 that performs (zero) output is added in the adder 42, and LT is output by the control signal clk.
C (latch circuit) 43 holds.

The output of the LTC 43 is fed back to the Zero circuit 41. When the control signal zero is 0 (zero), the value is input to the adder 42 as it is. In this way, the output of the LTC 43 is set to L level by the control signal ltc.
The value is stored in a TC (latch circuit) 44 as an added value.
Next, the output of the LTC 44 and the power consumption upper limit value Uc are input to the comparator 45, where the magnitude is compared, and the result is output as the comparison value CpOut to the A clock control circuits 11 to C clock control circuit 13.

With such a connection, as shown in the timing chart of FIG. 3, clk, zero, and se
By generating various signals of IA, selB, selC, and ltc, it is possible to monitor whether the power consumption exceeds a preset power consumption. This comparison value CpOu
By using a signal obtained by performing a logical OR operation with the half empty signal controlling the count up and down in the circuit for generating the clock of each module using t for the up and down control of the counter, the power consumption becomes the set value. When the clock frequency becomes larger than the above, the control can be performed in a direction to lower the entire clock frequency. Conversely, when the power consumption becomes smaller than the set value, it is possible to control to increase the overall clock frequency.

FIG. 4 is a block diagram of another embodiment (power consumption calculation based on a power consumption value table) of the power consumption calculation / comparison means shown in FIG. FIG. 5 is an operation timing chart of the power consumption calculation / comparison means of FIG.
In the power consumption calculation / comparison means 60 having the configuration of FIG. 4, the operating frequencies CLKA, CLKB, CL
Tables 46, 47 and 48 containing power consumption values for each module, which are almost determined by KC, are prepared, and power consumption values corresponding to clock frequencies supplied to each module are prepared from the tables 46, 47 and 48. By calculating and adding all the obtained power consumption values, the power consumption of the entire system is obtained.

First, the outputs of the tables 46, 47 and 48 holding the power consumption values for the clock frequencies CLKA, CLKB and CLKC for the respective A to C modules enter the MUX (multiplexer) 49. This MUX4
9 from the respective input values to A,
Only the signal of the corresponding module of B and C is selectively output. The output of the MUX 49 and the control signal ze
The output from the Zero circuit 50 that outputs 0 (zero) when rob is 1 is added in the adder 51 and is held in the LTC (latch circuit) 52 by the control signal clkb. The output of the LTC 52 is fed back to the Zero circuit 50. When the control signal zerob is 0 (zero), the value as it is is input to the adder 51. In this way, the output of the LTC 52 is controlled by the LTC signal in accordance with the control signal ltcb.
(Latch circuit) 53 holds the sum as an added value. Next, the output of the LTC 53 and the power consumption upper limit Uc are
4 and compared in magnitude, the result is a comparison value Cp
The signal is output to the A clock control circuit 11 to the C clock control circuit 13 as Outb.

With such a connection, as shown in the timing chart of FIG. 5, clkb, zerob,
By generating various signals selA, selB, selC, and ltcb, it is possible to monitor whether the power consumption exceeds a preset power consumption. This comparison value C
The power consumption is set to a set value by using a signal obtained by performing an OR operation with a half empty signal for controlling the count up and down in a circuit for generating a clock of each module using pOutb for a counter up / down control. When the clock frequency becomes larger than the above, the control can be performed in a direction to lower the entire clock frequency. Conversely, when the power consumption becomes smaller than the set value, it is possible to control to increase the overall clock frequency.

Further, in addition to the above-described configuration including the power consumption calculating / comparing means 14 or 60, as shown in FIG. A configuration including the amount monitoring means 16 may be adopted. In this system, the power consumption upper limit setting means 15 is configured to lower the power consumption upper limit Uc based on a signal 16a from the battery remaining amount monitoring means 16 corresponding to the battery remaining amount used by the system. According to such a configuration, when the charged amount decreases while monitoring the remaining battery power used by the system, the clock frequency is reduced by lowering the power consumption upper limit Uc, and thus the processing capacity of the system is reduced. It is very convenient when you want to extend the usage time as much as possible by using the remaining battery.

Further, in addition to the above-described configuration including the power consumption calculating / comparing means 14 or 60, as shown in FIG. 1, a power consumption upper limit setting means 15 and a temperature monitoring means 17 for monitoring the temperature are provided. In the system provided, a signal 17a corresponding to the temperature of the system from the temperature monitoring means 17 is provided.
, The power consumption upper limit setting means 15 may reduce the power consumption upper limit Uc. With such a configuration, by monitoring the temperature of the system, it is possible to control the power consumption in a direction to reduce the power consumption at the very point where the system is destroyed due to the temperature rise, so that the capacity of the system can be utilized to the maximum.

[0045]

As described in detail above, claim 1 of the present invention
The clock frequency control method according to the present invention is applied to a clock control system in which a plurality of modules are connected by an asynchronous FIFO and a system clock of each module is dynamically changed, and a clock for controlling power consumption of the entire system. Since the configuration includes the step of calculating the power consumption corresponding to the frequency, quantitative control of the power consumption according to the purpose and application can be performed.

In the frequency control method according to the second aspect of the present invention, the step of calculating power consumption corresponding to the clock frequency in the clock control circuit is performed by multiplying a constant by the clock frequency.
There is an effect that high-speed processing can be performed.

In the frequency control method according to a third aspect of the present invention, the step of calculating the power consumption corresponding to the clock frequency in the clock control circuit is performed by referring to a power consumption value table using the clock frequency as an address. Therefore, there is an effect that the access speed is high and the contents can be easily changed / updated.

The frequency control method according to claim 4 of the present invention is applied to a system for monitoring the remaining battery power, and defines an upper limit of power consumption when the remaining battery power becomes smaller than a set value. Since it has steps, there is a remarkable effect that the processing speed can be reduced to reduce power consumption, thereby reducing battery consumption and extending usable time.

A frequency control method according to a fifth aspect of the present invention is applied to a system whose temperature is monitored, and has a step of defining an upper limit of power consumption when the system temperature exceeds a set temperature. Therefore, there is an effect that the temperature is kept below the specified value and the system is automatically protected, so that a system with excellent reliability can be realized.

According to a sixth aspect of the present invention, in the data processing apparatus, a plurality of modules are connected by an asynchronous FIFO, and clock control means for dynamically changing a system clock of each module includes a power consumption of the entire system. And a means for calculating the power consumption corresponding to the clock frequency for controlling the power consumption. Therefore, the quantitative control of the power consumption according to the purpose and application becomes possible.

According to a seventh aspect of the present invention, there is provided a data processing apparatus comprising: the clock control means according to the sixth aspect for calculating power consumption corresponding to a clock frequency.
Since it is configured by multiplying a constant and a clock frequency, there is an effect that high-speed processing can be performed.

The data processing apparatus according to claim 8 of the present invention is characterized in that the clock control means of claim 6 calculates power consumption corresponding to a clock frequency.
Since it is constituted by a referenceable power consumption value table using the clock frequency as an address, there is an effect that the access speed is high and the contents can be easily changed and updated.

According to a ninth aspect of the present invention, in the data processing device according to the sixth, seventh or eighth aspect, the data processing apparatus further includes a battery remaining amount monitoring unit and a power consumption upper limit setting unit, and the clock control unit includes a battery control unit. When the remaining amount becomes smaller than the set value, the power consumption upper limit setting means sets the lower power consumption upper limit value, so that the processing speed is reduced to reduce the power consumption, thereby suppressing the consumption of the battery. There is a remarkable effect that the usable time can be extended.

According to a tenth aspect of the present invention, in the data processing apparatus according to the sixth, seventh or eighth aspect, a temperature monitoring means and a power consumption upper limit setting means are provided, and the temperature is set by the clock control means. When the temperature is exceeded, the power consumption upper limit setting means sets the power consumption upper limit to a low value, so that the clock frequency is reduced and the temperature is kept below the specified value, thereby automatically protecting the device. There is an effect that a highly reliable data processing device can be realized.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram of an embodiment of a data processing device according to the present invention.

FIG. 2 is a block diagram of an embodiment (power consumption calculation by constant multiplication) of the power consumption calculation / comparison means shown in FIG. 1;

FIG. 3 is an operation timing chart of the power consumption calculation / comparison means of FIG. 2;

FIG. 4 is a block diagram of another embodiment (power consumption calculation based on a power consumption value table) of the power consumption calculation / comparison means shown in FIG. 1;

FIG. 5 is an operation timing chart of the power consumption calculation / comparison means of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration example of a conventional data processing device.

FIG. 7 is a block diagram showing a configuration example of another conventional data processing device.

FIG. 8 is a block diagram showing a configuration example of another conventional data processing apparatus.

FIG. 9 is a block diagram showing a configuration of a first clock control circuit shown in FIG.

[Explanation of symbols]

1. Data processing device according to the present invention, 2. FIFO,
3 ... A module, 4 ... FIFO, 5 ... B module, 6 ... FIFO, 7 ... C module, 8 ... F
IFO, 10 clock control means, 11 A clock control circuit, 12 B clock control circuit, 13 C
Clock control circuit, 14... Power consumption calculation comparing means, 1
5 ... power consumption upper limit setting means, 16 ... battery remaining amount monitoring means, 17 ... temperature monitoring means

Claims (10)

[Claims] 1. A method applied to a clock control system in which a plurality of modules are connected by an asynchronous FIFO and a system clock of each module is dynamically changed, for controlling power consumption of the entire system. Calculating a power consumption corresponding to the clock frequency of the clock frequency. 2. The step of calculating power consumption corresponding to a clock frequency in the clock control circuit,
2. The clock frequency control method according to claim 1, wherein the method is performed by multiplying a constant by a clock frequency. 3. The step of calculating power consumption corresponding to a clock frequency in the clock control circuit,
2. The clock frequency control method according to claim 1, wherein the control is performed by referring to a power consumption value table using the clock frequency as an address. 4. A method applied to a system for monitoring the remaining battery power, the method comprising a step of defining an upper limit of power consumption when the remaining battery power becomes lower than a set value. 4. The clock frequency control method according to claim 1, wherein the clock frequency is controlled. 5. A method applied to a system whose temperature is monitored, comprising a step of defining an upper limit of power consumption when the system temperature exceeds a set temperature. 4. The clock frequency control method according to 2 or 3. 6. A data processing apparatus comprising: a plurality of modules connected by an asynchronous FIFO; and a clock control unit for dynamically changing a system clock of each module, wherein the clock control unit is configured to control an entire system. A data processing device comprising: means for calculating power consumption corresponding to a clock frequency for controlling power consumption. 7. The data processing apparatus according to claim 6, wherein the means for calculating the power consumption corresponding to the clock frequency in the clock control means is configured by multiplying a constant by the clock frequency. 8. The clock control means for calculating the power consumption corresponding to the clock frequency is configured by referring to a power consumption value table using the clock frequency as an address. 7. The data processing device according to 6. 9. A data processing device comprising a battery remaining amount monitoring means, wherein said clock control means comprises a power consumption upper limit setting means for defining an upper limit of power consumption, and said power consumption upper limit setting means comprises: 9. The data processing device according to claim 6, wherein an upper limit of power consumption is updated based on a monitoring result of the amount monitoring unit. 10. A data processing device comprising a temperature monitoring means, wherein said clock control means comprises a power consumption upper limit setting means for defining an upper limit of power consumption, and said power consumption upper limit setting means comprises a power consumption upper limit setting means. 9. The data processing apparatus according to claim 6, wherein an upper limit of power consumption is updated based on a monitoring result.