JP2000286702A - Synchronous clock generation circuit and clock switch device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the influence of the expected fluctuation of an outer clock by transmitting a digital value generated in an inner memory to a voltage control oscillator instead of a digital value generated from the phase difference of outer and inner clocks in a period when the outer clock is abnormal. SOLUTION: The phase frequency comparison circuit 11 of a synchronous clock generation part 6 compares the phases of a selected outer clock and that of an inner clock 4 and sends the result to a digital value generation circuit 12. The digital value generation circuit, 12 generates a digital value corresponding to a phase difference and sends it to a voltage control oscillator 14. A holding over circuit 17 is provided with a memory and it sequentially stores filtering data sampled in the memory. When the abnormality of frequency fluctuation occurs in the outer clock, a control circuit 23 sends a holding over signal to the holding over circuit 17. The holding over circuit 17 reads data which are timewise ascended from the memory and sends it to the voltage control oscillator 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generating circuit for generating an internal clock signal synchronized with an external clock signal and a clock switching device using the same. An internal clock with a very stable period can be generated,
The present invention relates to a synchronous clock generation circuit that can be suitably used in an optical communication device that performs high-speed communication with an optical cable or the like, and a clock switching device using the same.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing the configuration of a conventional clock switching device disclosed in Japanese Patent Application Laid-Open No. 5-243980. In the figure, reference numeral 1 denotes an external clock signal transmitted from an optical cable or the like, and 2 denotes a plurality of external clock signals 1...
A selection unit for selecting one and outputting it as a selected clock signal,
5, a plurality of external clock signals 1... 1 are input, a selection signal for selecting one of them is output to the selection unit 2, and an abnormality of the selected external clock signal 1 is detected. While detecting the abnormality, an external clock monitoring unit that outputs an abnormality detection signal, 9 is an input divider that divides the selected clock signal by 1 / N1 (N1 is an integer), and 10 is an internal clock signal 4 An output divider that divides the frequency by 1 / N2 (N2 is an integer), 51 compares the phases of the divided external clock signal 1 and internal clock signal 4 with each other, and outputs data corresponding to the phase difference. Phase comparison circuit that outputs
Reference numeral 2 denotes a digital low-pass filter that performs a filtering process based on a plurality of data output from the phase comparison circuit 51 to generate digital data according to the phase difference. Reference numeral 53 denotes an abnormality detection signal from the external clock monitoring unit 5. A latch circuit for latching the digital data when input, a D / A converter circuit 13 for converting the digital data into an analog voltage value, a voltage control oscillator 14 oscillating at a frequency corresponding to the analog voltage value, The output of the voltage controlled oscillator 14 is the internal clock signal 4.

Next, the operation will be described. The selection unit 2 selects one of the plurality of external clock signals 1... 1 based on the selection signal from the external clock monitoring unit 5, and the input frequency divider 9 divides the frequency of the external clock signal 1. 51 is output. Then, the internal clock signal 4 corresponding to this input
Is output, the phase comparison circuit 51 compares these phase differences and outputs data according to the phase difference, the digital low-pass filter 52 performs a filtering process based on the plurality of data, and the latch circuit 53 Let this pass through,
The D / A conversion circuit 13 outputs an analog voltage corresponding to the data, and the voltage controlled oscillator 14 outputs the internal clock signal 4 having a frequency corresponding to the analog voltage.

In the state where the internal clock signal 4 synchronized with the external clock signal 1 is generated, when the external clock monitoring unit 5 detects an abnormality of the external clock signal 1, the external clock monitoring unit 5 Outputs a latch signal, and the latch circuit 53 responds to the latch signal.
Holds the digital data at that time.

As described above, the conventional synchronous clock generation circuit is provided with the latch circuit 53 for holding the state in the phase locked loop, and the latch circuit 5 for holding the state.
By holding the state immediately before at 3, even if an abnormality occurs in the external clock signal 1, the predetermined internal clock signal 4 can be continuously generated.

FIG. 11 is a block diagram showing a configuration of another conventional clock switching device disclosed in the publication.
This circuit has a configuration in which a fixed oscillator 54, a frequency difference comparison circuit 55, and an addition / subtraction circuit 56 are added to the configuration of the conventional clock switching device. Then, the frequency difference comparing circuit 55 compares the data of the reference frequency output from the fixed oscillator 54 with the data output from the latch circuit 53, and outputs a correction signal so that these frequency differences become constant. The circuit 56 performs this correction processing.
Therefore, even if an abnormality occurs in the external clock signal 1 as in the conventional clock switching device, a predetermined internal clock signal 4
Can be continuously generated, and the frequency can be stabilized irrespective of temperature fluctuation.

FIG. 12 is a block diagram showing a configuration of a third conventional clock switching device disclosed in Japanese Patent Application Laid-Open No. 9-93237. In the figure, 57 is a quantization circuit, 58 is a memory, and 59 is an analog low-pass filter. Then, the quantization circuit 57 quantizes the data corresponding to the phase difference output from the phase comparison circuit 51, and
8 stores a plurality of quantized data and D /
Output to the A conversion circuit 13 and the analog low-pass filter 5
9 smoothes the analog voltage output from the D / A conversion circuit 13. Therefore, when the external clock signal 1 is normal, the internal clock signal 4 is synchronized by the PLL loop. On the other hand, if the external clock signal 1 becomes abnormal, writing to the memory 58 is prohibited, and the memory 58 continues to output phase difference information when the external clock signal 1 is normal. As a result, a predetermined internal clock signal 4 can be continuously generated even if an abnormality occurs in the external clock signal 1 as in the conventional clock switching device.

[0008]

Since the conventional clock switching device is configured as described above, the digital value in the digital phase locked loop is held according to the abnormality detection output of the external clock monitoring unit 5. The digital phase locked loop holds a signal synchronized with the clock state immediately before the abnormality is detected. As a result, for example, if there is a predictive change between the time when the external clock signal 1 starts to fluctuate from a predetermined frequency and the time when the external clock signal 1 enters the hold state, the external clock signal 1 is synchronized with the external clock signal 1 in the predictive fluctuation state. There were issues such as letting them do it.

To eliminate this effect, it is conceivable to set a large time constant of the digital phase locked loop. However, if the time constant is set in this way, the synchronization pull-in characteristic is similarly degraded. Therefore, the above-mentioned problem at the time of the clock abnormality cannot be solved while maintaining the synchronization pull-in characteristic.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is intended to synchronize with an external clock signal 1 which is in a predictive fluctuation state when the external clock signal 1 is abnormal, without deteriorating the synchronization pull-in characteristic. It is an object of the present invention to obtain a synchronous clock generation device capable of suppressing the occurrence of a clock and a clock switching device using the same.

[0011]

A synchronous clock generation circuit according to the present invention is a synchronous clock generation circuit for generating an internal clock signal synchronized with an external clock signal, wherein the external clock signal is compared with the internal clock signal. A comparison circuit that outputs an analog value according to the phase difference; a digital value generation circuit that converts the analog value into a digital value to generate digital data according to the phase difference; An oscillator that oscillates the internal clock signal having a frequency corresponding to the value of the external clock signal; an external clock monitoring unit that detects an abnormality of the external clock signal and outputs an abnormality detection signal while detecting the abnormality; During the period when the detection signal is input and the abnormality detection signal is input, the digital data generated by the digital value generation circuit is output. Warini digital data generated inside is obtained and a control circuit for input to the oscillator.

A synchronous clock generation circuit according to the present invention comprises:
An external clock signal and an internal clock signal are input, and a phase difference monitoring unit that outputs a switching signal when the phase difference exceeds a predetermined allowable range of phase fluctuation is provided. Is to increase or decrease the digital data input to the oscillator during the period when the abnormality detection signal is being input.

A synchronous clock generation circuit according to the present invention comprises:
A digital value generation circuit that samples an analog value and outputs sampling data; a digital low-pass filter that performs low-pass filtering using a plurality of continuous sampling data and outputs filtering data; and And a holdover circuit for selecting one of the internally generated digital data based on the abnormality detection signal and outputting the selected data to the oscillator.

A synchronous clock generation circuit according to the present invention comprises:
A holdover circuit, a memory for storing the filtering data, a hold clock determination circuit for comparing the data stored in the memory with the filtering data, and outputting an increase / decrease signal in accordance with a difference therebetween; A counter that outputs count data that sequentially increases or decreases while the increase / decrease signal is being input; a latch circuit that latches the filtering data; An adder / subtractor circuit for adding the count data to the data latched in the circuit, and outputting the output of the adder / subtractor circuit to the oscillator.

A synchronous clock generation circuit according to the present invention comprises:
The memory and the counter operate based on a clock having a longer cycle than the hold clock determination circuit.

A synchronous clock generation circuit according to the present invention comprises:
A holdover circuit for storing a filtering data, a memory for storing the filtering data, a hold clock determining circuit for comparing the data stored in the memory with the filtering data, and outputting an increase / decrease signal in accordance with a difference between them; A hold signal generation circuit that inverts the increase / decrease signal to generate a hold signal during a period in which the abnormality detection signal is input and a period in which the increase / decrease signal and the hold signal are input and the hold signal is not input An up-down counter that outputs the filtered data as it is to the oscillator as it is, and holds the data immediately before the hold signal is input, and outputs the increased or decreased data to the oscillator based on the increase / decrease signal. It is provided.

The synchronous clock generation circuit according to the present invention comprises:
The memory and the up / down counter operate based on a clock having a longer cycle than the hold clock determination circuit.

A synchronous clock generation circuit according to the present invention comprises:
The memory sequentially stores a plurality of latest filtering data, and outputs the oldest data to the hold clock determination circuit each time a clock is input.

The synchronous clock generation circuit according to the present invention comprises:
A digital value generation circuit that samples an analog value and outputs sampling data, a memory that stores a plurality of continuous sampling data,
A digital low-pass filter that selects one of the output of the sampling circuit and the output of the memory based on the abnormality detection signal and performs low-pass filtering to output filtering data; and inputs the output of the low-pass filter to an oscillator. Is what you do.

The synchronous clock generation circuit according to the present invention comprises:
An analog low-pass filter is provided between the comparison circuit and the digital value generation circuit, and the digital value generation circuit controls the digital low-pass filter to a non-operating state during synchronization.

A clock switching device according to the present invention comprises: a selector for selecting one external clock signal from a plurality of external clock signals; and a synchronous clock for receiving one external clock signal selected by the selector. And a generation circuit.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a clock switching device according to Embodiment 1 of the present invention. In the figure, 1 is an external clock signal transmitted from an optical cable or the like, 2 is a plurality of external clock signals, and 2 is a selecting unit that selects one of them and outputs it as a selected clock signal. A synchronous clock generation circuit 4 for generating an internal clock signal 4 synchronized with the selected clock signal is an internal clock signal.

In the synchronous clock generation circuit 3, a plurality of external clock signals 1... 1 are input to the synchronizing clock generation circuit 3, and a selection signal for selecting one of them is output to the selection unit 2, and the selected clock is selected. An external clock monitoring unit that detects an abnormality of the external clock signal 1 and outputs an abnormality detection signal while the abnormality is detected. The external clock monitoring unit 6 receives the selected clock signal and generates an internal clock signal 4 synchronized with the selected clock signal. The synchronous clock generator 7 receives the selected clock signal and the internal clock signal 4 and monitors the magnitude of the phase difference. The phase jump monitor monitors the phase difference. The reference numeral 8 denotes the phase jump monitor. And a phase jump direction switching unit (phase difference monitoring unit) that outputs a switching signal when the phase difference exceeds a predetermined allowable range of phase fluctuation. So that the switch their operation in response to the abnormality detection signal and the switching signal.

FIG. 2 is a block diagram showing a configuration of the synchronous clock generator 6 according to the first embodiment of the present invention. In the figure, 9 is an input divider for dividing the selected clock signal by 1 / N1 (N1 is an integer) and 10 is the internal clock signal 4
An output frequency divider that divides 1 / N2 (N2 is an integer), 11
Is a phase frequency comparison circuit (comparison circuit) that compares phases of the divided external clock signal 1 and internal clock signal 4 and outputs a pulse (analog value) having a pulse width corresponding to the phase difference. And 12 are digital value generation circuits that sample the pulse and generate digital data basically corresponding to the phase difference, 13 are D / A conversion circuits that convert the digital data into analog voltage values, and 14 Is a voltage controlled oscillator (oscillator) that oscillates at a frequency corresponding to the analog voltage value, and the output of the voltage controlled oscillator 14 becomes the internal clock signal 4.

In the digital value generation circuit 12, reference numeral 15 denotes a quantization circuit (sampling circuit) for sampling a pulse and outputting sampling data having a value corresponding to the pulse width. A digital low-pass filter that performs a low-pass filtering process using a plurality of output sampling data and outputs filtering data, and a D / A converter 17 selects one of the filtering data and internally generated digital data to perform D / A conversion This is a holdover circuit that outputs to the circuit 13. Incidentally, reference numeral 18 denotes these circuits 1
It is a fixed oscillator that outputs a sampling clock signal to 5, 16, and 17.

An unlock detecting circuit 21 receives sampling data, and outputs an unlock signal when the integrated value of the sampling data exceeds a predetermined allowable range of phase fluctuation (such as a threshold value). The system reset circuit 23 for detecting the power-on of the system including the clock switching device receives the abnormality detection signal from the external clock monitoring unit 5 together with the outputs of the unlock detection circuit 21 and the system reset circuit 22 and makes a judgment from these. This is a control circuit that outputs a coefficient change instruction to the digital low-pass filter 16 and outputs a holdover instruction to the holdover circuit 17 according to the operating state to be performed.

FIG. 3 shows digital low-pass filter 16 and holdover circuit 1 according to the first embodiment of the present invention.
7 is a block diagram showing a configuration of FIG. In the digital low-pass filter 16, 241 to 24n (n is an integer) are arranged in a line in a signal path of the sampling data, and are provided with n D flip-flops for latching data output from the preceding stage by a sampling clock signal.
The output data of the D flip-flops 241... 24n are input to 51 to 25 (n + 1), and the output data is multiplied by a coefficient designated by a coefficient change instruction from the control circuit 23. Coefficient unit,
261 to 26n are coefficient units 251 ... 25, respectively.
There are n adders for sequentially adding outputs of (n + 1) and outputting filtering data from the last stage. It is to be noted that the coefficient units 251... 25 (n + 1) maintain stability in a normal state if a coefficient selection instruction is input such that a time constant becomes smaller than usual during synchronization pull-in. Synchronization characteristics can be improved.

In the holdover circuit 17, reference numeral 27 denotes a clock divider for dividing the sampling clock signal by 1 / L (L is an integer), and reference numeral 28 denotes a plurality of latest filterings based on the divided sampling clock signal. A memory for sequentially storing a predetermined number of data and outputting the oldest data of the stored data to the hold clock determination circuit 29 each time a clock is input;
9 is a memory 28 together with the filtering data.
And a hold clock determination circuit 30 that outputs an increase / decrease signal in accordance with the difference each time a sampling clock signal is input. The hold clock determination circuit 30 receives a holdover instruction from the control circuit 23 together with the increase / decrease signal. During the period when the over instruction and the increase / decrease signal are input, the counter outputs count data which increases / decreases each time the frequency-divided sampling clock signal is input, and otherwise outputs “0”. A latch circuit 32 for latching receives count data together with the latch data, normally outputs the latch data as it is, and outputs data of a value obtained by adding these while the increase / decrease signal is being input. The addition result output of the addition / subtraction circuit 32 becomes digital data.

Next, the operation will be described. When the power supply of the system including the clock switching device is turned on, the system reset circuit 22 detects this, and in response, the control circuit 23 outputs a holdover instruction to the holdover circuit 17, and the holdover circuit 17 Digital data is output based on a predetermined initial value set in advance at 28. Then, the D / A conversion circuit 13 converts the digital data into an analog voltage value, and the voltage controlled oscillator 14 controls the internal clock signal 4 having a frequency corresponding to the analog voltage value.
Is output.

When a plurality of external clock signals 1... 1 are input in such a state, the external clock monitoring unit 5 selects one of them and outputs it to the selection signal. Then, the selector 2 selects the external clock signal specified by the selection signal and outputs it to the synchronous clock generator 3, and the input divider 9 of the synchronous clock generator 6 divides the frequency of the selected clock signal. On the other hand, the output frequency divider 10 divides the frequency of the internal clock signal 4 based on the predetermined initial value, and the phase frequency comparison circuit 11 calculates the phase of the divided external clock signal 1 and the internal clock signal 4. The quantization circuit 15 samples the pulses, outputs sampling data having a value corresponding to the pulse width, and outputs a digital low-pass filter. Reference numeral 16 performs low-pass filtering using a plurality of sampling data continuously output from the quantization circuit 15, and outputs filtered data.

At the same time, the external clock monitor 5 releases the abnormality detection signal when outputting the selection signal, and the control circuit 23 outputs a coefficient change instruction to the digital low-pass filter 16 and a hold instruction signal to the holdover circuit 17. Is output, the holdover circuit 17 outputs digital data based on the filtering data. Then, the D / A conversion circuit 13 converts the digital data into an analog voltage value, and the voltage controlled oscillator 14 controls the internal clock signal 4 having a frequency corresponding to the analog voltage value.
Is output.

When the operation based on the external clock signal 1 is started, the phase frequency comparison circuit 11
A phase-locked loop that passes through the quantization circuit 15, digital low-pass filter 16, holdover circuit 17, D / A conversion circuit 13, voltage-controlled oscillator 14, and output frequency divider 10 is formed. Control is performed such that the phase difference between the divided external clock signal 1 and the divided internal clock signal 4 becomes a predetermined value and the phase difference between the phase of the divided internal clock signal 4 becomes a constant value. Then, the internal clock signal 4 which is stabilized in a state where the phase difference between the phase of the frequency-divided external clock signal 1 and the phase of the frequency-divided internal clock signal 4 becomes a constant value and which is synchronized with the external clock signal 1 is generated. Can be.

In this phase lock operation of the loop, the memory 28 sequentially stores the filtering data sequentially output from the digital low-pass filter 16 based on the divided sampling clock signal. The memory 28 outputs the oldest data among the stored data to the hold clock determination circuit 29. However, since the switching signal is not output, the hold clock determination circuit 29 and the counter 30 are stopped. In addition, the addition / subtraction circuit 32 adds “0” to the filtering data latched by the latch circuit 31 (that is, passes the latch data as it is) and outputs it as digital data.

The digital low-pass filter 16 is
The last n pieces of sampling data are held by D flip-flops 241... 24n, and (n + 1) coefficient units 2
25 (n + 1) multiply each sampling data by a coefficient in accordance with the coefficient change instruction, calculate the sum by n adders 261... 26n, and output them as filtering data.

In the state where the internal clock signal 4 synchronized with the selected clock signal is generated, if an abnormality such as a frequency fluctuation occurs in the external clock signal 1 which is the basis of the selected clock signal, the external clock monitoring unit 5 detects the abnormality and outputs an abnormality detection signal, and the control circuit 23 outputs a holdover instruction to the holdover circuit 17. Then, the hold clock determination circuit 29 compares the data output from the memory 28 with the filtering data every time the sampling clock signal is input,
If there is a difference between them, an increase / decrease signal having that value is output, and the counter 30 counts up or down every time the frequency-divided sampling clock signal is input until it reaches the value indicated by the increase / decrease signal. The addition / subtraction circuit 32 outputs the sum or difference of the count data and the latch data as digital data.
Therefore, if the holdover instruction is continuously output, the digital data converges to the filtering data output from the memory 28 slightly earlier in time, and the internal clock signal 4 is oscillated in this state. .

If the synchronization between the selected external clock signal 1 and the internal clock signal 4 is greatly deviated due to other abnormalities, etc., the synchronization based on the sampling data output of the quantization circuit 15 is performed. Lock detection circuit 21
Detects this, the control circuit 23 outputs a holdover instruction, and the digital data converges to the filtered data slightly earlier in time outputted from the memory 28. Similarly, in this state, the internal clock signal 4 oscillates. Will be done.

After this abnormality is detected, the external clock monitoring unit 5 again detects the normalization of the original external clock signal 1 or outputs a selection signal for selecting another external clock signal 1... Then, the output of the abnormality detection signal is stopped at the same time. Thereby, the control circuit 23 stops the output of the holdover instruction, and the digital phase locked loop restarts the generation of the internal clock signal 4 synchronized with the external clock signal 1 selected by the selection signal.

Further, in the digital phase locked loop based on the monitoring result of the external clock monitoring unit 5 and the like, switching between the operation based on the external clock signal 1 and the operation based on the data in the memory 28 is repeated. Then, the phase jump amount monitoring unit 7 monitors the magnitude of the phase difference between the selected clock signal and the internal clock signal 4, and the phase jump direction switching unit 8 performs the operation when the phase difference exceeds a predetermined allowable range of the phase variation. Outputs a switching signal. Therefore, when such a switching signal is output, the hold clock determination circuit 29 outputs an increase / decrease signal so as to correct the value of the digital data.

Specifically, for example, the rising edge of the (divided) internal clock signal 4 is later on the time axis than the rising edge of the (divided) selected clock signal,
If a pulse is generated during the period from this edge to the edge and positive-valued sampling data is output based on this pulse, it is necessary to shorten this period. In this case, the cycle of the internal clock signal 4 is intentionally controlled to be small, and conversely, if the relationship between the edges is reversed, the value of the digital data is increased to intentionally control the cycle of the internal clock signal 4 to be large. do it.

Thus, when the operation based on the external clock signal 1 and the operation based on the data in the memory 28 are alternately switched in the digital phase locked loop,
Since it is necessary to stabilize the cycle and phase of the internal clock signal 4 before and after the switching, especially when switching from the operation based on the data of the memory 28 to the operation based on the external clock signal 1, the pulse It is necessary to change the initial value used as a reference when quantizing, and the phase difference is absorbed in this initial value.
Although the digital phase locked loop operates similarly in synchronization based on the sampling data, the selected clock signal (external clock signal 1)
In some cases, the phase difference between the internal clock signal 4 and the internal clock signal 4 fluctuates each time the switching is performed. In particular, the error accumulates after switching many times, and the selected clock signal (external clock signal 1) and the internal clock signal 4 There was a problem that the clock signal 4 could not be synchronized within the predetermined allowable phase difference range. However, this can be prevented.

FIG. 4 is a block diagram showing an example of a data processing circuit which operates using such an external clock signal 1 and an internal clock signal 4. Such a circuit is used in a data transmission path multiplexing device using an optical cable. In the figure, reference numeral 33 denotes a buffer memory which latches and holds input data with an external clock signal 1 and outputs latch data in the order in which the latched data is held in synchronization with the internal clock signal 4; .. Are data processing circuits for generating output data based on the latch data from 33. In order to make the latch operation based on the external clock signal 1 and the output operation based on the internal clock signal 4 appropriate in such a buffer memory 33, the latch operation based on the external clock signal 1 4, a fixed phase difference with respect to the external clock signal 1 due to a margin such as a setup time from the output operation based on the internal clock signal 4 to a latch operation from the output operation based on the internal clock signal 4 to a latch operation based on the external clock signal 1. It is required that the internal clock signal 4 be synchronized within the range.

FIG. 5 is an explanatory diagram for explaining an example of a method of setting a permissible range of the phase variation of the phase jump direction switching section 8 for such a phase difference range. In the figure, the horizontal axis represents the number of clock switchings, the vertical axis represents the amount of phase fluctuation of the internal clock signal 4 with respect to the external clock signal 1, 35 represents the upper limit of the phase difference range, and 36 represents the lower limit of the phase difference range. . And
The upper limit value 37 and the lower limit value 38 of the allowable phase variation range may be set so as to be between the upper limit value 35 and the lower limit value 36 of the phase difference range.

The change of the value of the digital data based on the switching signal is performed in the operation based on the external clock signal 1, in the operation based on the data in the memory 28, or in both of them. You may.

As described above, according to the first embodiment, the phase frequency comparison circuit which compares the external clock signal 1 with the internal clock signal 4 and outputs a pulse having a pulse width corresponding to the phase difference between them. 11, a digital value generation circuit 12 for generating digital data corresponding to the pulse width of the pulse, a D / A conversion circuit 13 for oscillating an internal clock signal 4 having a frequency corresponding to the value of the input digital data, and a voltage An external clock monitoring unit 5 which detects an abnormality of the external clock signal 1 and outputs an abnormality detection signal while detecting the abnormality, together with a digital phase locked loop comprising the control oscillator 14, Input, and during the period when this abnormality detection signal is input,
The control circuit 23 for inputting digital data generated in the internal memory 28 to the D / A conversion circuit 13 instead of the digital data generated by the digital value generation circuit 12 is provided. If this occurs, it is detected by the external clock monitor 5 and the control circuit 2
3 converts digital data generated internally into a D / A conversion circuit 1
3, and the voltage-controlled oscillator 14 can oscillate the internal clock signal 4 based on the digital data generated therein.

Therefore, since the internal clock signal 4 is generated based on the internally generated digital value, even if a predictive fluctuation state occurs in the external clock signal 1 before the above-mentioned abnormality detection, such an abnormal state The internal clock signal 4 does not synchronize with the external clock signal 1 in the above. In addition, since it is not necessary to increase the time constant of the digital phase locked loop, there is an effect that secondary problems such as deterioration of the synchronization pull-in characteristic do not occur.

According to the first embodiment, the external clock signal 1 and the internal clock signal 4 are input, and when the phase difference between the external clock signal 1 and the internal clock signal 4 exceeds a predetermined allowable range of phase fluctuation, a phase jump for outputting a switching signal is performed. A quantity monitoring unit 7 and a phase jump direction switching unit 8 are provided, and when the switching signal is input,
Since the digital value generation circuit 12 increases or decreases the digital data input to the D / A conversion circuit 13 during the period when the abnormality detection signal is input, the digital data of the digital phase-locked loop is converted into the internally generated digital data. Even if the value is cumulatively increased or decreased from the initial value each time it is switched, the internal change is detected to detect the cumulative change and suppress the cumulative change. Digital data can be changed.

Therefore, while repeatedly performing the operation of switching the digital data of the digital phase locked loop to the internally generated digital data, it is possible to surely keep the cumulative change of the value of the digital data within a predetermined allowable range. Therefore, the phase difference between the internal clock signal 4 and the external clock signal 1 can be surely maintained within a predetermined allowable range, and the buffer in which the internal clock signal 4 and the external clock signal 1 are input. Memory 33
For example, there is an effect that it is possible to reliably prevent the read margin in the output operation based on the internal clock signal 4 and the write margin in the latch operation based on the external clock signal 1 from becoming insufficient.

According to the first embodiment, the digital value generation circuit 12 performs the low-pass filtering process using the quantization circuit 15 that outputs sampling data corresponding to the pulse width of the pulse and the plurality of continuous sampling data. A digital low-pass filter 16 for outputting filtered data, and a hold for selecting one of the filtered data and internally generated digital data stored in the memory 28 based on a holdover instruction and outputting the selected data to the D / A conversion circuit 13 The pulse width of the pulse output from the phase frequency comparison circuit 11 is converted into a digital value, which is converted into a digital value.
4 and, when an abnormality occurs in the external clock signal 1, the voltage controlled oscillator 14 can be oscillated based on the internally generated digital data based on the abnormality detection signal.

According to the first embodiment, the holdover circuit 17 compares the memory 28 for storing the filtering data with the data stored in the memory 28 and the filtering data, and responds to the difference therebetween. A hold clock determination circuit 29 that outputs an increase / decrease signal; a counter 30 that outputs count data that sequentially increases / decreases while a holdover instruction and an increase / decrease signal are being input;
Latch circuit 31 for latching the filtering data
And an addition / subtraction circuit 32 that receives the increase / decrease signal and adds the count data to the data latched by the latch circuit 31 while the increase / decrease signal is input. Since the data is output to the D / A conversion circuit 13, the digital data in a normal state, which is a little before the time when the abnormality is detected, is stored in the memory 28, and the voltage controlled oscillator 14 can be oscillated based on the digital data. Therefore, there is no need to previously set internally generated digital data to a fixed value, and there is an effect that the frequency of the internal clock signal 4 can be used flexibly and stably.

According to the first embodiment, since the memory 28 and the counter 30 operate on the basis of the frequency-divided signal of the sampling clock signal, the control operation of the voltage-controlled oscillator 14 at the time of abnormality is slowed down and the digital phase The time constant of the locked loop can be increased. Therefore, there is an effect that the time constant of the digital phase locked loop is increased in the event of an abnormality, and the frequency fluctuation in this abnormal state can be effectively suppressed.

According to the first embodiment, the memory 28
Sequentially stores a plurality of latest filtering data,
Each time a clock is input, the oldest data is output to the hold clock determination circuit 29. Therefore, even if a predictive fluctuation state occurs in the external clock signal 1 before the abnormality is detected, the previous digital signal is output in the event of an abnormality. There is an effect that the frequency of the internal clock signal 4 can be stabilized at a predetermined value by using data reliably.

According to the first embodiment, selection unit 2 for selecting one external clock signal from a plurality of external clock signals 1... 1 and one external clock signal 1 selected by this selection unit 2 Is input to the synchronous clock generating circuit 3 so that the external clock signal 1 used for synchronizing the internal clock signal 4 becomes abnormal and switches between the plurality of external clock signals 1... Even in such a case, there is an effect that the frequency of the internal clock signal 4 can be stabilized without being affected by the predictive fluctuation of the external clock signal 1 that has become abnormal.

In particular, even if the external clock signal 1 becomes abnormal, the internal clock signal 4 whose phase and cycle are very stable
Can be suitably used in an optical communication device or the like that performs high-speed communication with an optical cable or the like.

Embodiment 2 FIG. 6 is a block diagram showing a configuration of a digital low-pass filter and a holdover circuit according to Embodiment 2 of the present invention. In the figure,
Reference numeral 39 denotes a hold signal generation circuit for receiving a holdover instruction and an increase / decrease signal, and inverting the increase / decrease signal to generate a hold signal while the holdover instruction is input. 40 denotes a sampling clock signal and a divided sampling clock. A selector for selecting a frequency-divided sampling clock signal during a period when a signal is input and a holdover instruction is input, and selecting a sampling clock signal during a period when a holdover instruction is not input; When a holdover instruction, a hold signal, and an increase / decrease signal are input together with the data, and there is no holdover instruction, the selector 40
This is an up / down counter that outputs the filtering data as digital data in synchronization with the output clock, and holds the digital data when there is a hold signal, and increases / decreases the value according to the increase / decrease signal. The other configuration is the same as that of the first embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. An abnormality occurs in the external clock signal 1 selected by the selection unit 2,
When the abnormality detection signal is output from the external clock monitoring unit 5, the holdover instruction output from the control circuit 23 is inverted, and the up / down counter 41 holds the digital data at this time in accordance with the inversion of the holdover instruction. I do. When the phase of the internal clock signal 4 based on the digital data is different from the phase corresponding to the digital data output from the memory 28, an increase / decrease signal is output from the hold clock determination circuit 29, and the divided clock signal is output. Each time is output from the selector 40, the up / down counter 41 increases or decreases the value of the digital data by a predetermined value. As a result, when the phase of the internal clock signal 4 based on the digital data matches the phase corresponding to the digital data output from the memory 28, the output of the increase / decrease signal from the hold clock determination circuit 29 is stopped, and the generation of the hold signal is stopped. The hold signal is output from the circuit 39, and the up / down counter 41 holds the value.
Then, when the selected clock signal is a normal external clock signal 1
, And the holdover instruction disappears, and the up / down counter 41 restarts the operation based on the selected clock signal.

The hold clock determination circuit 29
When the switching signal is input, the value of the digital data is increased or decreased regardless of the operation state.
Of the internal clock signal 4 can be eliminated. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the second embodiment, the holdover circuit 17 compares the memory 28 storing the filtering data with the data stored in the memory 28 and the filtering data. A hold clock determination circuit 29 for outputting an increase / decrease signal corresponding to the difference between the signals, and a hold signal generation circuit for inverting the increase / decrease signal and generating a hold signal during a period when the increase / decrease signal is input and an abnormality detection signal is input 39, the increase / decrease signal and the hold signal are input, and the filtering data is directly output to the D / A conversion circuit 13 during a period when the hold signal is not input, and during the period when the hold signal is input. The immediately preceding data is held and the data obtained by increasing or decreasing the
Up / down counter 41 for outputting to the / A conversion circuit 13
Therefore, the voltage controlled oscillator 14 can be caused to oscillate based on the normal digital data before the abnormality is detected, while maintaining the frequency stability of the internal clock signal 4.

Therefore, there is no need to previously set internally generated digital data to a fixed value, and there is an effect that the frequency of the internal clock signal 4 can be used flexibly and stably.

According to the second embodiment, since the memory 28 and the up / down counter 41 operate on the basis of the frequency-divided sampling clock signal, the control operation of the voltage controlled oscillator 14 at the time of an abnormality is delayed so that the digital system The time constant of the phase locked loop can be increased. Therefore, there is an effect that the time constant of the digital phase locked loop is increased in the event of an abnormality, and the frequency fluctuation in this abnormal state can be effectively suppressed.

Embodiment 3 FIG. 7 is a block diagram showing a configuration of the synchronous clock generator 6 according to the third embodiment of the present invention. In the figure, reference numeral 42 denotes a digital low-pass filter which performs low-pass filtering processing using a plurality of sampling data continuously output from the quantization circuit 15 and outputs filtered data, and 43 denotes a digital signal used in the digital low-pass filter 42. A holdover circuit for sequentially storing data and outputting the data to the digital low-pass filter 42.

FIG. 8 shows a digital low-pass filter 42 and a holdover circuit 4 according to a third embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of No. 3; In the figure, reference numeral 44 denotes a clock divider for dividing the sampling clock signal by 1 / L (L is an integer), and reference numeral 45 denotes an output from the final stage D flip-flop 24n based on the divided sampling clock signal. A memory for sequentially storing a predetermined number of filtered data and outputting the oldest data among the stored data to the digital low-pass filter 42 each time a clock is input. A selector for selecting whether the sampling data input to the data inputs of the D flip-flops 241... 24n is the data of the path output from the quantization circuit 15 or the data output from the memory 45. The other configuration is the same as that of the first embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. When the selected external clock signal 1 is normal, the abnormality detection signal is not output from the external clock monitoring unit 5 and no holdover instruction is output, so that each selector 461. The sampling data output from the circuit 15 is transferred to each D flip-flop 241.
・ Output to 24n. Therefore, the digital low-pass filter 42 performs a filtering process using a plurality of sampling data continuously output from the quantization circuit 15 at each time to generate digital data, and the voltage-controlled oscillator 14 generates a digital data based on the digital data. The generated internal clock signal 4 is generated. Then, the memory 45 sequentially stores the digital data under the normal state, and outputs the oldest data among the stored data to the digital low-pass filter 42.

Thereafter, when an abnormality occurs in the external clock signal 1 or the like, a holdover instruction is output from the control circuit 23, and the selectors 461,.
n switches so that the digital data output from the memory 45 is output to each of the D flip-flops 241 to 24n. Accordingly, the digital low-pass filter 42 performs a filtering process using the plurality of sampling data output from the memory 45 to generate digital data, and the voltage-controlled oscillator 14 generates the internal clock signal 4 based on the digital data. You. When the holdover instruction is canceled, each selector 461.
.. 46n outputs the output of the quantization circuit 15 to each of the D flip-flops 241. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the third embodiment, the digital value generation circuit 12 samples the analog value and outputs the sampling data.
And a memory 45 for storing a plurality of continuous sampling data, an output of the quantization circuit 15 and the memory 45
And a digital low-pass filter 42 that selects one of the outputs based on the holdover instruction, performs low-pass filtering processing, and outputs filtered data, and outputs the output of the low-pass filter 42 to the D / A conversion circuit 13 and voltage control. Since the pulse width is input to the oscillator 14, the pulse width of the pulse output from the phase frequency comparison circuit 11 can be converted into a digital value and the internal clock signal 4 can be output from the voltage controlled oscillator 14 in accordance with the digital value. When an abnormality occurs in the signal 1, the voltage-controlled oscillator 1 is controlled based on the normal digital data previously stored in the memory 45 in response to the holdover instruction.
4 can be oscillated.

Embodiment 4 FIG. 9 is a block diagram showing a configuration of the synchronous clock generator 6 according to the fourth embodiment of the present invention. In the figure, 47 is a phase frequency comparison circuit 11
And an analog low-pass filter for smoothing the pulse output from the phase frequency comparison circuit 11, and an A / A for sampling the smoothed pulse to generate sampling data.
The D conversion circuit 49 performs a low-pass filtering process using a combination of coefficients selected by a coefficient change instruction based on a plurality of sampling data continuously output from the A / D conversion circuit 48 and outputs filtering data. The digital low-pass filter 50 is a control circuit that outputs a coefficient change instruction for selecting a combination of coefficients that outputs only the sampling data output from the A / D conversion circuit 48 as it is at the time of synchronization pull-in. The other configuration is the same as that of the first embodiment, and the description is omitted.

Next, the operation will be described. The pulse output from the phase frequency comparison circuit 11 is smoothed by an analog low-pass filter 47 to a level corresponding to the pulse width, and then changed to sampling data by an A / D conversion circuit 48. When no special coefficient change instruction or holdover instruction is output from the control circuit 50 in response to the abnormality detection signal or the like, the sampling data is filtered by the digital low-pass filter 49 and output from the holdover circuit 17. Digital data based on the sampling data is output.

When a detection signal is output from the unlock detection circuit 21 or the like in a state where no abnormality detection signal is output, for example, in order to synchronize the selected external clock signal 1 and the internal clock signal 4, The control circuit 50 outputs a coefficient change instruction at the time of synchronization pull-in, that is, a coefficient change instruction for selecting a combination of coefficients that outputs only the sampling data output at that time from the A / D conversion circuit 48 as it is. Specifically, for example, only the coefficient unit 251 multiplies the sampling data by “1”, and all other coefficient units 252... 25 (n +
1) may be set so as to multiply the sampling data by “1”. Therefore, at the time of synchronization pull-in, the digital low-pass filter 49 is controlled to be substantially inactive, and
It operates based on the time constant of only the analog low-pass filter 47. Then, after the synchronization is secured, the control circuit 23 outputs a coefficient change instruction so as to select a normal coefficient, and a stable synchronous operation is performed with a synergistic time constant of the analog low-pass filter 47 and the digital low-pass filter 49. I do.

Since the digital low-pass filter 49 is made to function after the synchronization is pulled in, the initial value of the sampling data is stabilized at a substantially constant value even if a simple A / D conversion circuit 48 is used. 1
A complicated sampling circuit such as the quantization circuit 15 is unnecessary. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the fourth embodiment, the phase frequency comparison circuit 11 and the digital value generation circuit 12
And the digital value generation circuit 12 controls the digital low-pass filter 49 to a non-operating state at the time of synchronization pull-in, so that the analog low-pass filter 47 is at the time of synchronization pull-in.
The internal clock signal 4 can be synchronized with the external clock signal 1 faster than before by using only the high-speed filtering process. Moreover, when the synchronization is completed, the time constant of the digital phase-locked loop is increased by using the digital low-pass filter 49 together with the analog low-pass filter 47, whereby the internal clock signal 4 can be controlled stably, and the jitter suppression can be suppressed. There is an effect that characteristics can be improved.

[0070]

As described above, according to the present invention, a comparison circuit that compares an external clock signal with an internal clock signal and outputs an analog value corresponding to the phase difference between the external clock signal and the internal clock signal, and converts the analog value into a digital signal. A digital phase locked loop comprising: a digital value generation circuit that converts the value into a value to generate digital data according to the phase difference; and an oscillator that oscillates the internal clock signal having a frequency according to the value of the input digital data. At the same time, an external clock monitoring unit that detects an abnormality of the external clock signal and outputs an abnormality detection signal while the abnormality is detected, the abnormality detection signal is input, and the abnormality detection signal is input During the period, digital data generated internally instead of the digital data generated by the digital value generation circuit is input to the oscillator. When the external clock signal is abnormal, the external clock monitoring unit detects it and the control circuit inputs digital data generated internally to the oscillator. An internal clock signal is oscillated based on digital data.

Accordingly, since the internal clock signal is generated based on the digital value generated inside, even if a predictive fluctuation state occurs in the external clock signal before the above-mentioned abnormality detection, such an abnormal state is present. There is no attempt to synchronize the internal clock signal with the external clock signal. Moreover, since the time constant of the digital phase locked loop can be set in the same manner as in the related art, there is an effect that secondary problems such as deterioration of the synchronization pull-in characteristic do not occur.

According to the present invention, an external clock signal and an internal clock signal are input, and a phase difference monitoring section is provided for outputting a switching signal when the phase difference between them exceeds a predetermined allowable range of phase fluctuation. When the switching signal is input, the digital data input to the oscillator is increased or decreased during the period in which the abnormality detection signal is input, so that the digital data of the digital phase locked loop is switched to the internally generated digital data. In addition, even if a state in which the value is cumulatively increased or decreased from the initial value occurs, the cumulative change is detected by the phase difference monitoring unit, and the cumulative change is suppressed. Digital data generated internally can be changed.

Therefore, while repeatedly performing the operation of switching the digital data of the digital phase locked loop to the digital data generated internally, it is possible to surely keep the cumulative change in the value of the digital data within a predetermined allowable range. Therefore, the phase difference between the internal clock signal and the external clock signal can be reliably maintained within a predetermined allowable range. In a circuit to which the internal clock signal and the external clock signal are input, the read margin and the write There is an effect that the shortage of the margin can be reliably prevented.

According to the present invention, the digital value generation circuit samples the analog value and outputs the sampling data, and performs the low-pass filtering process using a plurality of continuous sampling data to output the filtering data. The analog value output from the comparison circuit is composed of a digital low-pass filter and a holdover circuit that selects one of the filtering data and internally generated digital data based on the abnormality detection signal and outputs the selected signal to the oscillator. Can be converted to a digital value and input to the oscillator, and if an external clock signal becomes abnormal, the oscillator can be oscillated based on the internally generated digital data based on the abnormality detection signal. There is.

According to the present invention, the holdover circuit compares the data stored in the memory with the filtering data, and outputs an increase / decrease signal in accordance with the difference between the memory and the memory. A clock determination circuit, a counter that outputs count data that sequentially increases or decreases while the abnormality detection signal and the increase / decrease signal are input, a latch circuit that latches the filtering data, and the increase / decrease signal is input, And an adder / subtractor circuit for adding the count data to the data latched in the latch circuit while the input is being input. The output of the adder / subtractor circuit is output to the oscillator, so that the normal state before the abnormality is detected is output. The oscillator can be oscillated based on the digital data at the time. Therefore, there is no need to previously set internally generated digital data to a fixed value, and there is an effect that the frequency of the internal clock signal can be used flexibly and stably.

According to the present invention, since the memory and the counter operate based on a clock having a longer cycle than that of the hold clock determination circuit, the control operation of the oscillator at the time of abnormality is delayed to reduce the time constant of the digital phase locked loop. Can be increased. Therefore, there is an effect that the time constant of the digital phase locked loop is increased in the event of an abnormality, and the frequency fluctuation in this abnormal state can be effectively suppressed.

According to the present invention, the holdover circuit compares the data stored in the memory with the filtering data, and outputs the increase / decrease signal in accordance with the difference between the memory and the memory. A clock determination circuit, a hold signal generation circuit that receives the increase / decrease signal, and inverts the increase / decrease signal to generate a hold signal during a period in which the abnormality detection signal is input;
When the increase / decrease signal and the hold signal are input and the hold signal is not input, the filtering data is output to the oscillator as it is, and while the hold signal is input, the immediately preceding data is held and increased / decreased. Since an up / down counter is provided which outputs data obtained by increasing or decreasing the signal to an oscillator based on a signal, the oscillator can be oscillated based on normal digital data before an abnormality is detected. Therefore, there is no need to previously set internally generated digital data to a fixed value, and there is an effect that the frequency of the internal clock signal can be used flexibly and stably.

According to the present invention, the memory and the up / down counter operate on the basis of a clock having a longer cycle than the hold clock determination circuit. The constant can be increased. Therefore,
At the time of abnormality, there is an effect that the time constant of the digital phase locked loop is increased and the frequency fluctuation in this abnormal state can be effectively suppressed.

According to the present invention, the memory sequentially stores a plurality of latest filtering data, and outputs the oldest data to the hold clock determination circuit every time a clock is input. Even if a predictive fluctuation state occurs in the external clock signal, there is an effect that the frequency of the internal clock signal can be stabilized to a predetermined value by reliably using the digital data before that in the event of an abnormality.

According to the present invention, the digital value generation circuit samples the analog value and outputs sampling data, the memory for storing a plurality of continuous sampling data, the output of the sampling circuit and the memory And a digital low-pass filter that performs low-pass filtering by selecting one of the outputs based on the abnormality detection signal and outputs filtered data.The output of the low-pass filter is input to the oscillator, so that the output The analog value can be converted to a digital value and input to the oscillator, and if an external clock signal becomes abnormal, the oscillator can be oscillated based on the internally generated digital data based on the abnormality detection signal. There is an effect that can be.

According to the present invention, the analog low-pass filter is provided between the comparison circuit and the digital value generation circuit, and the digital value generation circuit controls the digital low-pass filter to the non-operating state at the time of synchronization pull-in. The internal clock signal can be synchronized with the external clock signal at a higher speed than before by using only the high-speed filtering process of the analog low-pass filter. In addition, when the synchronization is completed, the time constant of the digital phase-locked loop is increased by using the digital low-pass filter together with the analog low-pass filter, so that the internal clock signal can be controlled as stably as before.

According to the present invention, there is provided a selection unit for selecting one external clock signal from a plurality of external clock signals, and a synchronous clock generation circuit to which one external clock signal selected by the selection unit is inputted. Therefore, even if an abnormality occurs in the external clock signal used for synchronizing the internal clock signal, and the external clock signal is switched between a plurality of external clock signals, the abnormal state of the external clock signal that has become abnormal There is an effect that the frequency of the internal clock signal can be stabilized without being affected by the predictive fluctuation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock switching device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a synchronous clock generation unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a digital low-pass filter and a holdover circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a data processing circuit that operates using an external clock signal and an internal clock signal according to the first embodiment of the present invention;

FIG. 5 is an explanatory diagram illustrating an example of a method of setting a permissible range of a phase change of a phase jump direction switching unit with respect to a phase difference range of a buffer memory of the data processing circuit.

FIG. 6 is a block diagram showing a configuration of a digital low-pass filter and a holdover circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a synchronous clock generator according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a digital low-pass filter and a holdover circuit according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a synchronous clock generator according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a conventional clock switching device.

FIG. 11 is a block diagram showing a configuration of another conventional clock switching device.

FIG. 12 is a block diagram showing a configuration of a third conventional clock switching device.

[Description of Signs] 1 external clock signal, 2 selection unit, 3 synchronous clock generation circuit, 4 internal clock signal, 5 external clock monitoring unit, 7 phase jump amount monitoring unit (phase difference monitoring unit), 8 phase jump direction switching unit (Phase difference monitoring unit), 11 phase frequency comparison circuit (comparison circuit), 12 digital value generation circuit, 1
3 D / A conversion circuit, 14 voltage-controlled oscillator (oscillator), 15 quantization circuit (sampling circuit), 16,
42, 49 digital low-pass filter, 17, 43 holdover circuit, 23 control circuit, 28, 45 memory, 29 hold clock determination circuit, 30 counter, 31 latch circuit, 32 addition / subtraction circuit, 39 hold signal generation circuit, 41 up / down counter , 47
Analog low-pass filter, 48 A / D conversion circuit (quantization circuit).

Continued on the front page. (72) Inventor Kazuo Kubo 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Hiroshi Ichigase 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Ryo Denki Co., Ltd. (72) Inventor Tadami Yasuda 2-3-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Inside Kay Diddy Submarine Cable System Co., Ltd. (72) Eiichi Shibano 2-3-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo No.2 Kay Didi Submarine Cable System Co., Ltd. F term (reference) 5J106 AA04 BB02 CC01 CC21 CC31 CC41 CC46 CC52 DD09 DD13 DD17 DD19 DD33 DD35 DD38 DD42 DD48 EE05 EE10 GG07 HH08 HH10 KK05 KK29

Claims (11)

[Claims] 1. A synchronous clock generation circuit for generating an internal clock signal synchronized with an external clock signal, wherein the synchronous clock generation circuit compares the external clock signal with the internal clock signal and outputs an analog value according to a phase difference between the external clock signal and the internal clock signal. A comparison circuit; a digital value generation circuit that converts the analog value into a digital value to generate digital data according to the phase difference; and oscillates the internal clock signal having a frequency according to the value of the input digital data. An oscillator, an external clock monitoring unit that detects an abnormality of the external clock signal, and outputs an abnormality detection signal while the abnormality is detected, and the abnormality detection signal is input, and the abnormality detection signal is input. During this period, the digital data generated internally instead of the digital data generated by the digital value generation circuit is sent to the oscillator. Synchronous clock generation circuit characterized by comprising a control circuit for force. 2. An external clock signal and an internal clock signal are input, and a phase difference monitoring unit is provided for outputting a switching signal when a phase difference between the external clock signal and the internal clock signal exceeds a predetermined phase fluctuation allowable range. 2. The synchronous clock generation circuit according to claim 1, wherein when input, the digital data input to the oscillator is increased or decreased during a period when the abnormality detection signal is input. 3. A digital value generation circuit, comprising: a sampling circuit that samples an analog value and outputs sampling data; and a digital low-pass filter that performs low-pass filtering processing using a plurality of continuous sampling data and outputs filtering data. 2. A synchronous clock generation circuit according to claim 1, further comprising a holdover circuit for selecting one of the filtering data and internally generated digital data based on an abnormality detection signal and outputting the selected data to an oscillator. . 4. A holdover circuit comprising: a memory for storing filtering data; a hold clock determination circuit for comparing data stored in the memory with the filtering data and outputting an increase / decrease signal in accordance with the difference between the memory and the filtering data; A counter that outputs count data that sequentially increases and decreases while the abnormality detection signal and the increase / decrease signal are input;
A latch circuit for latching the filtering data,
An input / output circuit that receives the increase / decrease signal and adds the count data to the data latched in the latch circuit while the increase / decrease signal is input, and outputs the output of the add / subtract circuit to an oscillator 4. The synchronous clock generation circuit according to claim 3, wherein: 5. The synchronous clock generation circuit according to claim 4, wherein the memory and the counter operate based on a clock having a longer cycle than the hold clock determination circuit. 6. A holdover circuit, comprising: a memory for storing filtering data; a hold clock determining circuit for comparing data stored in the memory with the filtering data and outputting an increase / decrease signal in accordance with a difference between the data; During the period when the increase / decrease signal is input and the abnormality detection signal is input, a hold signal generation circuit that inverts the increase / decrease signal to generate a hold signal, the increase / decrease signal and the hold signal are input, and the hold signal is The filtering data is output as it is to the oscillator during the period when it is not input, and the data immediately before and after the holding signal is input and the data obtained by increasing or decreasing the data based on the increase / decrease signal is output to the oscillator during the period when the hold signal is input. 4. A synchronous clock generator according to claim 3, further comprising an up / down counter. circuit. 7. The synchronous clock generation circuit according to claim 6, wherein the memory and the up / down counter operate based on a clock having a longer cycle than the hold clock determination circuit. 8. The memory according to claim 5, wherein the memory sequentially stores a plurality of latest filtering data, and outputs the oldest data to the hold clock determination circuit every time a clock is input. 7. The synchronous clock generation circuit according to 7. 9. A digital value generation circuit, comprising: a sampling circuit for sampling an analog value and outputting sampling data; a memory for storing a plurality of continuous sampling data; and an output of the sampling circuit and an output of the memory. 2. The synchronization according to claim 1, further comprising: a digital low-pass filter that selects one of them based on the abnormality detection signal, performs a low-pass filtering process, and outputs filtering data, and inputs an output of the low-pass filter to an oscillator. Clock generation circuit. 10. The digital value generating circuit according to claim 3, wherein an analog low-pass filter is provided between the comparing circuit and the digital value generating circuit, and the digital value generating circuit controls the digital low-pass filter to a non-operating state at the time of pull-in. The synchronous clock generation circuit according to claim 9. 11. A synchronizing clock generating circuit according to claim 1, wherein a selecting section for selecting one external clock signal from a plurality of external clock signals and one external clock signal selected by said selecting section are inputted. Clock switching device provided.