KR20020053238A - clock and frame sync signal stability device of the duplex system - Google Patents

Abstract

PURPOSE: A clock and frame synchronization signal stabilizer in a duplexing system is provided to remove a loss of a frame synchronization by equally processing a system clock signal and the frame synchronization signal according to active and standby mode statuses. CONSTITUTION: An OSC(3A-B) generates a reference clock signal for an active side main processor. A PLL(4A-B) divides the reference clock signal from the OSC(3A-B) and generates and provides a system clock signal to slaves(2A-N). A system clock section(5A-B) generates and provides a system clock signal using PLLs(4A-B) of active and standby sides to the slaves(2A-B). A frame synchronization section(6A-B) generates and provides a frame synchronization signal using a clock signal from the system clock section(5A-B) of the active and standby sides to the slaves(2A-B). A change switch(7A-B) selects an output of the OSC(3A-B) and an output of the system clock section(5A-B).

Description

Clock and frame sync signal stability device of the duplex system

The present invention relates to a clock and frame synchronization signal stabilizer of a redundant system, and more particularly, to a system clock signal and a frame synchronous signal according to active and standby modes of a system clock part and a frame synchronous part which are connected to a master device of a redundant system by redundancy. In this case, the standby master device operates with the same clock and frame synchronization signal as the active master device, so that the phase change of the clock and the loss of frame synchronization due to the switching of the redundant system are eliminated. The present invention relates to a clock and frame synchronization signal stabilizer of a redundant system that can be eliminated.

In general, the transmission technology began with the spiral carrier in the 1910s, developed into the analog transmission technology, and in the form of the digital transmission technology. Later, the digital transmission technology has evolved the development of the D1 channel bank with a 1.544Mbps transmission speed in the 1960s. It was. Moreover, such digital technology has been applied to the field of exchange technology in the mid-1970s. 4 ESS has led to the emergence of a digital relay switch, which has revolutionized the multiplexing of wired transmission systems. In addition, the digital transmission method has been developed into an optical transmission method using an optical cable as a transmission medium, and based on this, there is a trend of changing from an asynchronous PDH transmission system to a synchronous SDH transmission system.

However, in the above-described exchange system, a main device which is divided into active and standby sides through a bus line as shown in FIG. 1 in order to prevent call disconnection or system failure due to instability of internal devices. The processor 70A-B and various boards constituting a plurality of slave devices 71A-N operated by receiving a system clock and a frame synchronization signal from the master device 70A-B, for example, connect a call signal. It consists of redundancy of switching board.

Then, a more detailed example of such a conventional redundancy system, the system clock and the frame synchronization signal to the active main processor (70A) and standby main processor (70B) that is a master composed of slaves (71A-N) and redundancy Components for generating the same are configured with redundancy.

That is, each of the master active and standby main processors 70A-B divides an OSC 72A-B for generating a reference clock signal and a reference clock signal input from the OSC 72A-B. Frame synchronization signals are generated using a PLL 73A-B, which is a phase synchronization loop for generating a clock signal and supplying the slave signals to the slaves 71A-N, and a system clock signal of the PLL 73A-B to generate a frame synchronization signal. Counter 74A-B for supplying 71A-B is provided.

The PLL 73A-B has a PFD 75A-B for comparing the phase difference between the reference clock signal input from the OSC 72A-B and the signal fed back from the terminal and outputting the phase difference signal. LF 76A-B for low-pass filtering the phase difference signal input from 75A-B and converting it into a voltage difference signal, and a VCXO for generating a system clock signal according to the signal input from the LF 76A-B. (77A-B).

On the other hand, referring to the operation of the redundant system applied to the conventional exchange as described above, when the system is first set up, any one of the main processors 70A-B constituting the master device becomes active and the other one It is operated by STAND-BY. For example, if the main processor 70A is set to active, the main processor 70B is set to standby. Then, a system clock and a frame synchronizing signal are generated by the active main processor 70A. At this time, the PFD 75A of the PLL 73A of the main processor 70A is input from the OSC 72A. The phase difference between the clock signal and the clock signal fed back from the terminal is compared and the comparison signal is input to the LF 76A. The LF 76A of the PLL 74A converts the input phase difference signal of the PFD 75A into a voltage difference signal and inputs it to the VCO 77A. Then, the VCO 77A generates a system clock signal according to the signal input from the LF 76A and supplies it to each board constituting the slaves 71A-N, for example, to a switching board connecting the call. At the same time, the system clock signal is also input to the counter 74A. The counter 74A generates a frame synchronization signal once every 256 system clocks when the frame synchronization is 8 MHz TDM and supplies it to the slaves 71A-N. do. Accordingly, the slaves 71A-N perform a normal call processing function according to a system clock and a frame synchronization signal supplied from the active main processor 70A.

However, if the main processor 70A that has been active during the above process is switched for several reasons, the main processor 70A in the active state becomes standby and the main processor 70B previously in the standby state. Becomes active, and the system clock and frame synchronization signals are supplied to the slaves 71A-N to operate the redundant system normally.

However, in the conventional redundant system as described above, the master device is dualized to the active side and the standby side using a common bus. However, since the system clock and the frame synchronizing signal for driving the system are not actually duplicated, the master device that was operated in an active state is replaced. In this case, a phase difference is generated in the system clock signal, which causes a defect in deteriorating the operating stability of the entire system.

In addition, the conventional redundant system as described above loses the frame synchronization due to the system structure when the master device operated in the active state is switched. In this case, the frame synchronization signal of the system must be received from the newly activated master. There was a problem lacking this.

Accordingly, the present invention has been invented to solve the above problems, the system clock unit and the frame synchronization unit is connected to the master unit of the redundancy system redundantly and the system clock signal and the frame synchronization signal according to the active and standby mode state By processing the same and supplying to the slave, the standby master device operates with the same clock and frame synchronization signal as the active master device at the time of switching, thus eliminating the clock phase change and the loss of frame synchronization due to the switching of the redundant system. The object of the present invention is to provide a clock and frame synchronization signal stabilizer of a redundant system.

Another object of the present invention is that even if the active master device is switched, the standby master device operates immediately with the same clock and frame synchronization signal, so that the function of the redundant system is not malfunctioned. The present invention provides a clock and frame synchronization signal stabilizer for a redundant system. The present invention for achieving the above object is to generate an OSC for generating a reference clock signal to the active main processor of the redundancy system, and to divide the reference clock signal input from the OSC to generate a system clock signal to supply to the slaves A system clock unit for generating a system clock signal using a PLL, which is a phase locked loop, a clock signal input from the active and standby PLLs, respectively, and supplying the system clock signal to slaves, and a system clock unit for the active and standby sides. The clock and frame synchronization signal stabilizer of a redundant system comprising a system clock unit for generating frame synchronization signals using the clock signals inputted from the system and supplying the slave signals to the slaves, and a switch for selecting an output of the OSC and system clock units. to provide.

1 is an explanatory diagram illustrating a conventional redundancy system.

2 is an explanatory diagram illustrating a redundancy system of the present invention.

<Detailed Description of Codes>

1A-B: Main Processor 2A-N: Slave

3A-B: OSC 4A-B: PLL

5A-B: System Clock 6A-B: Frame Synchronizer

7A-B: Changeover switch 8A-B: False gate

9A-B: DFF 10A-B: Frequency Multiplier

11A-B: Counter 12A-B: False Gate

13A-B: PFD 14A-B: LF

15A-B: VCO

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the apparatus of the present invention receives a main clock 1A-B, which is a master device divided into active and standby sides through a bus line, and receives a system clock and a frame synchronization signal from the master device. Various boards constituting the plurality of slave devices 2A-N operated, for example, a duplication of switching boards for connecting call signals.

Each of the active and standby main processors 1A-B of the present invention as described above divides an OSC 3A-B for generating a reference clock signal and a reference clock signal input from the OSC 3A-B. By using a PLL (4A-B), which is a phase locked loop for generating a system clock signal and supplying it to the slaves (2A-N), and a clock signal input from the active and standby PLLs (4A-B), respectively. By using a system clock unit 5A-B for generating a system clock signal and supplying it to the slaves 2A-N, and a clock signal input from the system clock unit 5A-B on the active and standby sides, respectively. A frame switch 6A-B for generating a frame sync signal and supplying the slave signals to the slaves 2A-B, and a switching switch for selecting an output of the OSC 3A-B and the system clock unit 5A-B ( 7A-B).

The system clock section 5A-B includes an oal gate 8A-B which logically combines and outputs the clock signal of the counterpart PLL 4A-B, which is redundant with the clock signal of the PLL 4A-B, The DFF (9A-B) for correcting the duty cycle of the clock frequency signal input from the false gates (8A-B) and the frequency multiplier (10A-B) for multiplying the output frequency of the DFF (9A-B) by two times. Is done.

The frame synchronizer 6A-B also counters the clock signals of the PLL 4A-B to generate frame synchronization pulses, and the frame synchronizer input from the counters 11A-B. It consists of an false gate 12A-B which logically combines and outputs the frame synchronization pulses inputted from the counter counters 11A-B which are redundant with a pulse.

A phase frequency detector (PFD) for comparing the phase difference between the reference clock signal input from the OSC 3A-B and the signal fed back from the terminal and outputting the phase difference signal to the PLL 4A-B. And a LF 14A-B for low-pass filtering the phase difference signal input from the PFD 13A-B and converting it into a voltage difference signal, and a system clock signal in accordance with the signal input from the LF 14A-B. It consists of a VCXO (15A-B) to generate.

Next, the operation and effects of the apparatus of the present invention as described above will be described.

First, when a system is set up like a conventional redundant device, any one of the main processors 1A-B constituting the master device becomes active and the other is set to a standby mode. For example, if the main processor 1A is set to be active, the main processor 1B is set to standby.

Then, a system clock and a frame synchronizing signal are generated by the active main processor 1A. At this time, the changeover switch 7A of the main processor 1A connects the switching contact to the OSC 3A. On the other hand, the changeover switch 7B of the main processor 1B connects the switching contact to the system clock section 5B.

Accordingly, the PFD 13A of the PLL 4A of the main processor 1A has a phase difference between the reference clock signal inputted from the OSC 3A via the switch 7A and the clock signal fed back from the VCO 15A. After comparison, the comparison signal is input to the LF 14A. In the LF 14A of the PLL 4A, the input phase difference signal of the PFD 13A is converted into a voltage difference signal and input to the VCO 15A. Then, the VCO 15A generates a system clock signal in accordance with the signal input from the LF 14A and generates an oar gate 8A of the redundant system clock unit 5A and an oar of the opposite system clock unit 5B. Input to gate 8B, respectively.

At the same time, the PFD 13B of the PLL 4B of the main processor 1B also has a phase difference between the clock signal of the system clock unit 5B input via the changeover switch 7B and the clock signal fed back from the VCO 15A. And compare the signal to the LF 14B. In the LF 14B of the PLL 4B, the input phase difference signal of the PFD 13B is converted into a voltage difference signal and input to the VCO 15A. Then, the VCO 15A generates a system clock signal in accordance with the signal input from the LF 14B and generates an oar gate 8B of the redundant system clock unit 5B and an oar of the opposite system clock unit 5A. Input to gate 8A, respectively.

Therefore, the false gates 8A-B of the system clock units 5A-B are always operated because clocks are input from the active and standby VCOs 15A-B, respectively. ). Then, the DFF 9A-B corrects the difference in the duty cycle of the input gate 8A-B and inputs the frequency multiplier 10A-B to the frequency multiplier 10A-B. The output is reduced to 1/2 of the output frequency of the false gates 8A-B. Therefore, the frequency multiplier 10A-B multiplies the frequency signals of the input DFFs 9A-B by two and supplies them to the slaves 2A-N and the frame synchronizer 6A-B as system clocks.

In other words, the clock supplied from the active side OSC 3A is output via the VCO 15A of the PLL 4A. At this time, the clock signal of the active VCO 15A is also supplied to the false gate 8B of the system clock unit 5B on the opposite side and used as the system clock on the standby side. By the clock, both the active and standby sides operate in a synchronous state.

On the other hand, the system clock signals of the system clock units 5A-B are respectively input to the false gates 12A-B of the frame synchronization units 6A-B, that is, the active side system clock units 5A. The system clock signal is input to the active side counter 11A, and the system clock signal of the standby side system clock section 5B is input to the standby side counter 11B, respectively. Then, each of these counters 11A-B generates a frame synchronization signal once every 256 system clocks when the frame synchronization is 8 MHz TDM, and inputs it to the false gate 12A-B of the corresponding frame synchronization unit 6A-B. In this case, the system clock units 5A-B also cross input the system clock signals to the false gates 12A-B of the opposite frame synchronization units 6A-B, respectively. Then, each of the frame synchronization units 6A-B generates a frame synchronization signal by combining the input signals and supplies them to the respective slaves 2A-N. Accordingly, the slaves 2A-N perform a normal call processing function according to a system clock and a frame synchronization signal supplied from the active main processor 1A. At this time, the slaves 2A-N also receive the system clock and frame synchronization signals from the standby side main processor 1B synchronized with the active side.

Therefore, if the main processor 1A that was active during this process is switched over for several reasons, for example, a failure of the main processor 1A, the main processor 1A that is currently in the active state becomes standby. The main processor 1B, previously in standby mode, is immediately switched to the active mode to supply the system clock and frame synchronization signals to the slaves 2A-N.

At this time, the main processor 1B switched to the active mode is operated through the same process as the operation of the main processor 1A on the active side.

Therefore, even if the master device operating in the active mode is switched for whatever reason, the slave system 2A-N is always the same system because the master device operating in the standby mode is always in sync with the master device operating in the active mode. Since the clock and frame synchronization signals are supplied, the system is stabilized accordingly.

As described above, according to the present invention, the system clock unit and the frame synchronizing unit which are connected to the master unit of the redundancy system redundantly process the system clock signal and the frame synchronizing signal in the same manner according to the active and standby modes and supply them to the slave. In other words, when the standby master device is operated with the same clock and frame synchronization signal as the active master device, the phase change of the clock and the loss of frame synchronization due to the switching of the redundant system are eliminated.

In addition, according to the present invention, even if the active master device is switched, the standby master device operates immediately with the same clock and frame synchronization signal, so that the function of the redundant system is not malfunctioned. Accordingly, the operation stability of the redundant system is significantly improved. There is also an effect.

Claims (3)

In a redundant system having a main processor that is a master that is divided into active and standby via a bus line, An OSC for generating a reference clock signal to the active side main processor, a PLL for generating a system clock signal by dividing the reference clock signal inputted from the OSC, and supplying it to slaves, and the active and standby sides The system clock unit generates a system clock signal using the clock signals inputted from the PLLs of the PLL, and supplies the frame synchronization signal using the clock signals inputted from the system clock units of the active and standby sides, respectively. A system clock and frame synchronization signal stabilizer of a redundant system, comprising: a system clock unit for generating and supplying the slaves; and a switching switch for selecting an output of the OSC and the system clock unit. 2. The system of claim 1, wherein the system clock unit comprises an logic gate that logically combines the clock signal of the counterpart PLL which is redundant with the clock signal of the PLL, a DFF correcting the duty cycle of the clock frequency signal inputted from the false gate; And a frequency multiplier for multiplying the output frequency of the DFF by two. 2. The frame synchronizing unit according to claim 1, wherein the frame synchronizing unit logically combines a counter for generating a frame synchronizing pulse by counting a clock signal of the PLL, and a frame synchronizing pulse input from the counter of the counter which is redundant with the frame synchronizing pulse input from the counter Clock and frame synchronization signal stabilizer of the redundant system, characterized in that consisting of an output gate.