KR20030055374A - A system for clock synchronization between switch boards with redundancy and line boards - Google Patents

Abstract

PURPOSE: A system for clock synchronization between a dual switch board and a line connection board is provided, which achieves clock synchronization between the switch board and the line connection board, and supplies a stable clock to each line connection board. CONSTITUTION: The system comprises two dual switch boards(210,220) performing switching according to a switching signal and a plurality of line connection boards(230,240) connected to the switch boards by a signal line to transmit a synchronous clock. Each switch board includes a switching part(211,221) performing switching according to the switching signal and generating a control signal indicating dual state by exchanging the dual control signal between each switch board, and a synchronous clock circuit part(212,222) generating a self clock using a clock generated by an external synchronous reference clock or a clock generated by self oscillation and then supplying it to the switching part. The synchronous clock circuit part generates a synchronous clock using the clock generated by self oscillation or the external synchronous reference clock only when the present switching board is in an active state, and supplies the generated synchronous clock to the plurality of line connection boards through the signal line.

Description

A SYSTEM FOR CLOCK SYNCHRONIZATION BETWEEN SWITCH BOARDS WITH REDUNDANCY AND LINE BOARDS}

The present invention relates to a clock synchronization device, and more particularly, to a system implementing clock synchronization between a switch board having a redundant structure and a plurality of line connection boards.

In a system having a redundant switch board and a line connection board, for example, an Asynchronous Transfer Mode (ATM) switching system, clock synchronization between the switch board and a plurality of line connection boards is required.

Conventionally, in order to provide a synchronous clock in a system, a clock generation and distribution board is separately provided to supply a synchronous clock to a switch board and a line connection board, and the clock generation board and the clock distribution board are connected to a cable or a wiring pattern in the board. The connection method is used. This known technology has been published in Korean Patent Publication No. 2000-41887 (published date: July 15, 2000). Hereinafter, the known technology will be described with reference to FIG. 1.

1 shows a circuit configuration of a conventional clock synchronizer.

As shown in FIG. 1, the conventional clock synchronizing apparatus includes a clock generation board 101 and two clock generation and distribution boards 102 and 103. The clock generation and distribution boards 102 and 103 may be integrated into one board or may be configured as separate boards connected to each other by a cable or a wiring pattern. In FIG. 1, the case of being integrated into one board is illustrated.

The clock generation board 101 generates a synchronization reference clock as an external synchronization reference clock input from the outside, and supplies the synchronization reference clock to the clock generation and distribution boards 102 and 103. In the system environment, when the external synchronization reference clock is not input, a clock generator may be provided inside the clock generation board 101 to generate the synchronization reference clock with its own clock without receiving the external synchronization reference clock. The clock generation and distribution boards 102 and 103 generate the synchronous clocks using the synchronous reference clocks, and supply them to the switch boards and the plurality of line connection boards in common. Allow clock synchronization.

However, the conventional clock synchronizing apparatus described above has a problem in that the clock is not supplied to the switch board and the line connection board when a failure occurs in the clock generation block by being installed in a separate board form in the system. In addition, in the case of duplexing the switch board and the like, since a separate board for clock synchronization must be manufactured, there is a problem that the manufacturing cost of the system increases.

On the other hand, by configuring a clock generator on each board having a redundant structure, and by detecting the board when mounting or mounting the board, a method has been proposed to stably supply the clock even if the redundant board is mounted or mounted. . This prior art has been disclosed in Korean Patent Publication No. 2000-32961 (published date: June 15, 2000). However, in the above method, only the emphasis is placed on the mounting or mounting of the board, and there is a problem in that a state in the board or an external command cannot be detected.

The present invention has been made under the technical background as described above, and in a system having a switch board having a redundant structure and a plurality of line connection boards connected to the switch board, the clock synchronization between the switch board and the line connection board can be implemented. Another object of the present invention is to provide a system capable of supplying a stable clock to each of the line connection boards by including a synchronization clock generator, a synchronization clock supply unit, and a synchronization clock selector in each of the redundant switch boards.

1 is a circuit diagram of a conventional clock synchronizer.

2 is a circuit diagram of a clock synchronizing apparatus according to the present invention;

3 is a detailed configuration diagram of a synchronous clock circuit shown in FIG. 2;

4 is a detailed block diagram showing an actual implementation of the synchronous clock supply unit shown in FIG.

5 is a waveform diagram of major signals used in the clock synchronizer of the present invention.

(Explanation of symbols for the main parts of the drawing)

210, 220: switch board 230, 240: line connection board

211 and 221: switching unit 212 and 222: synchronous clock circuit unit

The present invention for achieving the above object,

In a system consisting of two redundant switch boards for switching in accordance with a transfer signal and a plurality of line connection boards connected to the two switch boards by signal lines for transmitting synchronous clocks,

Each switch board,

A switching unit which performs switching according to a switching signal and generates a control signal indicating a redundancy state by exchanging redundancy control signals between the switch boards; And

Generates its own clock using an external synchronous reference clock or a clock generated by its own oscillation and supplies it to the switching unit, and judges the control signal generated by the switching unit only when the current switch board is active. And a synchronization clock circuit unit configured to generate a synchronization clock using the external synchronization reference clock or a clock generated by oscillation by itself, and supply the generated synchronization clock to a plurality of line connection boards through the signal line. do.

According to the present invention, a synchronous clock is generated using a reference clock only in a switch board that is active according to the control signal indicating a state of the switch board, and the generated synchronous clock is supplied to a plurality of line connection boards. . Therefore, clock synchronization can be achieved between the redundant switch board and the plurality of line connection boards, and stable supply of the synchronous clock is possible.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 shows a circuit configuration of the clock synchronizing apparatus according to the present invention.

As shown in FIG. 2, the clock synchronizing apparatus according to the present invention includes two switch boards 210 and 220 and N line connection boards 230 and 240. Each switch board 210 and 220 includes a switching unit 211 and 221 and a synchronous clock circuit unit 212 and 222. Since the two switch boards 210 and 220 have a redundant structure, when one is in an active state, the other is in a standby state.

The external switching signal and the internal switching signal are input to each of the switching units 211 and 221 in the two switch boards 210 and 220, and a unique switching function is performed according to these switching signals. Although not shown in the drawings, each of the switching units 211 and 221 includes a circuit for controlling switching. The two switch boards 210 and 220 exchange redundancy control signals with each other, and determine whether their boards are active or standby according to the redundancy control signal. In addition, when the external transfer signal and the internal transfer signal are input, each switch board determines its own state according to a predetermined duplication algorithm. As the external transfer signal, a transfer signal input to an external processor may be used. As the internal transfer signal, a signal generated from a transfer switch (not shown) existing in a switch board may be used. have.

The synchronous clock circuits 212 and 222 generate a self clock and a synchronous clock for use in a switch board to which the synchronous reference clock is externally received or by using a clock generated by oscillation.

In order to generate the respective clocks, the synchronous clock circuits 212 and 222 receive an external synchronous reference clock or have an oscillator as a reference clock for generating the respective clocks using the generated clocks. Can be used. That is, in the case of a system environment in which the synchronous reference clock is not input from the outside, the synchronous clock circuit unit 212 and 222 includes an oscillator to generate a reference clock through the system environment, and the synchronous reference clock is input from the outside. In this case, a reference clock is generated using the input external synchronization reference clock. In this embodiment, it is assumed that an external synchronization reference clock is input to each of the synchronization clock circuits 212 and 222.

In other words, the synchronous clock circuits 212 and 222 of the two switch boards 210 and 220 generate their own clocks by using an external synchronous reference clock or a clock generated by the oscillation itself, and these are included in the clocks. It supplies to the switching parts 211 and 221 of a switch board.

Each of the synchronous clock circuits 212 and 222 generates the synchronous clocks for the N line connection boards 230 and 240 using the clock generated by the external synchronization reference clock or its own oscillation. When the belonging switch board is in an active state, the generated sync clock is supplied to each of the line connection boards 230 and 240. In other words, the clocks generated by each of the synchronous clock circuits 212 and 222 are supplied to the switching unit of the switch board to which they belong regardless of the redundancy algorithm, but the synchronous clock depends on the state of the switch board to which they belong. That is, if the switch board to which it belongs is active, the generated sync clock is supplied to the N line connection boards, and if the switch board to which it belongs is standby, the generated sync clock is supplied to the N line connection boards. It doesn't work. In the present invention, when the synchronous clocks are transmitted to N line access boards in two redundant switch boards, the synchronous clocks are transmitted by sharing a common channel. By doing the above, the synchronization clock can be transferred from the two redundant switch boards 210 and 220 to the N line connection boards using one channel. When viewed from the input side of each line connection board, the source of the synchronous clock input is different depending on the state of each redundant switch board, but the synchronization can be synchronized to the switch board which is always active. Under this structure, clock synchronization between the redundant switch board and the N line connection boards can be achieved without having a separate clock board in the system.

3 shows a detailed configuration of the synchronous clock circuit shown in FIG.

As shown in FIG. 3, the synchronous clock circuit unit of FIG. 2 receives a control signal from a synchronous clock generator 301 which generates a reference clock using an external synchronous reference clock or a clock generated by itself, and receives a control signal. And a synchronization clock supply unit 302 for generating its own clock and N synchronization clocks by receiving the reference clock and the synchronization clock generation signal.

As outlined above, the sync clock generator 301 generates a reference clock using an external synchronous reference clock or a clock generated by oscillation itself. The sync clock selector 303 determines a control signal input from the switching unit of FIG. 2, generates a sync clock generation signal, and transfers the generated sync clock generation signal to the sync clock supply unit 302. The control signal is a signal indicating whether the current switch board is in an active state or a standby state. The sync clock generation signal is a signal for instructing whether or not a synchronization clock is generated. This is to generate a synchronous clock only when it is active.

The synchronous clock supply unit 302 generates its own clock using the reference clock input from the synchronous clock generator 301, and always supplies the generated self clock to the switching unit of the switch board to which the synchronous clock generator belongs. In addition, the sync clock supply unit 302 determines whether to generate a sync clock according to the state of the sync clock generation signal. That is, if the switch board to which the synchronous clock circuit belongs is active, the control signal will indicate the active state, and the synchronous clock generation signal will command the generation of the synchronous clock, so that the synchronous clock supply unit 302 generates the synchronous clock. N synchronization clocks are generated using the reference clock by the signal. If the switch board to which the sync clock circuit unit belongs is in a standby state, a control signal will indicate a standby state, and the sync clock generation signal will instruct not to generate a sync clock. The synchronous clock is not generated by the clock generation signal. On the other hand, the synchronous clock circuit portion provided in each of the two redundant switch boards share the signal line of the synchronous clock provided to the plurality of line connection board, in order to prevent the signal collision, the synchronous clock circuit portion of the switch board in the active state Generates a synchronous clock, the synchronous clock circuit portion of the switch board in the standby state does not generate a synchronous clock, and while the synchronous clock circuit portion does not generate a synchronous clock, the synchronous clock supply portion of the synchronous clock circuit portion Maintain high impedance.

FIG. 4 shows an actual implementation of the synchronous clock supply unit shown in FIG. 3 in detail.

As shown in FIG. 4, the synchronous clock supply unit includes a tri-state buffer 401 and a buffer 402. 4 shows two synchronous clock supplies each provided on two redundant switch boards. A reference clock is input to the two buffers 401 and 402, and the buffer 402 buffers the reference clock and outputs it as its own clock. The tri-state buffer 401 synchronizes the reference clock according to the synchronization clock generation signal. Output as a clock or output a high impedance signal. As shown in FIG. 4, the synchronous clock generation signal SYNC_GER is input to the control terminal of the tri-state buffer 401, and according to the state of the signal, the reference clock on the input side is output as a synchronous clock or a high impedance signal is output. Output it. Here, the three-state buffer 401 of each of the two switch boards includes a synchronization clock generation signal SYNC_GER and an inverted signal thereof. ) Are inputted so that the two tri-state buffers 401 do not simultaneously output a synchronous clock. That is, while the tri-state buffer 401 belonging to the active switch board of the two switch boards outputs the synchronous clock, the tri-state buffer 401 belonging to the other switch board outputs a high impedance signal. In this way, the signal line for transmitting the synchronous clock can share the synchronous clock circuit portion of the two switch boards. The number of signal lines for transmitting the sync clock output from the sync clock supply unit is determined according to the output driving capability of the tri-state buffer in the sync clock supply unit. For example, when the output driving capability is '1' (only one input is driven) and the number of line matching boards is N, the number of sync clock signal lines is N. As in this embodiment, when the output driving capability of the tri-state buffer 401 is 'N', one sync clock signal line is required.

5 is a waveform diagram of main signals used in the clock synchronizing apparatus of the present invention. More specifically, the control signals used in the switching units 211 and 221 of the two switch boards 210 and 220 shown in FIG. 2 and the synchronous clock circuits 212 and 222 of each switch board 210 and 220. The waveforms of the reference clock used in the synchronous clock and the sync clock provided to the N line connection boards 230 and 240 are shown. Referring to the waveform diagram of FIG. 5, it can be seen that the control signals used in the two switch boards 210 and 220 are always opposite to each other. In addition, since the reference clock of the switch board in the active state is provided as a synchronous clock, it can be seen that the phase of the reference clock and the sync clock used in the switch board in the active state coincide with each other. In Fig. 5, reference numerals 501 and 502 are for representing such phase matching. Thus, clock synchronization between the switch board and the respective line connection boards, which are always active, can be achieved.

As described above, in the system of the present invention, in order to implement clock synchronization between a switch board having a redundant structure and a plurality of line connection boards each connected by one signal line to these switch boards, A synchronization clock generating unit, a synchronization clock supply unit, and a synchronization clock selection unit are provided in the switch board, and the synchronization clock is generated using the reference clock only in the switch board which is active according to a control signal indicating the state of the switch board. Allow the clock to be supplied to multiple line connection boards. Therefore, clock synchronization can be achieved between the redundant switch board and the plurality of line connection boards, and stable supply of the synchronous clock is possible. In addition, the synchronization clock is generated only in the active switch board, so that two redundant switch boards can transmit the synchronization clock to the plurality of line connection boards using one signal line, thereby reducing the number of signal lines for the synchronization clock transmission. Can be reduced. In addition, the system of the present invention has the advantage that it is not necessary to put separate synchronous clock related circuits in the plurality of line connection boards.

Claims (6)

In a system consisting of two redundant switch boards for switching in accordance with a transfer signal and a plurality of line connection boards connected to the two switch boards by signal lines for transmitting synchronous clocks, Each switch board, A switching unit which performs switching according to a switching signal and generates a control signal indicating a redundancy state by exchanging redundancy control signals between the switch boards; And Generates its own clock using an external synchronous reference clock or a clock generated by its own oscillation and supplies it to the switching unit, and judges the control signal generated by the switching unit only when the current switch board is active. And a synchronization clock circuit unit configured to generate a synchronization clock using the external synchronization reference clock or a clock generated by oscillation by itself, and supply the generated synchronization clock to a plurality of line connection boards through the signal line. A system for clock synchronization between redundant switch boards and line connection boards. The method of claim 1, And said two redundant switch boards are in a standby state when one is active and the other is in a standby state. The method of claim 1, And a signal line for transmitting the synchronous clock is shared by the two switch boards. The method of claim 1, The synchronous clock circuit unit, A synchronization clock generator for generating a reference clock using the external synchronization reference clock or a clock generated by oscillation by itself; A sync clock selector configured to receive the control signal and generate a sync clock generation signal for determining whether to generate a sync clock according to a state of a switch board to which the control signal belongs; And The clock between the redundant switch board and the line connection board comprising a synchronous clock supply unit for generating a self clock using the reference clock and generating a synchronous clock using the reference clock according to the synchronous clock generation signal. System for synchronization. The method of claim 4, wherein The synchronous clock supply unit, A buffer which buffers the reference clock and outputs it as a self clock; And And a three-state buffer for buffering the reference clock according to the synchronization clock generation signal and outputting the reference clock as a synchronization clock. The method of claim 5, The synchronous clock supply unit is provided on each of the two switch boards, and the synchronous clock generation signal and its inverted signal are respectively input to each of the three state buffers of the synchronous clock supply unit. System for clock synchronization.