CN1156995C - Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system - Google Patents
Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system Download PDFInfo
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- CN1156995C CN1156995C CNB001194615A CN00119461A CN1156995C CN 1156995 C CN1156995 C CN 1156995C CN B001194615 A CNB001194615 A CN B001194615A CN 00119461 A CN00119461 A CN 00119461A CN 1156995 C CN1156995 C CN 1156995C
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Abstract
The present invention discloses a non-dithering method and a non-dithering device for switching between a hot-plugging main board and a hot-plugging backup board in a digital communication system. The device is composed of two non-dithering switching circuits respectively positioned on the main board and the backup board, wherein each circuit comprises a frequency locking circuit, a phase locking circuit, a switching control circuit and an output buffer circuit. The method is mainly characterized in that after a frequency and a phase are locked, the clock and the data of the main board are output so as to judge whether an effective switching indication exists; if the effective switching indication exists, the clock and the data of the original backup board are output, and the clock and the data of the original main board are closed; the original backup board is upgraded into a main board, and the original main board is degraded into a backup board. The present invention can realize the non-dithering switching between the main board and the backup board.
Description
Technical field
The present invention relates to hot-swappable active and standby non-jitter changing method and device in a kind of digital communication system, when mainboard is extracted or system sends when switching indication, can with signal and clock non-jitter switch to slave board, that is: switch the clock that causes and data dithering at can not perceiveing within the scope that system allows.
Background technology
At some digital communication system for example in SPC digital switch, the video conferencing multipoint controller, its high reliability request veneer not only can hot plug, important veneer even want Hot Spare.Being seen active and standby switching at present all is not that non-jitter is switched, promptly on clock or data wire, can introduce disturb, cause losing or producing burr of clock pulse, also can cause the data error code, therefore system produces irrecoverable property mistake sometimes, even or recover also can be unstable in short-term.
In certain switch system, the active and standby switching of clock board is typically to have shake to switch, main board (is called for short mainboard, down with) extract or the clock signal no-output all can (be called for short slave board by standby plate in several clock cycle, down together) clock detection circuit detects, thereby slave board sends switching signal forces former mainboard to become slave board, and slave board is upgraded to mainboard.
In the patent No. is that US 5289044, name are called in the United States Patent (USP) of " Electronic system switchable betweenits primary circuit and standby circuit ", and a kind of active and standby commutation circuit system has been described.The master and stand-by circuits of this system is identical, and each circuit includes primary function circuit, alarm detection circuit, commutation circuit, output select circuit and output tri-state buffer circuit.This system has automatically and manual two kinds of switching modes.The automated manner operation principle is, when primary function circuit is alarmed in being in master's usefulness system of attitude, main with the alarm detection electric circuit inspection in the attitude system to this signal and inform standby attitude system, the commutation circuit in the back-up system will be led output enable simultaneously with system and export three-state.The manual switchover operation principle is, when commutation circuit detect main when extracting with circuit, just with the stand-by circuit output enable.The shortcoming of this commutation circuit system is not guarantee the switching instant non-jitter, has clock pulse and loses, clock bur and data error code.
In the patent No. is CN1245999A, and name is called in the Chinese patent of " master backup reverse device ", and a kind of quick master-slave device for switching has been described.Utilize this device RS or JK flip-flop realize the interlocking of activestandby state between the active and standby plate, utilize jitter elimination circuit to overcome RS or JK flip-flop middle transition state and the phase hit in switching.This device can be realized active and standby fast switching, but can not guarantee the non-jitter switching.Reason is, on the one hand, the prerequisite that this circuit works is that power supply is stable, each logical circuit worked with normal condition under, in fact circuit board inserting or withdrawal process in, power supply is stable gradually, and is stable as yet at power supply, when control circuit did not play useful effect, this plate may produce interference to system.On the other hand, this device has only been done processing to switch-over control signal itself, the signal that control signal is controlled does not deal with, in fact in digital communication system, data-signal could switch after particularly clock signal must be alignd, otherwise can have the phase hit of data and clock when switching.Therefore this device is applicable to the occasion that allows to have in the handoff procedure instantaneous shake, and system can be fitted under new frequency and the phase place and rework after switching.
Open in the Japan Patent of flat 5-110425 for special in the patent No., illustrated a kind of under the condition that common clock reference signal is lost, still can one of them frequency and Phaselocked Circuit be locked onto on the output clock of another circuit by reference frequency disconnection detection circuit and control switching circuit, and alarm when the output clock of another circuit is also lost.This patent has only proposed reference frequency disconnection detection circuit and clock source selection control switching circuit, how not to propose locked clock and phase place.
In CompactPCI Hot Swap Specification PICMG 2.1 R1.0 standards, describe hot plug technology in detail.This standard is comprehensive support hot plug from hardware to software, though for hot-swap provide may, and undeclaredly how to realize hot-swap, comprise that non-jitter switches.
Summary of the invention
To the objective of the invention is in order addressing the above problem, hot-swappable active and standby non-jitter changing method and device in a kind of digital communication system to be provided, solve the non-jitter switching problem in the digital communication system of supporting hot plug.
For achieving the above object, the present invention realizes that the scheme of above-mentioned purpose comprises hot-swappable active and standby non-jitter changing method and device in a kind of digital communication system.
Described non-jitter switching device shifter is made up of the non-jitter commutation circuit that two-way lays respectively on mainboard and the slave board, mainboard is inserted on the different slots of a base plate with slave board, it is characterized in that: the two-way circuit structure is identical, includes frequency locking circuits, Phaselocked Circuit, control switching circuit and output buffer; Frequency locking circuits is used for the output clock frequency is locked onto the frequency of internal clocking on reference clock or the current mainboard; The phase place of the clock of Phaselocked Circuit after with frequency lock is adjusted, and snaps to the phase place of active clock, if phase place has been alignd and then need do not adjusted; Control switching circuit is used to finish active and standby switching, guarantee after effectively switching indication arrival, export the clock and the signal of former slave board earlier and it is upgraded to the master and use, just cut off the clock and the signal output of former mainboard then and it is reduced to standby, final output is the output of current mainboard, clock output in this output feeds back to two Phaselocked Circuit, as the input reference signal of phase place adjustment.
Described non-jitter changing method may further comprise the steps:
Locking frequency is that is: with the clock lock of mainboard and the slave board internal clock source on external clock reference or the current mainboard;
Locking phase that is: snaps to the clock phase on the slave board clock phase on the current mainboard;
The clock and the data of output mainboard, slave board output is forbidden;
Judged whether effective switching indication,, remained stationary that promptly mainboard is still exported clock and data, and slave board is exported still and is forbidden as not having; If any, then: after postponing a period of time S2, export the clock and the data of former slave board, and make former slave board be upgraded to mainboard; After postponing a period of time S1, close the clock and the data of former mainboard, and make former mainboard reduce to slave board; S1＞S2 wherein.
Owing to adopted above scheme, frequency lock and phase locking have been carried out in advance, clock frequency and phase place align (so-called alignment be meant that its error is within system's allowed band) between mainboard and the slave board, when clock switches to stand-by circuit from the main circuit clock, clock phase is continuous, the frequency unanimity, no burr; Owing to be to allow earlier after the clock and data output of slave board when switching, just close mainboard then again, the sampling instant of data wire clock before and after switching is continuous and correct value, no burr, and the system that guaranteed does not perceive the shake of switching.
Description of drawings
Fig. 1 is the schematic flow sheet that non-jitter of the present invention is switched.
Fig. 2 is that the non-jitter clock switches schematic diagram between effective transfer period.
Fig. 3 is to be switching time the example of one-period.
Fig. 4 is the circuit block diagram of non-jitter switching device shifter.
Fig. 5 is a clock board clock detection circuit in the general switch.
Fig. 6 a, 6b are the control switching circuit schematic diagrames.
Fig. 7 is a clock frequency lock-in circuit schematic diagram.
Fig. 8 a, 8b, 8c are clock phase lock-in circuit schematic diagrames.
Fig. 9 is the sequential chart of input and output clock.
Figure 10 is the output buffer schematic diagram.
Embodiment
Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.
Fig. 1 has illustrated the flow process that non-jitter of the present invention is switched.Master and stand-by circuits is all followed this flow process to the processing of clock and data-signal.
(1), reset after, if circuit is in standby attitude, change (9) (in (9) step below promptly changeing, other are analogized);
(2), if the system-timing reference source is an external clock, change (4);
(3), the clock frequency of circuit is by the decision of the clock source in this circuit, commentaries on classics (5);
(4), the clock frequency of circuit locks onto external clock reference;
(5), if, change (5) effectively there not being the index signal of switching between transfer period in the W;
(6), postpone Δ;
(8), forbid exporting clock and data, reduce to standby attitude;
(9), if the system-timing reference source is an external clock, change (12);
(10), the clock frequency of circuit locks onto main clock with circuit;
(11), the phase alignment of clock is to main phase place with circuit clock, commentaries on classics (14);
(12), the clock frequency of circuit locks onto external clock reference;
(13), the phase alignment of clock is to main phase place with circuit clock;
(14), if, change (14) effectively there not being the index signal of switching between transfer period in the W;
(15), output clock and data, be upgraded to the main attitude of use, commentaries on classics (2);
Above-mentioned flow process can be simplified and is described as: 1) locking frequency, that is: according to clock module, with the internal clock source of the clock lock of mainboard and slave board (or claim alignment, synchronously) on external source or the current mainboard; As for clock is to be synchronized to system External Reference source or to determine that by inside it is provided with decision by system.After the frequency lock, the two frequency is identical, but phase place is not necessarily identical.2) locking phase that is: snaps to the clock phase on the slave board clock phase on the current mainboard; Here phase place is roughly the same, but not necessarily identical, allows certain differing, and this differs by the system parameters decision, generally is no more than the clock cycle half, differs big more, and effectively W is more little between transfer period.3) clock and the data of output mainboard, slave board output is forbidden; 4) judged whether effective switching indication, as not having, remained stationary (promptly still export the clock and the data of former mainboard, slave board output is forbidden, does not switch); If any, then: after postponing a period of time S2, export the clock and the data of former slave board, and make former slave board be upgraded to mainboard; After postponing a period of time S1, close the clock and the data of former mainboard, and make former mainboard reduce to slave board; S1＞S2 wherein.
With reference to Fig. 6 a, Fig. 6 b, the implication of effectively switching indication is: the arbitrary signal among default active and standby signal MS_SLI, active and standby control signal ACTIVE2, line detection signal PLUGOUT, the reset signal RESET effectively arrives mainboard or backboard in the W between the switch area, and the variation of initiation current state signal STATE1, this causes the signal that switches is effectively to switch to indicate.Behind deduction relative delay Δ during the same level of master/backup clock is W between effective transfer period (as Fig. 2), switches to indicate to have only could arrive master and stand-by circuits initiation switching during this period simultaneously and not produce burr.
Relative delay: main be indicated to time (S1) of closing this road output and stand-by circuit and be indicated to time difference between time (S2) of output (Δ=S1-S2), S1＞S2 wherein, 0＜S2＜W, Δ＜S2＜W+ Δ from receiving to switch from receiving switching with circuit.This postpones to guarantee stand-by circuit output clock and data earlier, just closes the master then and uses circuit, has avoided the not stationary state of output.Mainly by the parameter decision of output buffer, for example for 74LS245, general Δ=20-30ns gets final product relative delay Δ value size.
This changing method is generally used for the switching of low-speed clock, and this mainly is subject to switch to be indicated to and switches time S1, the S2 that finishes, and S2 is determined by the performance of device usually, and S1 also is greater than S2, the two will be finished in a clock cycle, and general S1, S2 are less than W, so clock frequency can not be too fast.But by careful S1, the S2 value selected, for example make S2 be substantially equal to the integral multiple of clock cycle, the switching that just can cross over a plurality of clock cycle, S1, S2 are greater than W at this moment.Δ=S1-S2 wherein, S1＞S2 is during the level such as W+ Δ=clock.So, this method will can be used for the switching of high-frequency clock equally.It is the example of one-period that Fig. 3 has provided switching time.
Realize that according to preceding method the non-jitter device for switching is as follows:
The block diagram of system such as Fig. 4. Circuit 1,2 lays respectively on mainboard and the slave board, and structure is identical, includes frequency locking circuits, phase locking electricity, control switching circuit and output buffer.Two circuit interconnect by two cross interconnected holding wire ACTIVE1, ACTIVE2.Frequency locking circuits can be selected to export clock frequency and lock onto reference clock or determined by inside.The clock of Phaselocked Circuit after with frequency lock adjusted its phase place when being necessary, snaps to active clock, if phase place has been alignd and just need do not adjusted.Control switching circuit is finished active and standby switching, any time has only a circuit output (between transfer period in one blink before and after guarantee switching, then be that two-way has output simultaneously, but owing to frequency, phase place are alignd, the shake that causes is minimum, in the scope of looking into can not be felt by system), (three-state) forbidden in another output.Common circuit board output is main output with circuit, and the clock output in this output feeds back to two Phaselocked Circuit, as phase place adjustment input.
This device has following characteristics:
1. adopt special physical electrical structure.Power pin, grounding pin, signal pin and off-lined signal pin length difference, off-lined signal pin, signal, power supply and ground wire disconnect successively when pulling out plate, connect to reversed in order during plate; Move power supply on the off-lined signal pin on the plate, common circuit board is to the direct ground connection in position that should pin.This pin is as line detection signal (PLUGOUT).
2. circuit 1 is just the same with the structure of circuit 2, and default active and standby differentiation is discerned by reading on the common circuit board active/standby signal (MS_SLI).Active and standby control signal is transmitted by cross-coupled connection ACTIVE1, ACTIVE2 between two circuit, and so-called interconnection is meant: one tunnel output is as the input on another road, and vice versa.
3. two circuit are worked (unless wherein one the tunnel extracting fully) simultaneously, and a certain moment only is in the circuit output enable of activated state, and another piece output is ternary.The input of two circuit is not subjected to ternary control.
When 4. the clock of active and standby circuit guarantees to switch by frequency lock and phase place adjustment frequency equate and phase place consistent.
5. upper layer software (applications) is an output enable to the operation unanimity of two circuit, another three-state.The ternary requirement that will satisfy system parameters switching time to output.
6. switch and guarantee in the time that system parameters allows, to finish.
The course of work is as follows: when the master extracts with circuit, the pin of line detection signal PLUGOUT correspondence is an off-lined signal pin off-line at first, switch control logic is main after detecting off-line notifies stand-by circuit with circuit by switching controls line ACTIVE1, ACTIVE2, and the stand-by circuit output enable is upgraded to the main circuit of using simultaneously.Make the master reduce to stand-by circuit simultaneously simultaneously with circuit output three-state.
According to the said apparatus that preceding method is realized, when clock switched to stand-by circuit from the main circuit clock, clock phase was continuous, frequency unanimity, no burr; The sampling instant of data wire clock before and after switching is continuous and correct value, no burr, and the system that guaranteed does not perceive the shake of switching.
The specific implementation of circuit each several part is very flexible, multiple implementation can be arranged, for example general frequency locking circuits can be realized with phase-locked loop circuit, the also available phase-locked loop of phase locking or realize with logical circuit, the output buffering realizes the switch logic logical circuit with the balance driver or the non-equilibrium driver of the ternary control of band.Fig. 6 a, 6b, 7,8a, 8b, 8c, 10 have provided several realization circuit, and those skilled in the art is not difficult to obtain from explanation of the present invention to guide, and make other physical circuit, but still belong to protection scope of the present invention.
Fig. 5 is a clock board clock detection circuit in the general switch.Whether mainboard 4MHz clock is lost by the slave board clock detection circuit is detected.This circuit adopts one-shot multivibrator 74LS123, as heavily triggering input, so just can detect losing of clock in N clock cycle with tested clock.Suitably select time constant RC makes this circuit satisfy above-mentioned requirements and reliability requirement simultaneously.Suppose that constant RC guarantees that detecting 4M in N the 4M cycle (NT4M) loses and switch, the probability of losing a 8K pulse so in this time is N/512, and N is more little, and to switch the possibility of lost frames location, back more little, but the possibility that mistake is switched is big more; Otherwise the possibility that the big more mistake of N is switched is more little, but the possibility of lost frames location is big more.
Fig. 6 a, 6b are an embodiment of switch control logic circuit diagram, and two figure are actual to be a circuit diagram, the spaced apart for ease of picture, and the terminals that mark is identical among the figure link to each other.M2-1 2 selects 1 circuit among the figure, and FDP presets the d type flip flop of end for band, and NOR4 is the NOR gate with 4 inputs, and INV is an inverter, and OR2 is two inputs or door.The detailed description of element sees also XILINX company " XACT STEP, LIBRARIES GUIDE " in this circuit.
PLUGOUT is the off-line index signal, and ACTIVE1 is the switching controls output signal, outputs to the ACTIVE2 of another piece plate; ACTIVE2 is the switch control logic input, derives from the ACTIVE1 of another piece plate.MS_SLI is default active and standby signal, links a pin of common circuit board, and default master is a high level with this pin on the groove position, and default spareslots is a low level, pulled down to ground in plate.RESET is low at operating conditions.
After resetting, default main plate with groove position (MS_SLI=1) is in main with attitude (STATE=1), and the plate of default spareslots position (MS_SLI=0) is in standby attitude (STATE=0).When the master extracted with the attitude plate, the pin of this plate PLUGOUT correspondence is off-line at first, and PLUGOUT is uprised by low, and ACTIVE1 is by high step-down, and this plate SWITCH is uprised by low, and main board output three-state is reduced to standby plate simultaneously; Because main board ACTIVE1 output is directly connected to the ACTIVE2 input of standby plate, so standby plate ACTIVE2 follows ACTIVE1 by high step-down, this plate SWITCH is by high step-down, the standby plate output enable is upgraded to main board simultaneously simultaneously.
Fig. 7 is the embodiment of clock frequency lock-in circuit.MT8941 and peripheral circuit thereof constitute a digital phase-locked loop.G1 is the active crystal oscillator of 16.384MHz.The output clock (4MHz, 8KHz 2MHz) all are synchronized on the reference source 8KHz clock, promptly export 4MHz, and 2MHz signal and reference source 8KHz sequential relationship are fixed, 8KHz output with reference to 8KHz with frequency but differ.Please refer to the databook DIGITALSWITCHING ﹠amp of MITEL company about the details of MT8941; NETWORKING PP3-433-60.MT8941 has two kinds of working methods, and the one, the internal clocking mode, i.e. free oscillation mode (MS8941=1), all output clocks are produced by the direct frequency division of the 16.384MHz signal of the crystal oscillator of MT8941; The 2nd, the external clock mode, be common mode (MS8941=0), all outputs lock onto outside 8KHz reference clock, but do not guarantee to export the 8KHz signal and (can only finish frequency lock because of MT8941 with reference to the complete homophase of 8KHz, promptly all are exported clock frequencies or equal reference clock frequency, or are the integral multiple of reference clock).
Fig. 8 a, 8b, 8c are clock phase lock-in circuit embodiment, and three are schemed actual is a circuit diagram, the spaced apart for ease of picture, and the terminals that mark is identical among the figure link to each other.Wherein, 16 frequency counters that X74_161 can preset for the band asynchronous resetting with the 74LS161 compatibility, 10 frequency counters that X74_160 can preset for the band asynchronous resetting with the 74LS160 compatibility, FDP is the d type flip flop of band clear terminal, CB16RE is 16 digit counters with synchronous clear terminal.The detailed description of element sees also XILINX company in this circuit " XACT STEP, LIBRARIES GUIDE ".
4M, 8K_REF, 20MSI are clock input 4MO, and 8KO, 20MSO are clock output.
Work as MS=0, S1=1, during S0=0, it is main with attitude circuit 8KHz clock to represent that standby attitude circuit clock is synchronized to, and the 4MHz of stand-by circuit is with main anti-phase with circuit as can be known by the sequential chart of MT8941, so 4MO is the anti-phase output of 4M; Under other situation, because the MT8941 of master and stand-by circuits all is synchronized with same 8KHz reference source, so 4M does not need the anti-phase 4MO that directly outputs to.By utilizing the lock characteristic of MT8941, guarantee slave board 4MHz and mainboard homophase through top adjustment.
The 8KHz reference source after sampling as one of synchronous reset input signal of 256 frequency counters: SYNC, the feedback reset signal CARRY of SYNC and counter mutually non-or constitute the synchronous reset signal of counter later on, 8KO is 8KHz output.Can guarantee slave board output 8KHz and mainboard homophase by such logic.
The common formation of X74_161 and X74_160 160 frequency counters, input clock is the 4MHz clock of MT8941 after phase-locked, align adjusted 8KHz as the clock enable signal, DLY_20MS2 exports with reference to 20ms (50Hz) clock trailing edge detection signal, this signal is as the heavily loaded enable signal of counter, thereby the 20ms signal 20MSO that slave board is exported aligns with mainboard 20ms signal 20MSI trailing edge.
Fig. 9 is the sequential chart of input and output clock.
Figure 10 is the embodiment of output buffer.The balance driver of the ternary control of band is adopted in clock output, and tristate buffer is adopted in data output.Output control all output in=0 o'clock is effectively exported control=1 o'clock, and all export ternary.
Utilize the above embodiment of the present invention case, in the video conferencing multipoint control system, carried out the experiment of the active and standby non-jitter switching of power board.
In this control system, power board is finished functions such as video exchange simultaneously for system provides clock.The clock line that has of turnover power board also has lot of data and control line.Clock has 4MHz, 8KHz, and 50Hz (20ms) etc., data wire has video input-output line etc., and the switching controls line has ACTIVE1～2, and PLUGOUT is the off-line index signal.
All outputs are exported under the SWITCH signal controlling after three-state drives, and SWITCH is that high all outputs are ternary, and SWITCH is low all output enables.SWITCH is the output signal of active and standby control logic circuit.Main board SWITCH is low, and standby plate SWITCH is high.
The phase-locked of active and standby plate clock finished by MT8941, to guarantee that clock frequency equates with reference clock frequency.The phase place adjustment of active and standby plate clock is finished by Programmable Logic Device X95108PQ100, to guarantee the phase place and the reference clock phase alignment of clock.
Active and standby switch logic is finished by X95108PQ100.When the master extracted with the attitude plate, the pin of this plate PLUGOUT correspondence is off-line at first, and PLUGOUT is uprised by low, and ACTIVE1 is by high step-down, and SWITCH is uprised by low, and main board output three-state is reduced to standby plate simultaneously; Owing to active and standby plate ACTIVE1, ACTIVE2 interconnection, standby plate ACTIVE2 is by high step-down simultaneously, and SWITCH is by high step-down, and the standby plate output enable is upgraded to main board simultaneously.The time of finishing from the PLUGOUT off-line to switching is roughly 30ns by the speed of programmable logic device and the speed decision of three-state driver in this realization.This time is compared much smaller with system clock cycle 244ns.Test by reality learns that the switching instant clock phase is continuous, the data wire steady and continuous.The work of system is not affected, terminal image, sound noiseless.
From the above mentioned, non-jitter is switched can make switching that the impact of system is reduced to minimum, has improved the stability of system greatly, and simultaneity factor has strengthened system maintainability not carrying out the software and hardware upgrading under the powering-off state.
The patent No. is the patent of CN1245999A relatively, the present invention does not adopt the interlocking mechanism of RS or JK flip-flop, but at communication system, adopt special physical electrical structure, frequency and Phaselocked Circuit and control switching circuit to solve the existing problem of this patent of CN1245999A, realized the non-jitter switching.
The special relatively Japan Patent of opening flat 5-110425, the application has realized the Phaselocked Circuit of a kind of 8KHz and 50Hz clock, and in conjunction with active and standby control switching circuit, has realized the active and standby switching of non-jitter of clock data.
Claims (7)
1, hot-swappable active and standby non-jitter switching device shifter in a kind of digital communication system, form by the non-jitter commutation circuit that two-way lays respectively on mainboard and the slave board, mainboard is inserted on the different slots of a base plate with slave board, it is characterized in that: the two-way circuit structure is identical, includes frequency locking circuits, Phaselocked Circuit, control switching circuit and output buffer; Frequency locking circuits is used for the output clock frequency is locked onto the frequency of internal clocking on reference clock or the current mainboard; The phase place of the clock of Phaselocked Circuit after with frequency lock is adjusted, and snaps to the phase place of active clock, if phase place has been alignd and then need do not adjusted; Control switching circuit is used to finish active and standby switching, guarantee after effectively switching indication arrival, export the clock and the signal of former slave board earlier and it is upgraded to the master and use, just cut off the clock and the signal output of former mainboard then and it is reduced to standby, final output is the output of current mainboard, clock output in this output feeds back to two Phaselocked Circuit, as the input reference signal of phase place adjustment.
2, non-jitter switching device shifter as claimed in claim 1, it is characterized in that: the contact pin of two-way control switching circuit includes power pin, grounding pin, signal pin and off-lined signal pin, the length difference of each contact pin, at mainboard or slave board when base plate is extracted, guarantee that off-lined signal pin, signal pin, power pin and grounding pin are connected with the base plate disconnection in order successively, then above-mentioned each pin links to each other with base plate successively by opposite order when mainboard or slave board insertion base plate; Move power supply on the off-lined signal pin on mainboard or the slave board, the direct ground connection in position of the corresponding off-lined signal pin of base plate, this off-lined signal pin is as the line detection signal pin.
3, non-jitter switching device shifter as claimed in claim 1 or 2 is characterized in that: default active and standby signal MS_SLI is arranged on base plate, has line to link to each other respectively on mainboard and the slave board with this signal, with the default setting of determining this plate be main with or standby; Two active and standby control signal ACTIVE1, ACTIVE2 are also respectively arranged on mainboard and the slave board, wherein ACTIVE1 is output, ACTIVE2 is input, they are by cross interconnected connection transmission between two circuit, and promptly the active and standby control signal ACTIVE1 on plate outputs on another plate as active and standby control signal ACTIVE2 input; Mainboard or slave board only detect and just carry out handover operation when effective switching is indicated by the default active and standby signal MS_SLI of the comprehensive judgement of control switching circuit, active and standby control signal ACTIVE2, line detection signal PLUGOUT, five conditions of current state signal STATE1, reset signal RESET.
4, non-jitter switching device shifter as claimed in claim 1 or 2, it is characterized in that: described frequency locking circuits is made up of phase-locked loop circuit; Described Phaselocked Circuit is made up of phase-locked loop circuit or logical circuit.
5, non-jitter switching device shifter as claimed in claim 3, it is characterized in that: described frequency locking circuits is made up of phase-locked loop circuit; Described Phaselocked Circuit is made up of phase-locked loop circuit or logical circuit.
6, hot-swappable active and standby non-jitter changing method in a kind of digital communication system may further comprise the steps:
Locking frequency is that is: with the clock lock of mainboard and the slave board internal clock source on external clock reference or the current mainboard;
Locking phase that is: snaps to the clock phase on the slave board clock phase on the current mainboard;
The clock and the data of output mainboard, slave board output is forbidden;
Judged whether effective switching indication,, remained stationary as not having; If any, then: after postponing a period of time S2, export the clock and the data of former slave board, and make former slave board be upgraded to mainboard; After postponing a period of time S1, close the clock and the data of former mainboard, and make former mainboard reduce to slave board; S1＞S2 wherein, 0＜S2＜W, Δ＜S1＜W+ Δ, during the level such as W+ Δ=clock, Δ=S1-S2, W=is between effective transfer period.
7, non-jitter changing method as claimed in claim 6 is characterized in that: adjust the value of time S1, S2, the time S2 of making equals the integral multiple of clock cycle, crosses over the switching of a plurality of clock cycle, and this moment, S1, S2 were greater than W between effective transfer period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001194615A CN1156995C (en) | 2000-07-11 | 2000-07-11 | Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001194615A CN1156995C (en) | 2000-07-11 | 2000-07-11 | Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1324148A CN1324148A (en) | 2001-11-28 |
| CN1156995C true CN1156995C (en) | 2004-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001194615A Expired - Fee Related CN1156995C (en) | 2000-07-11 | 2000-07-11 | Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162960B (en) * | 2007-11-13 | 2012-03-07 | 中兴通讯股份有限公司 | Main-slave control cell signal synchronizing method |
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| CN100382452C (en) * | 2005-11-15 | 2008-04-16 | 中兴通讯股份有限公司 | Device and method for realizing ASC |
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| CN101562513B (en) * | 2009-05-25 | 2012-02-29 | 中兴通讯股份有限公司 | Method and device for switching main veneers and standby veneers |
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-
2000
- 2000-07-11 CN CNB001194615A patent/CN1156995C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162960B (en) * | 2007-11-13 | 2012-03-07 | 中兴通讯股份有限公司 | Main-slave control cell signal synchronizing method |
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