CN1156995C - Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system - Google Patents

Abstract

The present invention discloses a non-dithering method and a non-dithering device for switching between a hot-plugging main board and a hot-plugging backup board in a digital communication system. The device is composed of two non-dithering switching circuits respectively positioned on the main board and the backup board, wherein each circuit comprises a frequency locking circuit, a phase locking circuit, a switching control circuit and an output buffer circuit. The method is mainly characterized in that after a frequency and a phase are locked, the clock and the data of the main board are output so as to judge whether an effective switching indication exists; if the effective switching indication exists, the clock and the data of the original backup board are output, and the clock and the data of the original main board are closed; the original backup board is upgraded into a main board, and the original main board is degraded into a backup board. The present invention can realize the non-dithering switching between the main board and the backup board.

Description

Method and device for hot-swappable main-standby jitter-free switching in digital communication system

technical field

The present invention relates to a hot-swappable main-standby switchover method and device without jitter in a digital communication system. When the mainboard is pulled out or the system sends a switching instruction, the signal and clock can be switched to the standby board without jitter, that is, the switching causes The clock and data jitter of the system is within the imperceptible range allowed by the system.

Background technique

In some digital communication systems such as program-controlled digital switches and conference TV multi-point controllers, their high reliability requires not only hot-swappable single boards, but also hot backup for important single boards. The master-standby switchover seen so far is not a jitter-free switchover, that is, interference will be introduced on the clock or data line, resulting in loss of clock pulses or glitches, and data errors, so the system sometimes produces unrecoverable errors. Or become unstable for a short time even after recovery.

In a certain switch system, the master/standby switching of the clock board is a typical switching with jitter. The main board (referred to as the main board, the same below) is pulled out or the clock signal has no output, and the standby board ( The standby board for short, the same below) detects the clock detection circuit, so that the standby board sends a switching signal to force the original main board to become the standby board, and the standby board is upgraded to the main board.

In the US patent No. US 5289044 and the name "Electronic system switchable between its primary circuit and standby circuit", a main and standby switching circuit system is described. The main and backup circuits of the system are identical, and each circuit includes a main function circuit, an alarm detection circuit, a switching circuit, an output selection circuit and an output tri-state buffer circuit. The system has automatic and manual switching modes. The working principle of the automatic mode is that when the main function circuit in the system in the active state alarms, the alarm detection circuit in the active state system detects the signal and informs the standby state system, and the switching circuit in the standby system will output enable, At the same time, the main system is output in three states. The working principle of manual switching is that when the switching circuit detects that the main circuit is pulled out, it will enable the backup circuit output. The disadvantage of this switching circuit system is that there is no guarantee of no jitter at the switching time, and there will be loss of clock pulses, clock glitches and data errors.

In the patent No. CN1245999A, the Chinese patent titled "Master-Backup Switching Device" describes a device for fast master-backup switching. The device uses RS or JK flip-flops to realize the interlocking of the active and standby states between the main and standby boards, and uses a jitter elimination circuit to overcome intermediate transition states and phase jumps in the switching of RS or JK flip-flops. The device can realize fast master-standby switchover, but it cannot guarantee jitter-free switchover. The reason is that, on the one hand, the prerequisite for this circuit to work is that the power supply has been stabilized, and the logic circuits have been working under normal conditions. In fact, the power supply is gradually stable during the insertion or removal of the circuit board. , the board may have interfered with the system when the control circuit is not functioning effectively. On the other hand, the device only processes the switching control signal itself, and does not process the signal controlled by the control signal. In fact, in a digital communication system, the data signal, especially the clock signal, must be aligned before switching, otherwise it will be There are phase jumps in data and clock when switching. Therefore, the device is suitable for occasions where instantaneous jitter is allowed during the switching process, and the system can be adapted to a new frequency and phase to work again after switching.

In Japanese Patent No. 5-110425, it is described that under the condition that the common clock reference signal is lost, one of the frequency and phase locking circuits can still be locked by the reference frequency disconnection detection circuit and the switching control circuit. to another circuit's output clock and alert if the other circuit's output clock is also missing. This patent only proposes a reference frequency disconnection detection circuit and a clock source selection switching control circuit, but does not propose how to lock the clock and phase.

In the CompactPCI Hot Swap Specification PICMG 2.1 R1.0 specification, the hot swap technology is described in detail. This specification supports hot swap from hardware to software. Although it provides the possibility of hot switching, it does not explain how to realize hot switching, including jitter-free switching.

Contents of the invention

The object of the present invention is to solve the above problems, provide a method and device for hot-swappable main-standby jitter-free switching in a digital communication system, and solve the problem of jitter-free switching in a digital communication system that supports hot-swappable.

In order to achieve the above-mentioned object of the invention, the solution of the present invention to achieve the above-mentioned object includes a method and device for hot-swappable master-standby switchover without jitter in a digital communication system.

The jitter-free switching device is composed of two jitter-free switching circuits respectively located on the main board and the backup board. The main board and the backup board are inserted into different slots of a bottom board. The feature is that the two circuits have the same structure and include frequency Locking circuit, phase locking circuit, switching control circuit and output buffer circuit; the frequency locking circuit is used to lock the frequency of the output clock to the reference clock or the frequency of the internal clock on the current motherboard; the phase locking circuit adjusts the phase of the frequency-locked clock , aligned to the phase of the master clock, if the phase has been aligned, no adjustment is required; the switching control circuit is used to complete the master-standby switchover, to ensure that after the effective switchover instruction arrives, the clock and signal of the original standby board are first output and upgraded to Main use, then cut off the clock and signal output of the original main board and reduce it to standby, the final output is the output of the current main board, and the clock output in this output is fed back to two phase-locked circuits, used as the input for phase adjustment reference signal.

The jitter-free switching method includes the following steps:

Lock the frequency, that is: lock the clock of the main board and the standby board to the external clock source or the internal clock source on the current main board;

Lock the phase, that is: align the clock phase on the standby board to the clock phase on the current main board;

Output the clock and data of the main board, and the output of the standby board is prohibited;

Judging whether there is an effective switching instruction, if not, maintain the original state, that is, the main board still outputs clock and data, and the backup board still outputs prohibition; if there is, then: after a period of delay S2, output the clock and data of the original backup board, and Upgrade the original standby board to the main board; after a period of delay S1, turn off the clock and data of the original main board, and downgrade the original main board to the standby board; where S1>S2.

Due to the adoption of the above scheme, frequency locking and phase locking have been carried out in advance, and the clock frequency and phase between the main board and the standby board have been aligned (the so-called alignment means that the error is within the allowable range of the system), and the clock is switched from the main circuit clock to the In the standby circuit, the clock phase is continuous, the frequency is consistent, and there is no glitch; and because the clock and data of the standby board are output first, and then the main board is turned off, the data line is continuous and correct at the sampling time of the clock before and after switching. , no glitch, ensuring that the system does not perceive switching jitter.

Description of drawings

FIG. 1 is a schematic flow chart of the jitter-free handover in the present invention.

FIG. 2 is a schematic diagram of a jitter-free clock switching during effective switching.

Figure 3 is an example where the switching time is one cycle.

Fig. 4 is a circuit block diagram of a ditherless switching device.

Fig. 5 is a clock detection circuit of a clock board in a general switch.

6a and 6b are schematic diagrams of switching control circuits.

FIG. 7 is a schematic diagram of a clock frequency locking circuit.

8a, 8b, 8c are schematic diagrams of clock phase locking circuits.

FIG. 9 is a timing chart of input and output clocks.

FIG. 10 is a schematic diagram of an output buffer circuit.

Detailed ways

The present invention will be described in further detail below through specific embodiments and in conjunction with the accompanying drawings.

FIG. 1 illustrates the flow of the jitterless handover in the present invention. The processing of the clock and data signals by the main and backup circuits follows this process.

(1), after reset, if the circuit is in standby state, turn to (9) (that is, turn to step (9) below, and so on);

(2) If the system clock reference source is an external clock, go to (4);

(3), the clock frequency of the circuit is determined by the clock source in the circuit, turn to (5);

(4), the clock frequency of the circuit is locked to the external clock source;

(5), if there is no switching indication signal in the effective switching period W, turn (5);

(6), delay Δ;

(8), prohibit the output of clock and data, and reduce to standby state;

(9) If the system clock reference source is an external clock, go to (12);

(10), the clock frequency of the circuit is locked to the clock of the main circuit;

(11), the phase of the clock is aligned to the phase of the main circuit clock, turn to (14);

(12), the clock frequency of the circuit is locked to an external clock source;

(13), the phase of the clock is aligned to the phase of the main circuit clock;

(14), if there is no switching indication signal in the effective switching period W, turn (14);

(15), output clock and data, upgrade to master state, turn to (2);

The above process can be simplified and described as: 1) Lock the frequency, that is: according to the clock mode, the clocks of the main board and the standby board are locked (or aligned, synchronized) to an external source or the internal clock source on the current main board; as for the clock is synchronized to The reference source is external to the system or determined internally, which is determined by the system settings. After the frequency is locked, the frequency of the two is the same, but the phase is not necessarily the same. 2) Lock the phase, that is: align the clock phase on the standby board with the clock phase on the current main board; here the phases are roughly the same, but not necessarily identical, and a certain phase difference is allowed. The phase difference is determined by the system parameters, and generally not More than half a clock cycle, the greater the difference, the smaller the effective switching period W. 3) Output the clock and data of the main board, and the output of the standby board is prohibited; 4) Determine whether there is a valid switching instruction, if not, maintain the original state (that is, the clock and data of the original main board are still output, the output of the standby board is prohibited, and no switching occurs); if Yes, then: after a delay of S2, output the clock and data of the original standby board, and upgrade the original backup board to the main board; after a delay of S1, turn off the clock and data of the original main board, and downgrade the original main board to Standby board; where S1>S2.

Referring to Fig. 6a and Fig. 6b, the meaning of the effective switching indication is: any signal among the default main-standby signal MS_SLI, main-standby control signal ACTIVE2, online detection signal PLUGOUT, and reset signal RESET reaches the main board or backplane within the effective switching interval W , and cause the change of the current state signal STATE1, the signal that triggers switching is an effective switching indication. The effective switching period W (as shown in Figure 2) is the effective switching period W (as shown in Figure 2) after deducting the relative delay time Δ during the same level period of the main and standby clocks. Only during this period can the switching instructions reach the main and standby circuits at the same time to cause switching without generating glitches.

Relative delay: the time difference (Δ=S1-S2) between the time (S1) of the main circuit from receiving the switching instruction to closing the output of this channel and the time (S2) of the standby circuit from receiving the switching instruction to outputting, Wherein S1>S2, 0<S2<W, Δ<S2<W+Δ. The delay ensures that the standby circuit outputs the clock and data first, and then turns off the main circuit, avoiding the indefinite state of the output. The relative delay Δ value is mainly determined by the parameters of the output buffer, for example, for 74LS245, generally Δ=20-30ns is enough.

This switching method is usually used for low-speed clock switching, which is mainly limited by the time S1 and S2 from the switching instruction to the switching completion. S2 is usually determined by the performance of the device, and S1 is greater than S2. The two must be within one clock cycle. Complete, generally S1 and S2 are smaller than W, so the clock frequency cannot be too fast. However, by carefully selecting the values of S1 and S2, such as making S2 roughly equal to an integer multiple of the clock cycle, switching across multiple clock cycles can be performed, and S1 and S2 are greater than W at this time. Where Δ=S1-S2, S1>S2, W+Δ=equal level period of the clock. In this way, the method can also be used for high-speed clock switching. Figure 3 shows an example where the switching time is one cycle.

The device for realizing jitter-free switching according to the foregoing method is as follows:

The block diagram of the system is shown in Figure 4. Circuits 1 and 2 are respectively located on the main board and the backup board, and have the same structure, including a frequency locking circuit, a phase locking circuit, a switching control circuit and an output buffer circuit. The two circuits are connected to each other through two cross-interconnected signal lines ACTIVE1 and ACTIVE2. The frequency locking circuit can select the output clock frequency to be locked to the reference clock or determined internally. The phase locking circuit adjusts the phase of the frequency-locked clock when necessary, and aligns it with the main clock. If the phase is already aligned, no adjustment is required. The switching control circuit completes the main-standby switching, ensuring that there is only one circuit output at any time before and after the switching (during a short period of time during the switching period, there are two outputs at the same time, but because the frequency and phase have been aligned, the jitter caused is extremely small. In the system undetectable range), the other output is disabled (tri-state). The common circuit board output is the output of the master circuit, and the clock output in this output is fed back to the two phase-locked circuits for phase adjustment input.

The device has the following characteristics:

① Adopt a special physical and electrical structure. The power pin, ground pin, signal pin, and offline signal pin have different lengths. The offline signal pin, signal, power supply, and ground wire are disconnected in sequence when the board is pulled out, and connected in reverse order when the board is inserted; the offline signal pin on the board is pulled to The power supply, the common circuit board is directly grounded at the position corresponding to the pin. This pin is used as the online detection signal (PLUGOUT).

②The structure of circuit 1 and circuit 2 is exactly the same, and the default master/standby distinction is identified by reading the master/standby signal (MS_SLI) on the common circuit board. The main and standby control signals are transmitted through the communication lines ACTIVE1 and ACTIVE2 that are cross-connected between the two circuits. The so-called cross-connection means that the output of one circuit is used as the input of the other circuit, and vice versa.

③ Two circuits work at the same time (unless one of them has been completely pulled out), at a certain moment only the circuit in the active state is output enabled, and the other one outputs tri-state. The inputs to both circuits are not tri-stated.

④ The clocks of the main and backup circuits are frequency locked and phase adjusted to ensure that the frequencies are equal and the phases are consistent during switching.

⑤The operation of the upper layer software on the two circuits is the same, only one output is enabled, and the other is tri-state. The switching time from tri-state to output should meet the requirements of system parameters.

⑥Switching is guaranteed to be completed within the time allowed by the system parameters.

The working process is as follows: When the main circuit is pulled out, the pin corresponding to the online detection signal PLUGOUT, that is, the offline signal pin, is the first to go offline. After the switching control logic detects that it is offline, the main circuit notifies the backup circuit through the switching control lines ACTIVE1 and ACTIVE2. The circuit output can be promoted to the main circuit at the same time. At the same time, the three-state output of the main circuit is reduced to a standby circuit at the same time.

According to the above-mentioned device realized by the aforementioned method, when the clock is switched from the main circuit clock to the standby circuit, the clock phase is continuous, the frequency is consistent, and there are no glitches; the sampling time of the data line before and after the switch is a continuous and correct value without glitches, which ensures The system does not perceive the switching jitter.

The specific implementation of each part of the circuit is very flexible, and there are many ways to realize it. For example, the general frequency locking circuit can be realized by a phase-locked loop circuit, and the phase locking can also be realized by a phase-locked loop or a logic circuit. The output buffer uses a balanced circuit with three-state control. Driver or unbalanced driver implementation, switching logic with logic circuits. Fig. 6a, 6b, 7, 8a, 8b, 8c, 10 have provided several realization circuits, and those skilled in the art are not difficult to obtain guidance from the description of the present invention, and make other specific circuits, but still belong to this invention. protection scope of the invention.

FIG. 5 is a clock detection circuit of a clock board in a general switch. Whether the 4 MHz clock of the main board is lost is detected by the clock detection circuit of the standby board. This circuit adopts the monostable multivibrator 74LS123, and takes the detected clock as the retrigger input, so that the loss of the clock can be detected within N clock cycles. The time constant RC is properly selected so that the circuit can meet the above requirements and reliability requirements at the same time. Assuming that the constant RC guarantees that 4M loss is detected and switched in N 4M cycles (NT4M), then the probability of losing an 8K pulse within this time is N/512, and the smaller N is, the less likely it is to lose frame positioning after switching, but The greater the possibility of mishandling; on the contrary, the larger N is, the smaller the possibility of mishandling, but the greater the possibility of missing frame positioning.

Figures 6a and 6b are an embodiment of the switching control logic circuit diagram. The two diagrams are actually a circuit diagram, which are arranged separately for the convenience of drawing, and the same terminals are connected in the figure. In the figure, M2-1 is a 2-to-1 circuit, FDP is a D flip-flop with a preset terminal, NOR4 is a NOR gate with 4 input terminals, INV is an inverter, and OR2 is a two-input OR gate. For a detailed description of the components in this circuit, please refer to "XACT STEP, LIBRARIES GUIDE" of XILINX Company.

PLUGOUT is an offline indication signal, ACTIVE1 is a switching control output signal, which is output to ACTIVE2 of another board; ACTIVE2 is a switching control logic input, which comes from ACTIVE1 of another board. MS_SLI is the default active/standby signal, which is connected to a pin on the common circuit board. The pin on the default active slot is high level, and the default standby slot is low level, which is pulled down to ground in the board. RESET is low in the working state.

After reset, the board in the default active slot position (MS_SLI=1) is in the active state (STATE=1), and the board in the default standby slot position (MS_SLI=0) is in the standby state (STATE=0). When the main board is pulled out, the pin corresponding to the PLUGOUT of the board is the first to go offline, PLUGOUT changes from low to high, ACTIVE1 changes from high to low, the board SWITCH changes from low to high, and the output tri-state of the main board drops to the standby board at the same time ;At the same time, because the output of ACTIVE1 of the main board is directly connected to the input of ACTIVE2 of the backup board, ACTIVE2 of the backup board follows ACTIVE1 from high to low, and SWITCH of this board changes from high to low, and the output enable of the backup board rises to the master board at the same time.

FIG. 7 is an embodiment of a clock frequency locking circuit. MT8941 and its peripheral circuits form a digital phase-locked loop. G1 is a 16.384MHz active crystal oscillator. The output clocks (4MHz, 8KHz, 2MHz) are all synchronized to the reference source 8KHz clock, that is, the output 4MHz, 2MHz signal has a fixed timing relationship with the reference source 8KHz, and the 8KHz output has the same frequency as the reference 8KHz but has a phase difference. For more information about MT8941, please refer to MITEL's data sheet DIGITALSWITCHING & NETWORKING PP3-433-60. MT8941 has two working modes, one is the internal clock mode, that is, the free oscillation mode (MS8941=1), and all output clocks are directly divided by the 16.384MHz signal of the crystal oscillator of the MT8941; the other is the external clock mode, that is, the normal mode (MS8941=0), all outputs are locked to the external 8KHz reference clock, but it is not guaranteed that the output 8KHz signal is completely in phase with the reference 8KHz (because MT8941 can only complete frequency locking, that is, all output clock frequencies are either equal to the reference clock frequency or the reference clock Integer multiples of ).

Figures 8a, 8b, and 8c are the embodiments of the clock phase locking circuit. The three figures are actually a circuit diagram, which are arranged separately for the convenience of drawing, and the terminals marked the same in the figure are connected. Among them, X74_161 is a 16 frequency division counter with asynchronous clearing and presettable which is compatible with 74LS161, X74_160 is a 10 frequency division counter with asynchronous clearing and presettable which is compatible with 74LS160, and FDP is a D flip-flop with a clearing terminal. CB16RE is a 16-bit counter with a synchronous clear terminal. For the detailed description of the components in this circuit, please refer to "XACT STEP, LIBRARIES GUIDE" of XILINX Company.

4M, 8K_REF, 20MSI are clock input 4MO, 8KO, 20MSO are clock output.

When MS=0, S1=1, S0=0, it means that the clock of the standby circuit is synchronized to the 8KHz clock of the main circuit. From the timing diagram of MT8941, it can be seen that the 4MHz of the standby circuit is inverse to the main circuit, so 4MO is 4M inverse Phase output; in other cases, since the MT8941 of the main and backup circuits are all synchronized to the same 8KHz reference source, 4M directly outputs to 4MO without inversion. By using the phase-locking feature of MT8941, the above adjustments ensure that the 4MHz of the standby board is in phase with the main board.

The 8KHz reference source is sampled as one of the synchronous reset input signals of the 256 frequency division counter: SYNC, SYNC and the feedback reset signal CARRY of the counter are out of phase or later constitute the synchronous reset signal of the counter, and 8KO is an 8KHz output. This logic can ensure that the standby board outputs 8KHz in phase with the main board.

X74_161 and X74_160 together constitute a 160 frequency division counter. The input clock is the MT8941 phase-locked 4MHz clock, and the aligned and adjusted 8KHz is used as the clock enable signal. DLY_20MS2 is the reference 20ms (50Hz) clock falling edge detection signal output, which is used as a counter The overload enable signal of the main board, so that the falling edge of the 20ms signal 20MSO output by the standby board is aligned with the falling edge of the 20ms signal 20MSI of the main board.

Figure 9 is a timing diagram of the input and output clocks.

FIG. 10 is an embodiment of an output buffer circuit. The clock output uses a balanced driver with three-state control, and the data output uses a three-state buffer. When output control = 0, all outputs are active, when output control = 1, all outputs are tri-stated.

Utilizing the above-mentioned embodiments of the present invention, an experiment of switching between master and backup switch boards without jitter is carried out in a video conference multi-point control system.

In this control system, the switching board provides the clock for the system and completes functions such as video switching. There are clock lines going in and out of the switch board as well as a lot of data and control lines. The clock includes 4MHz, 8KHz, 50Hz (20ms), etc., the data line includes video input and output lines, etc., the switching control line includes ACTIVE1~2, and PLUGOUT is an offline indication signal.

All outputs are output under the control of SWITCH signal after being driven by three states. SWITCH is high and all outputs are three states, and SWITCH is low and all outputs are enabled. SWITCH is the output signal of the active and standby control logic circuit. The main board SWITCH is low, and the standby board SWITCH is high.

The phase locking of the clocks of the active and standby boards is completed by the MT8941 to ensure that the clock frequency is equal to the reference clock frequency. The phase adjustment of the clock on the active and standby boards is completed by the programmable logic circuit X95108PQ100 to ensure that the phase of the clock is aligned with the phase of the reference clock.

The active/standby switching logic is completed by X95108PQ100. When the main board is pulled out, the pin corresponding to PLUGOUT of the board is offline first, PLUGOUT changes from low to high, ACTIVE1 changes from high to low, SWITCH changes from low to high, and the three-state output of the main board decreases to the standby board at the same time; Due to the cross-connection between the main and standby boards ACTIVE1 and ACTIVE2, the standby board ACTIVE2 changes from high to low, and SWITCH changes from high to low, and the output enable of the standby board rises to the master board at the same time. The time from PLUGOUT offline to switching completion is determined by the speed of the programmable logic device and the speed of the three-state driver, which is roughly 30ns in this implementation. This time is much smaller than the system clock cycle of 244ns. Through the actual test, it is known that the clock phase is continuous at the time of switching, and the data line is stable and continuous. The work of the system is not affected in any way, and the terminal image and sound are noiseless.

As mentioned above, jitter-free switching can minimize the impact of switching on the system, which greatly improves the stability of the system. At the same time, the system can be upgraded in software and hardware without power interruption, which enhances the maintainability of the system.

Compared with the patent of CN1245999A, the present invention does not adopt the interlocking mechanism of RS or JK flip-flops, but for the communication system, adopts special physical electrical structure, frequency and phase locking circuit and switching control circuit to solve the problem of the CN1245999A patent. Existing problems, to achieve a jitter-free switching.

Compared with the Japanese patent of JP-A-5-110425, this application implements a phase locking circuit for 8KHz and 50Hz clocks, and combines the master-standby switching control circuit to realize the jitter-free master-standby switch of clock data.

Claims (7)

1. A hot-swappable main-standby jitter-free switching device in a digital communication system, which is composed of two jitter-free switching circuits respectively located on the main board and the standby board. It is characterized in that: the two circuits have the same structure, including a frequency locking circuit, a phase locking circuit, a switching control circuit and an output buffer circuit; the frequency locking circuit is used to lock the frequency of the output clock to the frequency of the reference clock or the current internal clock on the main board; The phase locking circuit adjusts the phase of the frequency-locked clock and aligns it with the phase of the master clock. If the phase is already aligned, no adjustment is required; the switching control circuit is used to complete the master-standby switchover, ensuring that after the effective switchover instruction arrives, the first Output the clock and signal of the original standby board and make it active, then cut off the clock and signal output of the original main board and reduce it to standby, the final output is the output of the current main board, and the clock output feedback in this output To two phase-locked circuits, it is used as the input reference signal for phase adjustment. 2. The jitter-free switching device according to claim 1, wherein the pins of the two switching control circuits include power pins, ground pins, signal pins and offline signal pins, and the lengths of the pins are different. Or when the backup board is pulled out from the bottom board, ensure that the offline signal pin, signal pin, power pin and ground pin are disconnected from the bottom board in sequence. Connected; the offline signal pin on the main board or standby board is pulled up to the power supply, and the position corresponding to the offline signal pin on the backplane is directly grounded, and the offline signal pin is used as the online detection signal pin. 3. The jitter-free switching device according to claim 1 or 2, characterized in that: there is a default active and standby signal MS_SLI on the base plate, and the main board and the standby board are respectively connected with the signal to determine the The default state is active or standby; there are two active and standby control signals ACTIVE1 and ACTIVE2 respectively on the main board and the standby board, among which ACTIVE1 is the output and ACTIVE2 is the input, and they are transmitted through the communication lines cross-connected between the two circuits, namely The active and standby control signal ACTIVE1 on one board is output to the other board as the active and standby control signal ACTIVE2 input; the main board or the standby board comprehensively judges the default active and standby signal MS_SLI, the active and standby control signal ACTIVE2, and the online detection signal PLUGOUT through the switching control circuit 1, the current state signal STATE1, and the reset signal RESET are five conditions, and the switching operation is performed only when an effective switching instruction is detected. 4. The jitter-free switching device according to claim 1 or 2, characterized in that: the frequency locking circuit is composed of a phase-locked loop circuit; the phase-locking circuit is composed of a phase-locked loop circuit or a logic circuit. 5. The jitter-free switching device according to claim 3, characterized in that: the frequency locking circuit is composed of a phase-locked loop circuit; the phase-locking circuit is composed of a phase-locked loop circuit or a logic circuit. 6. A hot-swappable active/standby switching method without jitter in a digital communication system, comprising the following steps: Lock the frequency, that is: lock the clock of the main board and the standby board to the external clock source or the internal clock source on the current main board; Lock the phase, that is: align the clock phase on the standby board to the clock phase on the current main board; Output the clock and data of the main board, and the output of the standby board is prohibited; Judging whether there is an effective switching instruction, if not, maintain the original state; if there is, then: after a period of delay S2, output the clock and data of the original standby board, and upgrade the original standby board to the main board; after a period of delay S1, Turn off the clock and data of the original main board, and reduce the original main board to the standby board; where S1>S2, 0<S2<W, Δ<S1<W+Δ, W+Δ=clock equal level period, Δ=S1- S2, W = active switching period. 7. The jitter-free switching method according to claim 6, characterized in that: adjust the values of time S1 and S2 so that time S2 is equal to an integer multiple of the clock period, and perform switching across multiple clock periods. At this time, S1 and S2 Greater than the effective switching period W.

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