JP3922774B2 - Information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus that supplies an operation clock signal to a sub-module such as a communication module connected to a motherboard from a motherboard on which a main processor such as a main processor is mounted.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an information processing apparatus or the like composed of a main processor and a sub-module such as a communication control module and an input / output control module mounted in an expansion slot of a main board on which the main processor is mounted, the main processor side The operation clock signal is supplied to each submodule from the main processor, and each submodule is operated based on the operation clock signal from the main processor, or an oscillation circuit for generating an operation clock signal independent for each submodule. So that each submodule operates based on an independent operation clock signal.
[0003]
[Problems to be solved by the invention]
In recent years, the performance of information processing devices has continued to improve dramatically. With each new product development, the performance of the main processor or submodule has been improved, that is, the operation clock speed has been increased. It has been. At this time, it is necessary to increase the speed on the sub-module side in accordance with the speed increase on the main processor side. However, it is possible to cope with the case of facilitating maintenance or even when the main processor side has an old frequency operation clock. In order to be able to do so, the submodule side is adapted to support both old and new frequency operating clocks.
[0004]
For example, when supplying an operation clock signal to each submodule from the main processor side, the digital circuit is synchronized in terms of hardware. It can be easily realized by providing it as a circuit. Since the setting value of the timer used in the submodule needs to be changed according to the operation clock, for example, a setting pin is prepared in the submodule, and the setting pin is set according to the frequency of the supplied operation clock signal. A method is conceivable in which the setting is changed and the setting by the setting pin is read by the processor on the submodule side to set the timer.
[0005]
However, this method requires the operator to set the setting pins. Especially when there are a large number of submodules, it is a troublesome operation to set all the submodules. There is a possibility that a pin setting error may occur.
[0006]
Such troublesomeness or setting mistakes can be solved by providing an oscillation circuit independently for each submodule. However, when an oscillation circuit is provided in each submodule in this way, the cost increases accordingly, and it is necessary to synchronize the operation clocks between the main processor and each submodule. As a result, the circuit becomes complicated and a design error tends to occur.
[0007]
Therefore, the present invention has been made paying attention to the above-mentioned conventional unsolved problems, and it is possible to easily cope with a change in the frequency of the operation clock signal supplied from the main processing unit on the submodule side. An object is to provide a possible information processing apparatus.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, an information processing apparatus according to claim 1 of the present invention supplies an operation clock signal from a mother board provided with a main processing unit to a sub-module connected to the mother board. In the information processing apparatus, the sub-module has a clock frequency detection means for detecting the frequency of the operation clock signal from the motherboard side, and a timer frequency of the own timer or communication baud rate according to the detection frequency of the clock frequency detection means. And an operation item setting means for setting related operation items.
[0009]
In the first aspect of the invention, an operation clock signal is supplied from the main processing unit to the submodule, and the submodule operates based on the supplied operation clock signal. At this time, the submodule detects the frequency of the operation clock signal supplied by the clock frequency detection means when the submodule is in an initial state, for example, at the time of start-up, and determines its own timer or communication according to the detected frequency. The operation specification related to the clock frequency of the baud rate is set by the operation specification setting means, and the operation according to this operation specification is performed.
[0010]
In the information processing apparatus according to claim 2 of the present invention, the clock frequency detection means includes a frequency detection oscillation circuit for detecting the clock frequency, and the oscillation signal of the frequency detection oscillation circuit is used as a reference. The frequency of the operation clock signal is detected.
[0011]
In the invention according to claim 2, the clock frequency detecting means includes a frequency detecting oscillation circuit, for example, detecting the number of pulses of the oscillation signal of the frequency detecting oscillation circuit per pulse of the supplied operation clock signal. The frequency of the supplied operation clock signal is detected with reference to the oscillation signal of the frequency detection oscillation circuit.
[0012]
According to a third aspect of the present invention, there is provided the information processing apparatus according to the third aspect of the present invention, wherein the submodule is a submodule including an oscillation circuit such as a communication clock independent of the submodule, and the oscillation circuit is used for the frequency detection. It is characterized by being used as an oscillation circuit.
[0013]
In the invention according to claim 3, the submodule includes an oscillation circuit such as an independent communication clock, such as a communication module mounted on a motherboard including a main processor. The frequency of the operation clock signal is detected by the clock frequency detection means by being used as a detection oscillation circuit.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described. FIG. 1 shows an example of an information processing apparatus 50 according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a motherboard, and the motherboard 1 includes a main processor 11 as a main processing unit, ROM 12, RAM 13, and function expansion slots 21 to 23 are mounted, and these are connected via a processor bus 31. The sub-modules 41 to 43 are mounted in the function expansion slots 21 to 23 so that the main processor 1 communicates with the sub-modules 41 to 43 via the processor bus 31. .
[0015]
The motherboard 1 is provided with a clock generation circuit (not shown) having a crystal oscillator or the like for generating an operation clock signal. Each part mounted on the motherboard 1 is synchronized with the clock signal CLK1 generated by the clock generation circuit. The clock signal CLK1 is supplied to each of the sub modules 41 to 43 from the mother board 1 side.
[0016]
Each of the sub-modules 41 to 43 is, for example, an input / output module that performs input / output control processing or a communication control module that performs communication control processing, and can operate in response to any operation clock signal of 16 MHz or 25 MHz. It has become. As shown in FIG. 2, each of the sub modules 41 to 43 is mounted with a processor 100 and a clock frequency detection circuit (clock frequency detecting means) 120. The sub modules 41 to 43 include a motherboard. It operates in synchronization with a clock signal CLK1 supplied from the first side.
[0017]
The clock frequency detection circuit 120 is a circuit for detecting whether the supplied clock signal CLK1 has a frequency of 16 MHz or 25 MHz. As shown in FIG. A frequency dividing counter 101 for frequency dividing the clock signal CLK1 and a frequency divided signal CLK1 (1/8) divided by 1/8 by the frequency dividing counter 101 are synchronized and delayed with a reference clock signal CLK2 described later. D-type flip-flops 111 and 112, D-type flip-flops 113 and a NAND circuit 114 for detecting rising edges of signals synchronized by the D-type flip-flops 111 and 112, a crystal oscillator, and the like 50 MHz reference clock signal CLK2 for detecting the frequency of the clock signal CLK1 generated A reference clock generation circuit (frequency detection oscillation circuit) 110, a frequency detection counter 102 that detects the number of pulses of the reference clock signal CLK2 using the rising detection signal SU of the NAND circuit 114 as a trigger, and each D-type flip-flop 111 113 and a D-type flip-flop 115 for resetting the frequency detection counter 102, and an inverter 116 for stopping the frequency detection counter 102 when a ripple carry of the frequency detection counter 102 is detected. .
[0018]
The frequency dividing counter 101 and the frequency detecting counter 102 are composed of a 4-bit binary counter such as 74LS161, for example. In the frequency dividing counter 101, the clock signal CLK1 supplied from the mother board 1 side is input to the clock input terminal CK. Further, the voltage Vcc for fixing the input to these terminals to “H” is input to each of the count control input terminals ET and EP, the preset input terminal LD, and the reset input terminal CR, and data input for data presetting is performed. Terminals A, B, C, and D receive a voltage GND that fixes the input to these terminals to “L”. Of the first bit output terminal QA, which is the least significant bit of the frequency dividing counter 101, and the fourth bit output terminal QD, which is the most significant bit, the output signal of the third bit output terminal QC is the flip-flop 111. Input terminal D. That is, the frequency division counter 101 divides the clock signal CLK1 by 1/8, and the 1/8 frequency signal CLK1 (1/8) is supplied to the input terminal D of the flip-flop 111. It has become.
[0019]
A reference clock signal CLK2 generated by the reference clock generation circuit 110 is input to each clock input terminal CK of the D-type flip-flops 111 to 113, and a reset signal SC from a flip-flop 115 described later is input to the reset input terminal CR. Is entered. Then, the frequency division signal CLK1 (1/8) from the frequency division counter 101 is inputted to the input terminal D of the flip-flop 111, the non-inverted output of the flip-flop 111 is inputted to the input terminal D of the flip-flop 112, The non-inverted output of the flip-flop 112 is input to the input terminal D of the flip-flop 113, and the non-inverted output of the flip-flop 113 is input to the count control input terminal EP of the frequency detection counter 102. Further, the non-inverted output of the flip-flop 112 and the inverted output of the flip-flop 113 are input to the NAND circuit 114, and this output is input to the preset input terminal LD of the frequency detection counter 102 as the rising detection signal SU.
[0020]
The reference clock signal CLK2 is input to the clock input terminal CK of the frequency detection counter 102, and the first bit that is the most significant bit among the data input terminals A, B, C, and D for data presetting is set. The corresponding data input terminal A and the data input terminal D corresponding to the fourth bit, which is the least significant bit, receive the voltage GND that fixes the input to “L” and correspond to the second bit. The data input terminal B and the data input terminal C corresponding to the third bit are supplied with a voltage Vcc for fixing the input to “H”, and the reset input terminal CR is reset from a flip-flop 115 described later. A signal Sc is input. Then, the carry signal from the carry signal output terminal RC is output to the processor 100 as a RESULT signal and also input to the count control input terminal ET of the frequency detection counter 102 via the inverter 116.
[0021]
In the flip-flop 115, the CHECK signal for instructing frequency detection from the processor 100 is input to the input terminal D, the reference clock signal CLK2 from the reference clock generation circuit 110 is input to the clock input terminal CK, and The reset input terminal CR is supplied with a voltage Vcc for fixing the input to “H”. The non-inverted output of the flip-flop 115 is input as the reset signal SC to the flip-flops 111 to 113 and the reset input terminal CR of the frequency detection counter 102.
[0022]
Then, in the processor 100 of each of the submodules 41 to 43, in the initial state such as at the time of starting or resetting, the clock frequency detection instruction is issued to the clock frequency detection circuit 120 to operate the clock frequency detection circuit 120. In accordance with the detection frequency detected by the clock frequency detection circuit 120, predetermined operation parameters related to the clock frequency of the own timer or communication baud rate are set.
[0023]
That is, as shown in the flowchart of FIG. 3, the processor 100 outputs the CHECK signal for instructing frequency detection to “H” and outputs the clock frequency detection circuit 120 to the clock frequency detection circuit 120 when it is in an initial state such as start-up or reset start. (Step S1). Then, the RESULT signal from the clock frequency detection circuit 120 is monitored for a preset predetermined time (step S2), and it is determined whether or not the RESULT signal becomes “H” during this time (step S3). Note that the time for monitoring the RESULT signal is sufficient for the clock frequency detection circuit 120 to complete the determination of the frequency of the clock signal CLK1.
[0024]
When the RESULT signal becomes “H” for a predetermined time, the clock signal CLK1 is assumed to be 16 MHz, and the operation parameters to be set according to the clock signal CLK1 of its own timer or communication baud rate are as follows: It is set so as to correspond to 16 MHz (step S4). On the other hand, when the RESULT signal is “L”, the clock signal CLK1 is assumed to be 25 MHz, and the predetermined operation parameters are set to correspond to 25 MHz (step S5). Note that the processing of steps S3 to S5 corresponds to the operation specification setting means.
[0025]
When the setting of the operation parameters is completed according to the frequency of the clock signal CKL1, the CHECK signal is reset to “L” and the process is terminated (step S6). Next, the operation of the first embodiment will be described.
[0026]
Now, assuming that the motherboard 1 operates in response to a 16 MHz clock signal CLK1, a 16 MHz clock signal CLK1 is supplied to each of the submodules 41 to 43.
[0027]
The processor 100 of each of the submodules 41 to 43 changes the CHECK signal from “L” to “H” and outputs it when it is in an initial state such as at start-up or reset start. Since the reset signal SC is output as “H”, the flip-flops 111 to 113 change from the reset state to the operating state, and at this time, the frequency detection counter 102 changes from the reset state to the operable state.
[0028]
Then, the clock signal CLK1 supplied to each of the submodules 41 to 43 is input to the frequency dividing counter 101, and as shown in FIG. 4, the clock signal CLK1 (FIG. 4A) is frequency-divided by 1/8. The frequency-divided signal CLK1 (1/8) (FIG. 4B) is input to the input terminal D of the flip-flop 111.
[0029]
Here, since the reference clock generation circuit 110 generates the reference clock signal CLK2 of 50 MHz (FIG. 4C), the divided signal CLK1 (1/8) is converted into the reference clock signal CLK2 by the flip-flops 111 to 113. Synchronized and delayed (FIGS. 4D to 4F).
[0030]
Then, from the output of the flip-flop 112 (FIG. 4E) and the inverted output of the flip-flop 113 (FIG. 4G), the rise of the output of the flip-flop 112, that is, the divided signal CLK1 (1/8). Is detected by the NAND circuit 114, and this rising detection signal SU (FIG. 4 (h)) is input to the preset input terminal LD of the frequency detection counter 102. Therefore, the frequency detection counter 102 At the rising edge of the signal CLK1 (1/8), each bit is preset to “0110”, and “6” is set in decimal. Then, as shown in FIG. 4, from time t2 when the frequency detection counter 102 is preset at time t1, the input to the count control terminal ET is "H", and the non-inverted output of the flip-flop 113 is "H". When the frequency detection counter 102 starts counting, the count value is counted up from the preset value “6” at the rising edge of the reference clock signal CLK2 (FIG. 4 (i)), and overflows at time t3. The output of the carry signal output terminal RC, that is, the RESULT signal is output as “H”. As a result, the input to the count control terminal ET becomes “L”, and the frequency detection counter 102 stops counting up.
[0031]
At this time, since the processor 100 of the submodules 41 to 43 monitors the RESULT signal for a predetermined time, when the RESULT signal is output as “H”, this is detected, and the clock signal CLK1 is determined to be 16 MHz. Then, the operation parameters relating to the clock frequency of its own timer or communication baud rate are set to 16 MHz, and the CHECK signal is reset to “L”.
[0032]
In the clock frequency detection circuit 120, when the CHECK signal becomes “L”, the flip-flops 111 to 113 and the frequency detection counter 102 are reset, and the operation is stopped.
[0033]
On the other hand, when the clock signal CLK1 supplied from the motherboard 1 is 25 MHz, as shown in FIG. 5, the clock signal CLK1 (FIG. 5A) input to the frequency dividing counter 101 in the same manner as described above. Is divided by 1/8, and this divided signal CLK1 (1/8) (FIG. 5 (b)) is synchronized with the reference clock signal CLK2 (FIG. 5 (c)) by the flip-flops 111-113. And delayed ((FIGS. 5D to 5F)), the NAND circuit 114 generates a frequency-divided signal CLK1 (from the non-inverted output of the flip-flop 112 and the inverted output of the flip-flop 113 (FIG. 5G)). When the rising edge detection signal SU (FIG. 5 (h)) becomes "L", the frequency detection counter 102 is preset to decimal "6" (time t11). ) At this time, since the input signal to the counter control input terminal EP becomes “H”, the frequency detection counter 102 starts counting at the rising edge (time t12) of the reference clock signal CLK2. When the input signal to the terminal EP becomes “L”, the count-up is finished at time t13.
[0034]
When the rising edge detection signal SU becomes "L" again at time t14, the frequency detection counter 102 is preset, starts counting up at time t15, and the input signal to the counter control input terminal at time t16 is " Since it is L ″, the count-up is finished.
[0035]
Therefore, when the clock signal CLK1 is 25 MHz, since the input signal to the counter control input terminal becomes “L” before the frequency detection counter 102 overflows, the RESULT signal maintains “L”. . Therefore, since the RESULT signal does not become “H” during the monitoring time monitored by the processor 100, the processor 100 determines that the clock signal CLK1 is 25 MHz, and sets a predetermined operation specification for 25 MHz. Then, the CHECK signal is reset to “L”. Thereby, the operation of the clock frequency detection circuit 120 is completed.
[0036]
Accordingly, as described above, the reference clock signal CLK2 while the input signal to the count control input terminal EP of the frequency detection counter 102 is “H” is counted, and the clock signal CLK1 is “H”. The number of pulses of the reference clock signal CLK2 is counted. When the clock signal CLK1 is 16 MHz, the frequency detection counter 102 overflows. When the clock signal CLK1 is 25 MHz, the overflow signal does not overflow. The frequency of the clock signal CLK1 can be determined depending on whether is “H” or “L”.
[0037]
Therefore, even if the supplied clock signal CLK1 is either 25 MHz or 16 MHz, the operator can automatically detect the frequency and set the predetermined operation parameters accordingly. The troublesomeness of setting the frequency of the clock signal can be avoided, and human errors such as setting mistakes due to the setting of the frequency of the clock signal by the operator can be avoided.
[0038]
In addition, since the frequency is automatically detected and the operation parameters related to the clock frequency of its own timer or communication baud rate are set accordingly, even when the clock frequency of the motherboard 1 is 25 MHz, it is 16 MHz. Even in some cases, the submodules 41 to 43 can be mounted on the mother board 1 without any change.
[0039]
Further, each of the submodules 41 to 43 operates based on the same clock signal CLK1 supplied from the motherboard 1 side, so there is no need to synchronize between the motherboard 1 side and the submodule side. The circuit configuration can be simplified.
[0040]
In the above-described embodiment, the case where the frequency of the clock signal CLK1 is detected to be 25 MHz or 16 MHz has been described. However, the present invention is not limited to this, and an arbitrary frequency can be determined. In addition, the frequency division ratio of the clock signal CLK1 and the frequency CLK2 of the reference clock signal are set so that the two frequencies can be discriminated even if the two frequencies are the same frequency, and the frequency detection is performed accordingly. If the preset value of the counter 102 is set, the frequency can be determined in the same manner as described above.
[0041]
In the above-described embodiment, the case where two types of frequencies are discriminated has been described. However, it is possible to discriminate even when there are three or more types of frequencies. What is necessary is just to add the counter for frequency detection according to the kind of. That is, in the case of 10 MHz, 16 MHz, and 25 MHz, the first frequency detection counter is set to overflow at 10 MHz and 16 MHz and not to overflow at 25 MHz, and at the second frequency detection counter, at 10 MHz. If the overflow is set so that it does not overflow at 16 MHz and 25 MHz, if both the first and second frequency detection counters overflow, the frequency is 10 MHz, and if both do not overflow, the frequency is either 25 MHz. If only overflows, the frequency can be determined as 16 MHz.
[0042]
In the above embodiment, the case where the clock frequency detection circuit 120 is provided in each of the submodules 41 to 43 has been described. However, for example, a clock circuit specific to the submodule, such as a communication control module, is already mounted. In this case, the clock signal generated by the clock circuit can be used as the reference clock signal CLK2, and in this case, the frequency division ratio or frequency detection counter 102 can be used in accordance with the reference clock signal CLK2. A preset value may be set. By doing so, cost reduction can be achieved.
[0043]
In the above-described embodiment, the case where the frequency is determined based on whether the carry signal is “H” has been described. For example, the count value of the frequency detection counter 102 is May be determined based on the size.
[0044]
Furthermore, in the above embodiment, the case where the processor 100 monitors the RESULT signal for a predetermined time has been described. However, a latch circuit is provided on the output side of the carry signal output terminal RC of the frequency detection counter 102. The processor 100 may read the RESULT signal when a sufficient time has elapsed after the processor 100 outputs the CHECK signal as “H” and the frequency detection by the clock frequency detection circuit 120 is completed. Good.
[0045]
【The invention's effect】
As described above, according to the information processing apparatus of the first aspect of the present invention, the frequency of the operation clock signal supplied from the main processing unit is detected by the clock frequency detection means of the submodule, and according to the detected frequency. Since the operation parameters related to the clock frequency of its own timer or communication baud rate are set by the operation parameter setting means according to the detected frequency, the frequency detection and the operation parameter setting according to the detected frequency are set. Can be carried out easily and accurately.
[0046]
According to the information processing apparatus of the second aspect of the present invention, since the frequency of the input operation clock signal is detected based on the oscillation signal of the frequency detection oscillation circuit, the frequency of the operation clock signal is It can be easily detected.
[0047]
According to the information processing apparatus of the third aspect of the present invention, the oscillation signal of the oscillation circuit such as the communication clock mounted in advance in the submodule is used as the oscillation signal of the frequency detection oscillation circuit. Therefore, it is not necessary to provide a new oscillation circuit, and the cost can be reduced accordingly.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating an example of an information processing apparatus according to the present invention.
FIG. 2 is a circuit diagram showing an example of a clock frequency detection circuit.
FIG. 3 is a flowchart illustrating an example of a processing procedure when setting operation specifications according to a clock frequency in a processor of a submodule according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram for explaining the operation of the embodiment of the present invention.
FIG. 5 is an explanatory diagram for explaining the operation of the embodiment of the present invention;
[Explanation of symbols]
1 Motherboard
11 Main processor
41-43 Submodule
100 processor
101 Dividing counter
102 Frequency detection counter
110 Reference clock generation circuit
111-113,115 D-type flip-flop
120 clock frequency detection circuit
CLK1 clock signal
CLK1 (1/8) divided signal
CLK2 reference clock signal

Claims (3)

An operation clock signal corresponding to the performance of the main processing unit is supplied from a motherboard including the main processing unit to a submodule connected to the motherboard so that the submodule operates in synchronization with the operation clock signal. In the information processing apparatus
The sub-module includes a clock frequency detection means for detecting the frequency of the operation clock signal from the motherboard side, the operation specifications relating to the clock frequency of the self-timer or the communication baud rate in response to the detection frequency of the clock frequency detection means An information processing apparatus comprising: operation specification setting means for setting  The clock frequency detection means includes a frequency detection oscillation circuit for detecting the clock frequency, and detects the frequency of the operation clock signal with reference to an oscillation signal of the frequency detection oscillation circuit. The information processing apparatus according to claim 1.  The sub-module is a sub-module provided with an oscillation circuit such as a communication clock independent of the sub-module, wherein the oscillation circuit is used as the frequency detection oscillation circuit. 2. The information processing apparatus according to 2.

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