CN1277363C - Method for interlocking control of master backup timer - Google Patents
Method for interlocking control of master backup timer Download PDFInfo
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- CN1277363C CN1277363C CN 02128332 CN02128332A CN1277363C CN 1277363 C CN1277363 C CN 1277363C CN 02128332 CN02128332 CN 02128332 CN 02128332 A CN02128332 A CN 02128332A CN 1277363 C CN1277363 C CN 1277363C
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Abstract
The present invention relates to an interlocking control method for main preparing clocks in communications devices. The present invention is characterized in that two clock plates respectively generate own first output clocks, frequency divided clocks and second output clocks, the second output clocks are respectively used as interlocking signals to be sent to output frequency dividing units and source selecting modules of counterparts. The output frequency dividing unit of a main use clock plate is used for directly processing the frequency divided clock in a frequency dividing way into a second main use clock in a main use clock plate. When the output frequency dividing unit of the spare clock plate is used for processing the frequency divided clock in a frequency dividing way in the spare clock plates, the phases of a second spare output clock are controlled according to the interlocking signals, and thereby, the second main use output clock and the second spare output clock have the same phase. When the external clock source is normal, the two clock plates are used for simultaneously tracking the external clock source. On the occasion of no external clock sources, the spare clock plate is used for tracking the interlock signals sent by the main use clock plate. The method of the present invention can enable actual phase difference between the second output clocks of the two clock plates to be reduced within the range of five ns so as to realize the smooth switchover between the two clock plates.
Description
Technical field
The present invention relates to the communications field, more particularly, relate to a kind of method for interlocking control of master backup timer that is used for communication equipment.
Background technology
In the switch or miscellaneous equipment of the communications field, need provide clock for equipment by special clock board, for guaranteeing the continous-stable operation of equipment, usually require its clock internal plate to have redundancy backup, promptly be provided with two clock boards, when wherein a clock board breaks down, can work on by another piece clock board, thereby can not cause the paralysis of whole system, the attendant can detect maintenance to the clock board that breaks down simultaneously.
In the prior art, between two clock boards and the method for work between they and the external clock reference have two kinds: wherein a kind of method is that two clock boards are taked biplane work, follows the tracks of external clock reference separately, not influenced by the other side.In this method, as shown in Figure 1, in the middle of wherein being positioned at is the external clock source signal, two is respectively that two clock boards are followed the tracks of the signal of exporting behind the external clock reference up and down, though the frequency of two clock boards is all consistent with external clock reference, but owing to follow the tracks of external clock reference respectively separately, the signal of two clock boards has the uncertain worker of a differing A1 and A2 with external clock reference respectively, and between two clock boards to differ A just more uncertain.When one leading and another when lagging behind, the A that differs between the signal of two clock board outputs can be bigger.If monolithic clock board and external clock reference maximum differ and be W, then differ A=A1+A2 between two clock boards, maximum can reach 2W.If wherein a clock board broke down and need switch this moment, just have a very big phase hit, can't accomplish to take over seamlessly, the equipment that also just can't guarantee can be worked continuously and stably.
Another kind method is that two clock boards are divided into main using and the standby clock plate, and only the active clock plate is followed the tracks of external clock reference, and the standby clock plate is followed the tracks of the interlocking signal that the active clock plate is sent here.As shown in Figure 2, wherein be external clock reference, the main signal of using with the standby clock plate from top to bottom successively.In this method, differing between active clock plate and the external clock reference is B1; The standby clock plate is followed the tracks of the output signal of active clock plate, differing between the two is B2, its maximum is W, obviously less than the 2W in preceding a kind of method, thereby can reduce the main uncertainty that differs with the output of standby clock plate of using, but this phase difference is still bigger, reaches microsecond (μ s) to millisecond (ms) level, still can not accomplish to take over seamlessly.And break down when switching at the active clock plate, the standby clock plate can not be followed the tracks of the active clock plate again, it need be switched to direct tracking external clock reference, and This move can bring new problem, influences working continuously and stably of equipment.
Summary of the invention
The technical problem to be solved in the present invention is, above-mentioned defective at prior art, a kind of new method for interlocking control of master backup timer is provided, make main use and the standby clock plate between differ and reduce to minimum, to realize leading taking over seamlessly between usefulness and the standby clock, guarantee the connection steady operation of its place equipment.
Technical program of the present invention lies in, a kind of interlock control method of master/backup clock, wherein,
A, two clock boards generate separately first clock signal respectively, by the sub-frequency clock signal and second clock signal, and respectively its second clock signal is delivered to the other side's output frequency division unit and selected source module as interlocking signal, the source module (11) that selects of described two clock boards connects same external clock reference, the source module (11) that selects of two clock boards masks the interlocking signal of being sent here by the other side's clock board, follows the tracks of described external clock reference simultaneously;
B, in the active clock plate, its output frequency division unit masks the interlocking signal of being sent here by the standby clock plate, will lead to use by the direct frequency division of sub-frequency clock signal to be treated to main second clock signal of using;
C, in the standby clock plate, its output frequency division unit is being carried out frequency division when handling to standby by sub-frequency clock signal, control the phase place of standby second clock signal according to the interlocking signal of sending here by the active clock plate, under the high frequency trigger impulse, as detect the rising edge of interlocking signal, then divide the rising edge that occurs frequently, as detect the trailing edge of interlocking signal, then divide the trailing edge that occurs frequently, thus output and main with synchronous standby second clock signal of second clock signal.
Among the present invention, describedly obtained by following steps: produce the local oscillator clock by the constant-temperature crystal oscillator unit, be treated to reference clock through first frequency multiplication of phase locked loop again and offer the DDS device as the reference clock by sub-frequency clock signal; Under the control of CPU,, obtain described first clock signal through behind the filter shape again by high frequency clock signal of DDS device output; Described first clock signal obtains described by sub-frequency clock signal after second frequency multiplication of phase locked loop is handled.
Described two clock boards are followed the tracks of external clock reference according to the following steps: by selecting source module and phase demodulation frequency unit respectively with the phase discrimination signal that is processed into same frequency by sub-frequency clock signal of external clock reference and this clock board, deliver to a phase discriminator again; Described phase discriminator is delivered to described CPU with its phase demodulation value, and CPU calculates the DDS value by the software filtering algorithm and delivers to described DDS device, and the DDS device is exported first clock signal consistent with the external clock source frequency under described DDS value control.
Adopt method of the present invention can make main use and the standby clock plate between differ and reduce to minimum, if its control circuit adopts the highest triggering clock of place system, 116M for example, then in theory can with main with standby clock between relevant being controlled in 4.3 nanoseconds (ns), can realize leading taking over seamlessly between usefulness and the standby clock, guarantee the connection steady operation of its place equipment.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is that two clock boards are followed the tracks of external clock reference and the oscillogram when working alone simultaneously in the prior art;
Fig. 2 is that the active clock plate is followed the tracks of external clock reference, the oscillogram when the standby clock plate is followed the tracks of the active clock plate in the prior art;
Fig. 3 is the inside theory diagram of clock board among the present invention;
Fig. 4 is the main schematic diagram of using when following the tracks of external clock reference and interlocking work simultaneously with the standby clock plate among the present invention.
Embodiment
In the method for the present invention, the hardware configuration of two clock boards and the software of adorning identical, when wherein one be chosen as the active clock plate after, another piece is then as the standby clock plate, this moment, both mode of operations were with different.
The inside theory diagram of clock board among the present invention as shown in Figure 3.At first, produce the local oscillator clock that frequency is 8MHz, after first phase-locked loop, 12 process of frequency multiplication, become the reference clock of 98MHz, offer DDS (directly frequency synthesis) device 3, CPU 6 and phase discriminator 7 respectively as the reference clock by constant-temperature crystal oscillator unit 1; Under the control of CPU 6, DDS device 3 obtains first clock signal again according to the high frequency clock signal of a 19.44MHz of this reference clock output after crystal filter unit 4 and shaping unit 5 processing, and its frequency is 19.44MHz.19.44MHz first clock signal after second phase-locked loop, 9 process of frequency multiplication, can obtain 116MHz by sub-frequency clock signal, this is sent to output frequency division unit 10 again by sub-frequency clock signal, obtains second clock signal of 8KHz after frequency division is handled.
As can be seen from Figure 3, select the input signal of source module 11 to comprise external clock reference and the 8KHz interlocking signal of sending here by the other side's clock board; The 8KHz interlocking clock signal that the 116MKHz that the input signal of output frequency division unit 10 comprises this clock board is sent here by sub-frequency clock signal and the other side's clock board.
The present invention is having under the situation of external clock reference, and two clock boards are followed the tracks of this external clock reference simultaneously, and interlocking signal is used for controlling the synchronous of master and spare clock plate phase position.If there is not external clock reference, then active clock plate free-running operation; The standby clock plate is followed the tracks of the interlocking signal that the active clock plate is sent here, with the main interlocking signal of sending here with the clock plate as external clock reference.
One, two clock boards are followed the tracks of external clock simultaneously
Schematic diagram when two clock boards are followed the tracks of external clock simultaneously as shown in Figure 4, this moment, main using with the standby clock plate was connected same external clock reference and interlocking work, wherein:
1-1, the main 8KHz interlocking signal of using with the standby clock plate that selects source module all to mask to send here by the other side's clock board, both select source module 11 and phase demodulation frequency unit 8 respectively with the phase discrimination signal that is processed into same frequency (500Hz) by sub-frequency clock signal of external clock reference and 116MHz, input phase discriminator 7, by phase discriminator its phase demodulation value is delivered to CPU again, CPU calculates the DDS value and delivers to DDS device 3 by the software filtering algorithm, the DDS device is under the control of DDS value, export first clock signal consistent, reach the purpose of following the tracks of external clock reference with the external clock source frequency.First clock signal is consistent with the external clock source frequency, is not to want the frequency of the two identical, and is meant between both frequency that a fixing coefficient relation is arranged.
1-2, in the active clock plate, its output frequency division unit masks the 8KHz interlocking signal of being sent here by the standby clock plate, and the 116MHz of this clock board is treated to 8KHz second clock signal by the direct frequency division of sub-frequency clock signal.
1-3, in the standby clock plate, its output frequency division unit is when being carried out the frequency division processing to 116MHz is standby by sub-frequency clock signal, control the phase place of standby second clock signal according to the interlocking signal of sending here by the active clock plate, under the high frequency trigger impulse, as detect the rising edge of interlocking signal, then divide the rising edge that occurs frequently, as detect the trailing edge of interlocking signal, then divide the trailing edge that occurs frequently; Lead the 8KHz second clock signal same-phase of using with the standby clock plate thereby allow.
In fact, reason owing to aspects such as hardware and running software speed, main use and 8KHz second clock signal of standby clock plate between always have certain phase difference, for obtaining minimum phase difference, the high frequency trigger impulse of the control circuit of two clock boards should adopt the highest frequency clock of system, just uses the highest frequency (the fastest speed) to control output frequency division unit 10 courses of work.Among the present invention, can adopt 116MHz as triggering frequency, in theory can with main use and 8KHz second clock signal of standby clock plate between differ and be controlled in 4.3 nanoseconds (ns), much smaller than microsecond level of the prior art even Millisecond phase difference.
The error that the present invention causes for the reasons such as circuit delay of eliminating clock signal, be not that 8KHz second clock signal of two clock boards is directly delivered to the other side as interlocking signal, but it is shifted to an earlier date one-period, deliver to the other side's output frequency division unit then respectively.
Two, active clock plate free-running operation, the standby clock plate is followed the tracks of active clock
Among the present invention, if there is not external clock reference, then the master uses with the course of work of standby clock plate as follows:
The 8KHz interlocking signal that selects source module to mask to send here of 2-1, active clock plate by the standby clock plate, any clock source is not followed the tracks of in free-running operation; The standby clock plate is followed the tracks of the interlocking signal that the active clock plate is sent here, the 8KHz interlocking signal that is equivalent to send here with the active clock plate is as external clock reference, it selects source module and phase demodulation frequency unit respectively the 500Hz phase discrimination signal that is processed into by sub-frequency clock signal of 8KHz interlocking signal and 116MHz to be imported phase discriminator, by phase discriminator its phase demodulation value is delivered to CPU again, CPU calculates the DDS value and delivers to the DDS device by the software filtering algorithm, the DDS device is under the control of DDS value, export first clock signal consistent, reach and follow the tracks of the interlocking signal purpose that active clock is sent here with 8KHz interlocking signal frequency.
2-2, in the active clock plate, its output frequency division unit masks the 8KHz interlocking signal of being sent here by the standby clock plate, and the 116MHz of this clock board is treated to 8KHz second clock signal by the direct frequency division of sub-frequency clock signal.
2-3, in the standby clock plate, its output frequency division unit is when being carried out the frequency division processing to 116MHz is standby by sub-frequency clock signal, control the phase place of standby second clock signal according to the 8KHz interlocking signal of sending here by the active clock plate, under the high frequency trigger impulse, as detect the rising edge of interlocking signal, then divide the rising edge that occurs frequently, as detect the trailing edge of interlocking signal, then divide the trailing edge that occurs frequently; Lead the 8KHz second clock signal same-phase of using with the standby clock plate thereby allow.
The difference of the working condition when contrast has external clock reference and do not have external clock reference below:
(1), when external clock reference is arranged, the source module that selects of master/backup clock plate all selects external clock reference to follow the tracks of, interlocking signal is used for controlling the Phase synchronization of master/backup clock plate;
(2), when not having external clock reference, the active clock plate freely shakes, interlocking signal is used for controlling the Frequency Synchronization of standby clock plate and active clock plate.
Apply the present invention to concrete equipment, when main use with standby clock plate tenacious tracking on behind the external clock reference, differing between 8KHz second output signal of both outputs less than 5ns.When system's full configuration is put operation, switch the clock plane and lose the cell phenomenon, can realize taking over seamlessly.
Claims (7)
1, a kind of interlock control method of master/backup clock, wherein,
A, two clock boards generate separately first clock signal respectively, by the sub-frequency clock signal and second clock signal, and respectively its second clock signal is delivered to the other side's output frequency division unit (10) and selected source module (11) as interlocking signal, the source module (11) that selects of described two clock boards connects same external clock reference, the source module (11) that selects of two clock boards masks the interlocking signal of being sent here by the other side's clock board, follows the tracks of described external clock reference simultaneously;
B, in the active clock plate, its output frequency division unit masks the interlocking signal of being sent here by the standby clock plate, will lead to use by the direct frequency division of sub-frequency clock signal to be treated to main second clock signal of using;
C, in the standby clock plate, its output frequency division unit is being carried out frequency division when handling to standby by sub-frequency clock signal, control the phase place of standby second clock signal according to the interlocking signal of sending here by the active clock plate, under the high frequency trigger impulse, as detect the rising edge of interlocking signal, then divide the rising edge that occurs frequently, as detect the trailing edge of interlocking signal, then divide the trailing edge that occurs frequently, thus output and main with synchronous standby second clock signal of second clock signal.
2, method according to claim 1 is characterized in that, in described two clock boards, is describedly obtained by following steps by sub-frequency clock signal:
Producing the local oscillator clock by constant-temperature crystal oscillator unit (1), is that reference clock offers DDS device (3) conduct with reference to clock through first phase-locked loop (2) process of frequency multiplication again;
Under the control of CPU (6),, obtain described first clock signal through behind the filter shape again by high frequency clock signal of DDS device (3) output;
Described first clock signal obtains described by sub-frequency clock signal after second phase-locked loop (9) process of frequency multiplication.
3, method according to claim 2 is characterized in that, described two clock boards are followed the tracks of external clock reference according to the following steps:
By selecting source module (11) and phase demodulation frequency unit (8), deliver to a phase discriminator (7) more respectively with the phase discrimination signal that is processed into same frequency by sub-frequency clock signal of external clock reference and this clock board;
Described phase discriminator (7) is delivered to described CPU (6) with its phase demodulation value, described CPU (6) calculates the DDS value and delivers to described DDS device (3) by the software filtering algorithm, described DDS device (3) is exported first clock signal consistent with the external clock source frequency under described DDS value control.
4, method according to claim 3 is characterized in that, described external clock reference comprises the interlocking signal as external clock.
5, according to each described method among the claim 1-4, it is characterized in that, in described steps A, second clock signal of two clock boards is shifted to an earlier date one-period output, deliver to the other side's clock board as interlocking signal respectively.
According to each described method among the claim 1-4, it is characterized in that 6, in described step C, the high frequency trigger impulse that control circuit adopted of standby clock plate is the maximum clock of its place system.
7, according to each described method among the claim 2-4, it is characterized in that, the frequency of described local oscillator clock is 8MHz, the frequency of reference clock is 98MHz, the frequency of described first clock signal is 19.44MHz, by the frequency of sub-frequency clock signal is 116MHz, and the frequency of phase discrimination signal is 500Hz; The frequency of second clock signal is 8KHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02128332 CN1277363C (en) | 2002-07-30 | 2002-07-30 | Method for interlocking control of master backup timer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02128332 CN1277363C (en) | 2002-07-30 | 2002-07-30 | Method for interlocking control of master backup timer |
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| Publication Number | Publication Date |
|---|---|
| CN1472912A CN1472912A (en) | 2004-02-04 |
| CN1277363C true CN1277363C (en) | 2006-09-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02128332 Expired - Fee Related CN1277363C (en) | 2002-07-30 | 2002-07-30 | Method for interlocking control of master backup timer |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655455B (en) * | 2004-02-10 | 2010-04-28 | 中兴通讯股份有限公司 | Method and apparatus for handling reversion of primary and secondary clock systems |
| CN100338967C (en) * | 2005-05-19 | 2007-09-19 | 北京北方烽火科技有限公司 | Method and apparatus for realizing clock redundancy back-up in WCDMA system base station |
| CN101197650B (en) * | 2007-11-21 | 2012-11-07 | 上海华为技术有限公司 | Clock synchronization device and method |
| CN107396326A (en) * | 2017-08-02 | 2017-11-24 | 北京北方烽火科技有限公司 | A kind of method and master clock system for generating System Frame Number |
| CN112583512B (en) * | 2020-12-10 | 2023-04-11 | 北京航星机器制造有限公司 | Time synchronization device and method |
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Granted publication date: 20060927 Termination date: 20170730 |