CN1655455B - Method and apparatus for handling reversion of primary and secondary clock systems - Google Patents
Method and apparatus for handling reversion of primary and secondary clock systems Download PDFInfo
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- CN1655455B CN1655455B CN 200410046457 CN200410046457A CN1655455B CN 1655455 B CN1655455 B CN 1655455B CN 200410046457 CN200410046457 CN 200410046457 CN 200410046457 A CN200410046457 A CN 200410046457A CN 1655455 B CN1655455 B CN 1655455B
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Abstract
The present invention discloses a method of disposing the reversing of the master backup in the clock system, includes: making the quartz clocks of the main and spare clock system arrive at the clock selective circuit through the rear panel; the clock selective circuits all choose the quartz clock of the clock system as output; locking down the output of the clock selective circuit with phase lock loop circuit, obtain the output clock of the main and spare clock system; the output clock is driven to each business unit point-to-point. The invention also discloses a sort of equipment for disposing the reversing of the master backup in the clock system, characterized in that the main and spare clock system comprise a quartz, a clock selective circuit, a phase lock loop circuit and a clock driver circuit. The present invention settles the problems that the clock phase differs greatly and the error code percentage is high during the reversing procedure of the master backup.
Description
Technical field
The present invention relates to communication field and other electronic applications, especially relate to a kind of processing clock system's main and device.
Background technology
At present, along with the fast development of broadband network, the user has not only proposed high request to the content of network service, and the quality of network service is also more and more paid attention to, and this reliability to communication apparatus has proposed more and more higher requirement.In order to improve the reliability of system, the most frequently used method is core board to be adopted the mode of active and standby work, when the master breaks down with core board, by masterslave switchover, business is transferred on the spare core core of energy operate as normal.Along with the raising of user, must higher requirement have been proposed to the error rate of system in the masterslave switchover process to the network service quality requirement.And in electronic equipment, clock is the basis of all signals.In present most main stock redundance system, general way is that the work clock of active and standby core board is separate, realize simpler like this, yet because the phase place of the work clock of active and standby core board is different, in the masterslave switchover process of core board, each service board bigger variation can occur from the phase place of the clock signal that core board obtains, and will inevitably produce bigger error code.
Fig. 1 is the block diagram of the present main/slave clock system of using always.Its specific implementation is: main/slave clock system outputs to each service board with the crystal oscillator output clock of oneself through clock driver circuit separately, and each service board is selected clock that the active clock system the sends work clock as this plate by clock selection circuit.Suppose that clock system 110 is the active clock system, clock system 120 is the standby clock system.Crystal oscillator 111 clock signal ClkA on the clock system 110 and the crystal oscillator 121 clock signal ClkB on the clock system 120 arrive each service board by local clock driver circuit output clock separately.Each service board is all selected clock that the active clock system sends here and is carried out clock output after phase-locked as the work clock of this service board by phase-locked loop circuit when operate as normal, for example when clock system 110 is the active clock system, the clock selection circuit of n piece service board 140 can select Cardn-ClkA and the clock output Cardn-Clk after phase-locked through phase-locked loop 141 as work clock.Because ClkA is through guaranteeing that phase place is consistent between the output of the multichannel behind the clock driver circuit 112 (Card1-ClkA is to Cardn-ClkA), ClkB be through can guaranteeing that also phase place is consistent between the output of the multichannel behind the clock driver circuit 122 (Card1-ClkB is to Cardn-ClkB), so the work clock during each service board operate as normal is synchronous.But because crystal oscillator 111 is uncontrollable with the output ClkA of crystal oscillator 121 these two different crystal oscillators and the phase place of ClkB, therefore to output to the phase place of the two-way clock signal on the every service board (from veneer 1 to veneer n) be uncontrollable for clock system 110 and clock system 120, if system's generation masterslave switchover, thereby active clock system 110 also can switch to standby clock system 120, promptly in reversed process, the work clock of service board 140 will be switched to Cardn-ClkB by Cardn-ClkA.If the phase place of clock ClkA and clock ClkB has big difference, on each service board, because the randomness of the work of phase-locked loop, phase-locked loop that might certain veneer i is caught up with final locking Cardi-ClkB forward, and the phase-locked loop of certain veneer j is caught up with final locking Cardi-ClkB backward, like this phase place unstable to stable (pll lock clock) back veneer i and veneer j to the counts differ of clock a clock cycle, the phase difference of veneer i and veneer j is bigger in the process of clock stable simultaneously, caused in system's reversed process the error rate higher like this, even veneer i and veneer j can occur in some occasion and do not contact and cause some devices on certain piece veneer such as the work of network processing unit to recover.
Want to realize core board the seamlessly transitting of customer service in the masterslave switchover process, this just is consistent to the phase place of master/backup clock and has proposed high request.
Summary of the invention
Technical problem to be solved by this invention provides a kind of processing clock system's main and device, and solution core board clock phase in the masterslave switchover process has big difference, error rate problem of higher.
For achieving the above object, the invention provides a kind of processing clock system main, be used to finish switching of active and standby clock system, its characteristics are, comprise the steps:
Step 1, the crystal oscillator clock that makes active and standby clock system all arrive the input of the clock selection circuit of two clock systems by backboard;
Step 2, the clock selection circuit of active and standby clock system all select crystal oscillator clock in the active clock system as output;
Step 3 locks by the output of the phase-locked loop circuit on the active and standby clock system to the clock selection circuit on this clock system, obtains the output clock of active and standby clock system;
Step 4 is driven into each service board by the clock driver circuit on the active and standby clock system with described output clock point-to-pointly.
Above-mentioned method, its characteristics are, also include:
Step 5 makes the clock selection circuit on each service board select the output clock of active clock system as output all the time;
Step 6, the phase-locked loop circuit on each service board lock and flow to the operating circuit of this service board to the output of the clock selection circuit on this veneer.
Above-mentioned method, its characteristics be, in described step 1, also comprise the clock selection circuit input that makes described two clock systems the step that is consistent of the phase place that receives respectively from the crystal oscillator clock of same clock system.
Above-mentioned method, its characteristics be, in described step 4, also comprises the step that the phase place from the described output clock of same clock system that makes that described each service board receives is consistent.
Above-mentioned method, its characteristics are, in described step 6, also comprise the step of the feedback line length that the phase-locked loop circuit on described each service board is set.
The invention also discloses the device of a kind of processing clock system masterslave switchover, comprise active and standby clock system, backboard and service board, its characteristics are that described active and standby clock system all includes crystal oscillator, clock selection circuit, phase-locked loop circuit and clock driver circuit;
Described crystal oscillator produces a crystal oscillator clock and sends described clock selection circuit to;
Described clock selection circuit is used to select the crystal oscillator clock of active clock system and exports to described phase-locked loop circuit;
Described phase-locked loop circuit is used to lock the output of described clock selection circuit, produces the output clock of this clock system;
Described clock driver circuit is used for described output clock is sent to described service board through described backboard is point-to-point;
Described crystal oscillator all connects the input of the clock selection circuit of described active and standby clock system by described backboard, described clock selection circuit connects described clock driver circuit through described phase-locked loop circuit, described clock driver circuit connects described service board through described backboard, described clock selection circuit is selected the crystal oscillator clock of active clock system and through the described output clock of described phase-locked loop circuit locking back generation, and described clock driver circuit sends to described service board with described output clock through described backboard is point-to-point.
Above-mentioned device, its characteristics be, it is isometric that same described crystal oscillator is connected to the length of arrangement wire of input of two described clock selection circuits.
Above-mentioned device, its characteristics are, described clock driver circuit has a plurality of outputs of corresponding a plurality of service boards, and the length of arrangement wire from described each output to backboard equates that the length of arrangement wire that is routed on the backboard from described each output to the corresponding service veneer equates.
Above-mentioned device, its characteristics are that described service board comprises phase-locked loop circuit and operating circuit, and the feedback line length of described phase-locked loop circuit equals described output clock arrives described operating circuit from described backboard length of arrangement wire.
Technique effect of the present invention is:
The invention discloses a kind of processing clock system's main and device, master/backup clock is the mode that adopts interlocking, promptly lock by the output of phase-locked loop circuit to clock selection circuit, when the selected clock of clock selection circuit changes, because the characteristic of phase-locked loop circuit makes the phase place after the clock of output changes by the phase place before changing is progressively approaching, the phase place that has realized the master/backup clock received on each veneer in the whole system remains unanimity, system is in the masterslave switchover process like this, work clock on each veneer phase hit can not occur before and after switching, thereby the system that guaranteed error rate in reversed process is lower.The present invention is particularly useful in communication apparatus or other electronic system clock system being switched phase place occasion strict or that in system's reversed process the error rate is had relatively high expectations.
Further describe specific embodiments of the invention below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is the block diagram of the present main/slave clock system of using always;
Fig. 2 is a processing clock of the present invention system main flow chart;
Fig. 3 is a schematic representation of apparatus of the present invention;
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
Fig. 2 is a processing clock of the present invention system main flow chart.At first execution in step 201 is looped back to the crystal oscillator output of main/slave clock system the input of the clock selection circuit of two clock systems by backboard, and note the wiring of backboard and clock system, make same crystal oscillator clock be looped back to via backboard two clock systems clock selection circuit input the length of arrangement wire of process identical; Execution in step 202 makes the clock selection circuit on the main/slave clock system all select the crystal oscillator clock in the active clock system to export then, and execution in step 203 locks by the output of phase-locked loop circuit to clock selection circuit, can guarantee that like this output clock of switching the phase-locked loop in the back active clock system (former standby clock system) at main/slave clock system phase hit can not take place, but a progressive phase shifts process; Execution in step 204 is driven into each veneer by clock driver circuit with the output clock of phase-locked loop point-to-pointly on main/slave clock system then, and the clock system wiring time need make each output of clock driver circuit to the backboard corresponding clock receiving node the length of arrangement wire of process isometric, the clock that need make simultaneously clock system output during backboard wiring via backboard be input to each service board on backboard the length of arrangement wire of process isometric, can guarantee to arrive the clock phase unanimity of each veneer like this; Then execution in step 205 makes clock selection circuit on each service board select the output clock of active clock system all the time, and execution in step 206 locks by the output of phase-locked loop circuit to clock selection circuit, because each veneer complex situations is different, the length of feedback line that need be by controlling each veneer phase-locked loop circuit guarantees the clock phase unanimity of the clock receiving terminal of operating circuit on each veneer, particularly, if equaling this veneer selects circuit input end from the node of backboard receive clock signal to clock length and clock selection circuit output, the negligible words of clock selection circuit internal transmission time delay, the length of the feedback line of each veneer phase-locked loop circuit export the length sum of clock receiving terminal of the operating circuit of clock to receiving phase-locked loop circuit to the length of the input of phase-locked loop circuit and phase-locked loop circuit output; If consider clock selection circuit internal transmission time delay, then need suitably to increase the length of the feedback line of phase-locked loop circuit.The operating circuit that so just can guarantee each veneer is consistent from the clock phase of the node of backboard receive clock signal with this veneer at the clock phase of clock acceptance point, has also just guaranteed the clock phase unanimity of the operating circuit of each veneer.
Fig. 3 is the schematic diagram of apparatus of the present invention.Crystal oscillator 311 output clock ClkA on the clock system 310 and the 321 output clock ClkB of the crystal oscillator on the clock system 320 all are looped back to the input of the clock selection circuit 312,322 of two clock systems by backboard 350, and when the wiring of backboard 350 and clock system, guarantee same crystal oscillator clock (ClkA or ClkB) arrive via backboard 350 two clock systems clock selection circuit 312,322 input the length of arrangement wire of process consistent, promptly use isometric clock line wiring constraint; The selection signal Clk-SelcetA and the Clk-SelectB of the clock selection circuit on while two clock systems are reciprocal, can be by active and standby selection signal controlling, this has guaranteed that the clock selection circuit 312,322 of two clock systems selects is that clock by same crystal oscillator output is the clock of the crystal oscillator output in the active clock system, and the isometric clock line wiring constraint by application of aforementioned can guarantee that the phase place of the clock of two phase-locked loop circuits 313,323 locking outputs on the clock system is consistent.Two clock systems arrive each service board 330,340 by clock driver circuit 314,324 output clocks, and when clock system connects up, need make each output of clock driver circuit to the backboard corresponding clock receiving node the length of arrangement wire of process isometric, the clock that need make clock system output during backboard 350 wirings simultaneously via backboard be input to each service board on backboard the length of arrangement wire of process isometric, can guarantee that like this clock of same clock system output arrives the clock phase unanimity of each veneer.Clock selection circuit on each service board is selected the output clock of active clock system all the time, and by phase-locked loop circuit 333, the output of 343 pairs of clock selection circuits locks, because each veneer complex situations is different, the length of feedback line that need be by controlling each veneer phase-locked loop circuit guarantees the clock phase unanimity of the clock receiving terminal of operating circuit on each veneer, particularly, if clock selection circuit 332, the negligible words of 342 internal transmission time delays, each veneer phase-locked loop circuit 333, the length of 343 feedback line equals this veneer and selects the length of circuit input end and clock selection circuit output to export the operating circuit 331 of clock to the length and the phase-locked loop circuit output of the input of phase-locked loop circuit to receiving phase-locked loop circuit from the node of backboard receive clock signal to clock, the length sum of 341 clock receiving terminal; If consider clock selection circuit internal transmission time delay, then need suitably to increase the length of the feedback line of phase-locked loop circuit.The operating circuit that so just can guarantee each veneer is consistent from the clock phase of the node of backboard receive clock signal with this veneer at the clock phase of clock acceptance point, has also just guaranteed the clock phase unanimity of the operating circuit of each veneer.Because the clock of the locking of the phase-locked loop circuit on main/slave clock system output can guarantee that phase place is consistent, thereby can guarantee that the phase place of the main/stand-by clock on each service board before system switches is consistent.After system began to carry out masterslave switchover, clock system was switched, and has promptly switched in the crystal oscillator source, and the clock that each service board of while receives switches.After the standby clock system becomes the active clock system, saltus step can not take place than the phase place of the output clock of the phase-locked loop circuit of preceding active clock system (existing standby clock system) in the phase place of the output clock of its phase-locked loop circuit, and can lock new crystal oscillator input clock again gradually, then the phase-locked loop output clock on each service board also settles out, and clock active/standby is switched and finished.Like this in whole clock switch process, because it is more approaching that the phase place in the clock source of the active and standby input of each service board keeps, not having uncontrollable clock phase error exists, the problem of catching up with after catching up with before phase-locked loop can not occur, thereby the work clock (being phase-locked loop output clock) that guarantees each service board keeps phase error less, thereby suppressed the error rate, guaranteed the success of switching.
Claims (9)
1. a processing clock system main is used to finish switching of active and standby clock system, it is characterized in that, comprises the steps:
Step 1, the crystal oscillator clock that makes active and standby clock system all arrive the input of the clock selection circuit of two clock systems by backboard;
Step 2, the clock selection circuit of active and standby clock system all select crystal oscillator clock in the active clock system as output;
Step 3 locks by the output of the phase-locked loop circuit on the active and standby clock system to the clock selection circuit on this clock system, obtains the output clock of active and standby clock system;
Step 4 is driven into each service board by the clock driver circuit on the active and standby clock system with described output clock point-to-pointly.
2. method according to claim 1 is characterized in that, also includes:
Step 5 makes the clock selection circuit on each service board select the output clock of active clock system as output all the time;
Step 6, the phase-locked loop circuit on each service board lock and flow to the operating circuit of this service board to the output of the clock selection circuit on this veneer.
3. method according to claim 1 is characterized in that, in described step 1, also comprise the clock selection circuit input that makes described two clock systems the step that is consistent of the phase place that receives respectively from the crystal oscillator clock of same clock system.
4. method according to claim 1 is characterized in that, in described step 4, also comprises the step that the phase place from the described output clock of same clock system that makes that described each service board receives is consistent.
5. method according to claim 2 is characterized in that, in described step 6, also comprises the step of the feedback line length that the phase-locked loop circuit on described each service board is set.
6. the device of a processing clock system masterslave switchover comprises active and standby clock system, and backboard and service board is characterized in that, described active and standby clock system all includes crystal oscillator, clock selection circuit, phase-locked loop circuit and clock driver circuit;
Described crystal oscillator produces a crystal oscillator clock and sends described clock selection circuit to;
Described clock selection circuit is used to select the crystal oscillator clock of active clock system and exports to described phase-locked loop circuit;
Described phase-locked loop circuit is used to lock the output of described clock selection circuit, produces the output clock of this clock system;
Described clock driver circuit is used for described output clock is sent to described service board through described backboard is point-to-point;
Described crystal oscillator all connects the input of the clock selection circuit of described active and standby clock system by described backboard, described clock selection circuit connects described clock driver circuit through described phase-locked loop circuit, described clock driver circuit connects described service board through described backboard, described clock selection circuit is selected the crystal oscillator clock of active clock system and through the described output clock of described phase-locked loop circuit locking back generation, and described clock driver circuit sends to described service board with described output clock through described backboard is point-to-point.
7. device according to claim 6 is characterized in that, it is isometric that same described crystal oscillator is connected to the length of arrangement wire of input of two described clock selection circuits.
8. device according to claim 6, it is characterized in that, described clock driver circuit has a plurality of outputs of corresponding a plurality of service boards, length of arrangement wire from described each output to backboard equates that the length of arrangement wire that is routed on the backboard from described each output to the corresponding service veneer equates.
9. device according to claim 6 is characterized in that described service board comprises phase-locked loop circuit and operating circuit, and the feedback line length of described phase-locked loop circuit equals described output clock arrives described operating circuit from described backboard length of arrangement wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410046457 CN1655455B (en) | 2004-02-10 | 2004-06-09 | Method and apparatus for handling reversion of primary and secondary clock systems |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200410039414 | 2004-02-10 | ||
| CN200410039414.1 | 2004-02-10 | ||
| CN 200410046457 CN1655455B (en) | 2004-02-10 | 2004-06-09 | Method and apparatus for handling reversion of primary and secondary clock systems |
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| CN1655455A CN1655455A (en) | 2005-08-17 |
| CN1655455B true CN1655455B (en) | 2010-04-28 |
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| CN 200410046457 Expired - Fee Related CN1655455B (en) | 2004-02-10 | 2004-06-09 | Method and apparatus for handling reversion of primary and secondary clock systems |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364861B (en) | 2007-08-08 | 2012-11-07 | 华为技术有限公司 | MicroTCA system, time clock card and method for providing time clock |
| CN101197650B (en) * | 2007-11-21 | 2012-11-07 | 上海华为技术有限公司 | Clock synchronization device and method |
| CN101299647B (en) * | 2008-06-27 | 2011-05-11 | 中兴通讯股份有限公司 | Apparatus and method for implementing nondestructive switch of SDH service |
| CN101958762B (en) * | 2009-07-14 | 2014-08-13 | 中兴通讯股份有限公司 | Main and standby clock switching device and method |
| CN102957552B (en) * | 2011-08-23 | 2017-03-15 | 中兴通讯股份有限公司 | clock protection method and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383287A (en) * | 2001-04-26 | 2002-12-04 | 深圳市中兴通讯股份有限公司 | Automatic-protecting switching device for multi-point clock synchronizing system |
| CN1472912A (en) * | 2002-07-30 | 2004-02-04 | 华为技术有限公司 | Method for interlocking control of master backup timer |
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2004
- 2004-06-09 CN CN 200410046457 patent/CN1655455B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383287A (en) * | 2001-04-26 | 2002-12-04 | 深圳市中兴通讯股份有限公司 | Automatic-protecting switching device for multi-point clock synchronizing system |
| CN1472912A (en) * | 2002-07-30 | 2004-02-04 | 华为技术有限公司 | Method for interlocking control of master backup timer |
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