CN101667906A - Method and system for switching main and backup clocks - Google Patents
Method and system for switching main and backup clocks Download PDFInfo
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- CN101667906A CN101667906A CN200810146642A CN200810146642A CN101667906A CN 101667906 A CN101667906 A CN 101667906A CN 200810146642 A CN200810146642 A CN 200810146642A CN 200810146642 A CN200810146642 A CN 200810146642A CN 101667906 A CN101667906 A CN 101667906A
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Abstract
The invention discloses a method for switching main and backup clocks, which is applied to a system comprising a main clock board and a backup clock board. Clock generation chips of the main clock board and the backup clock board respectively track a common-frequency clock source of the respective clock board; the mutual transmission of the main and backup clocks and data is achieved through respective logic chips; when the main and backup clocks are to be switched, a pre-switching instruction is sent to the logic chip of the main clock board, and after receiving the instruction, the logic chip of the main clock board sends a synchronous instruction to the logic chip of the backup clock board; after receiving the synchronous instruction, the logic chip of the backup clock board sends an effective synchronous signal in a pulse form to the clock generation chip of the backup clock board; and the clock generation chip of the backup clock board stops the clock output when the synchronous signal is effective, and restores the clock output after first delay time when the synchronous signal is not effective, phase positions of the main and backup clocks are aligned, and the main and backup clocks are instructed to execute main and backup switching. The method cannot cause phase position transient variation, unstable system and poor reliability due to the switching, and simultaneouslyhas less occupied resources.
Description
Technical field
The present invention relates to the switching of master/backup clock, more specifically, relate to the method and system that a kind of master/backup clock switches.
Background technology
Clock is the key signal of communication equipment, and every performance of clock can influence the performance of veneer and even whole system.So guarantee that the accuracy of the every performance of communication equipment clock and stability are very important for communication equipment.So each correspondence entity, country and operator all will carry out strict test to the every performance of the clock of equipment before equipment networks.The performance index of clock mainly comprise frequency and phase place, and the performance of investigating These parameters usually comprises long-term stability, long-term accuracy, keeps performance, phase transient and phase discontinuity etc.
The general reliability that main veneer is backed up raising equipment that adopts of communication equipment, clock is a very important part for communication equipment, therefore in the design of communication equipment clock, adopted the back-up job mode, in case master clock breaks down, being equipped with the alternative immediately master clock of clock provides timing signal for communication equipment.The switching of active and standby clock will guarantee business is not exerted an influence as far as possible, produce professional hit, error code etc. when for example switching, therefore under any circumstance, must guarantee when master/backup clock switches, the frequency and the phase place of master/backup clock are alignd, otherwise equipment will produce error code even service disconnection.
At existing clock backup scheme main phase-locked loop and the secondary phase-locked loops of adopting, promptly active clock adopts digital phase-locked loop track reference source more, is equipped with clock and adopts analog phase-locked look to follow the tracks of active clock, makes standby output clock and active clock phase alignment.It mainly is in order to guarantee that system clock satisfies the communication equipment relevant criterion, can to make clock work in various mode of operations, as states such as locking, tracking, maintenance and free oscillations that active clock adopts digital phase-locked loop.And the consideration that standby clock adopts analog loop mainly to differ for master/backup clock.The analog phase-locked look residue differs comparatively constant, and high conformity is being equipped with clock or master clock adjusting time-delay, can reach active and standby clock output alignment.
In this clock scheme, it is a major-minor phase-locked loop operation handoff procedure that clock active/standby switches.Suppose that A is arranged, two clock boards of B, the A plate is defaulted as main board, the B plate is a standby plate.This moment, the main phase-locked loop operation of A plate was a digital phase-locked loop, the locking reference source, and secondary phase-locked loop is an analog phase-locked look, does not work, and is network element output timing signal simultaneously; The main phase-locked loop of B plate is not worked, and secondary phase-locked loop is followed the tracks of and the timing signal of locking A plate output, and the B plate is not exported timing signal.If take place artificial force to switch to B master with or the A plate break down, the timing signal of network element switches to the output of B plate, A, B plate major-minor phase-locked loop operation are switched simultaneously, and the B plate is followed the tracks of A plate output timing signal by secondary phase-locked loop and switched to main phase-locked loop track reference source signal; On the contrary, the A plate switches to the timing signal that secondary phase-locked loop is followed the tracks of the output of B plate by main phase-locked loop, and this moment, the A plate was not exported timing signal.
Switch in the digital phase-locked loop process in analog phase-locked look like this and be easy to generate phase transient, promptly the clock phase discontinuity causes clock phenomenons such as error code to occur because of active and standby switching.This method also has following defective: the standby plate clock is wanted the frequency and the phase place of real-time tracking main board clock, has taken a large amount of resources.
In the prior art, realize the system of main clock phase alignment, as shown in Figure 8, mainly comprise the clock generating module, drive distribution module and with reference to a series of chips such as logic selections.The problem of its existence is, line complexity between the active and standby plate needs 7 pairs of lines.The device that participates in active and standby switching is too many, has brought hidden danger to reliability.
Summary of the invention
Technical problem to be solved by this invention provides the method that a kind of master/backup clock switches, can be because of switching does not cause phase transient, system's instability and poor reliability, and it is few to take resource simultaneously.
In order to solve the problems of the technologies described above, the invention provides the method that a kind of master/backup clock switches, the system that is applied to comprise the master clock plate and is equipped with clock board, this master clock plate is distributed the same frequency clock source that chip is followed the tracks of this clock board respectively with the clock that is equipped with clock board, and the logic chip by separately realizes the mutual biography of master/backup clock and data, and this method comprises:
When switching master/backup clock, to the logic chip transmission pre-switch instruction of master clock plate, the logic chip of master clock plate sends synchronic command to the logic chip that is equipped with clock board after receiving the pre-switch instruction;
After the logic chip of clock board is received this synchronic command fully, send the efficient synchronization signal of an impulse form to the clock distribution chip that is equipped with clock board;
The clock distribution chip that is equipped with clock board stops clock output when synchronizing signal is effective, after synchronizing signal is invalid, through recovered clock output behind one first delay time, main clock phase is alignd;
After the main clock phase alignment, indicate the master clock plate and be equipped with clock board and carry out active and standby switching.
Further, said method also can have following characteristics:
Described first delay time equals t
1With Δ t sum, wherein t
1Distribute chip from the invalid inherent delay to recovered clock output of synchronizing signal for clock, Δ t is to be the time-delay of clock distribution chip configuration, and Δ t determines by following formula:
t
1+t
2+t
3+Δt＝n*t
s
Wherein:
N is an integer; t
sBe the active and standby clock cycle; t
2The clock that is the master clock plate arrives the time-delay of the logic chip that is equipped with clock board through the logic chip of master clock plate after the clock distribution chip output of master clock plate; t
3Be to be equipped with this clock to receive synchronic command, to the time-delay of output synchronizing signal.
Further, said method also can have following characteristics:
After the main clock phase alignment, wait for one second delay time again after, indicate the master clock plate again and be equipped with clock board and carry out active and standby switching, this second delay time should be realized required time of Phase synchronization greater than other signal that transmits on the active and standby clock board.
Further, said method also can have following characteristics:
Described pre-switch instruction is that the CPU on the master clock plate sends, after the main clock phase alignment, and indication master clock plate and be equipped with clock board and carry out the process of active and standby switching and comprise:
CPU on the master clock plate sends switching command to the logic chip of master clock plate, and the logic chip of master clock plate carries out active and standby switching after receiving this switching command, and sends switching command to the logic chip that is equipped with clock board; After the logic chip of clock board is received this switching command fully, carry out active and standby switching.
Further, said method also can have following characteristics:
After also encoding to the instruction that will send, the logic chip of described master clock plate sends the data of coding back instruction again, be equipped with the data of the logic chip of clock board, recover the instruction that the master clock plate sends after the parsing with the clock sampling master clock plate transmission of master clock plate transmission.
The beneficial effect of this method is, has realized the master/backup clock switching, makes that reliability can be guaranteed when the master/backup clock unit switched because of work; Because standby plate clock of the present invention has reduced taking of resource without the frequency and the phase place of real-time tracking main board clock.
Another technical problem to be solved by this invention provides the system that a kind of master/backup clock switches, phase place and system stability during switching, and line is simple between active and standby plate, and the device that is used to switch is few.
In order to solve the problems of the technologies described above, the invention provides the system that a kind of master/backup clock switches, comprise two active and standby each other clock boards, every clock board includes clock distribution chip, logic chip and same clock source frequently, wherein:
Described with frequency clock source, be used for reference source as clock distribution chip clocking;
Described clock distribution chip, be used for following the tracks of respectively the same frequency clock source of this clock board, logic chip to this clock board provides clock, the synchronizing signal of sending at the logic chip of this clock board stops clock output when effective, after clock signal is invalid, postpone to recover the output clock again behind one first delay time;
Described logic chip further comprises:
Send part, be used for sending the data that generate behind the clock of this clock board and the command coding, wherein receiving that pre-switch instruction back sends synchronic command to the opposite end clock board this clock board to the opposite end clock board;
Receiving unit, be used to receive the clock and the data of opposite end clock board, the data-signal of receiving with the clock sampling of receiving, recover the instruction that the opposite end clock board is sent after the parsing, receive the efficient synchronization signal that sends an impulse form behind the synchronic command that the opposite end clock board sends to the clock distribution chip of this clock board.
Further, said system also can have following characteristics:
Described first delay time equals t
1With Δ t sum, wherein t
1Distribute chip from the invalid inherent delay to recovered clock output of synchronizing signal for clock, Δ t is to be the time-delay of clock distribution chip configuration, and Δ t determines by following formula:
t
1+t
2+t
3+Δt＝n*t
s
Wherein:
N is an integer; t
sBe the active and standby clock cycle; t
2The clock that is the master clock plate arrives the time-delay of the logic chip that is equipped with clock board through the logic chip of master clock plate after the clock distribution chip output of master clock plate; t
3Be to be equipped with this clock to receive synchronic command, to the time-delay of output synchronizing signal.
Further, said system also can have following characteristics:
Also comprise CPU on the described every clock board, this CPU is after the logic chip of this clock board sends described pre-switch instruction, wait for behind one second delay time that the logic chip to this clock board sends switching command again, this second delay time should be realized required time of Phase synchronization greater than other signal that transmits on the active and standby clock board.
Further, said system also can have following characteristics:
The transmission part of described logic chip also after receiving switching command, is carried out active and standby switching and the switching command after the opposite end clock board sends coding;
The receiving unit of described logic chip is also carried out active and standby switching after receiving the switching command that the opposite end clock board is sent.
Further, said system also can have following characteristics:
Adopt two pairs to pass lines mutually and connect between the logic chip of described standby each other two clock boards, a clock board uses a pair of line, and every pair of line comprises a holding wire and a holding wire that is used to transmit this clock board data that is used to transmit this clock board clock.
The beneficial effect of native system is, and is simple in structure, realized the main clock phase alignment, makes phase place and system stability when clock unit switches because of work, good reliability; Simultaneously, when being suitable for system of the present invention realization master/backup clock switching, the standby plate clock has reduced taking of resource without the frequency and the phase place of real-time tracking main board clock.
Description of drawings
Fig. 1 is the structural representation of embodiment of the invention system.
Fig. 2 is the schematic diagram that passes clock and data among Fig. 1 between the active and standby plate mutually.
Fig. 3 be among Fig. 1 active and standby clock board to the schematic diagram in the path of opposite end clock board transmission clock.
Fig. 4 is the flow chart of embodiment of the invention method.
Fig. 5 show clock distribution chip synchronously with the time diagram of output clock.
Fig. 6 shows t
3The device schematic diagram that time-delay is corresponding.
Fig. 7 shows t
3The sequential schematic diagram that time-delay is corresponding.
Fig. 8 shows the system that realizes the main clock phase alignment in the prior art.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.
As shown in Figure 1, present embodiment realizes that the system that master/backup clock switches includes the master clock plate and is equipped with clock board, the master clock plate and be equipped with CPU is all arranged on the clock board, with clock source, clock distribution chip and logic chip frequently.The logic chip of present embodiment is realized with field programmable gate array module (Field Programmable GateArray is called for short FPGA), is realized with high stability crystal oscillator with frequency clock source.Master clock plate and the clock that is equipped with clock board are followed the tracks of the same frequency high stability crystal oscillator of this clock board respectively, make master/backup clock output frequency basically identical.Master clock plate and be equipped with adopts two pairs to pass lines mutually and connect between the logic chip of clock board, a pair of line is used in the transmitting-receiving of clock board, and the every pair of line comprises the holding wire that a holding wire that is used to transmit this clock board clock and are used to transmit this clock board and the data of clock synchronization.The sequential schematic diagram of active and standby mutual biography data and clock as shown in Figure 2.Active and standby clock board is: this plate clock chip → this plate logic chip → to the plate logic chip to the path of opposite end transmission clock as shown in Figure 3.
Comprise on each clock board:
CPU, be used for when needs switch, logic chip to this clock board sends pre-switch instruction and switching command, wherein after sending the pre-switch instruction, send switching command again after waiting for one second delay time, this second delay time should be realized the required time of Phase synchronization greater than other signal that transmits on the active and standby clock board.
Logic chip comprises:
Send part, be used for to the opposite end clock board send the clock of this clock board and to the state information of this clock board and command coding after the data that generate, wherein, after receiving switching command, carry out active and standby switching and the switching command after the opposite end clock board sends coding receiving the synchronic command of pre-switch instruction back after the opposite end clock board sends coding; And
Receiving unit, be used to receive clock and the data that the opposite end clock board is sent, the data-signal of receiving with the clock sampling of receiving is also resolved, recover state information and instruction that the opposite end clock board is sent, after receiving the synchronic command that the opposite end clock board is sent, send the efficient synchronization signal sync of an impulse form, after receiving the switching command that the opposite end clock board is sent, carry out active and standby switching to clock distribution chip.
Clock distribution chip, be used for following the tracks of respectively the same frequency clock source of this clock board, the clock of this clock board is provided to logic chip and system, receiving that synchronizing signal that logic chip is sent stops clock output when effective, after clock signal is invalid, postpone to recover the output clock again behind one first delay time.The calculating of this delay time sees the explanation in the flow process for details.
With frequency clock source, be used for reference source as clock distribution chip clocking.
The present embodiment system is when operate as normal, and the same frequency clock source of each this clock board of self-locking of the clock chip of active and standby clock board does not need master clock and be equipped with the same reference source signal of clock tracing to satisfy with requirement frequently.Master/backup clock utilizes the synchronizing function of system earlier when switching, make master/backup clock Phase synchronization before switching, and then switch.
Concrete switching flow may further comprise the steps as shown in Figure 4:
The possibility that the master clock plate initiates to switch has a lot, and it is unusual that for example CPU detects mainboard output clock, and CPU will initiate switching command to mainboard.
After step 120, the logic chip of master clock plate are received the pre-switch instruction, the data of the synchronic command after the logic chip that is equipped with clock board sends coding;
Step 140 after the clock of clock board distribution chip is received synchronizing signal fully, stops clock output, after synchronizing signal is invalid, through recovered clock output behind one first delay time, realizes the alignment of main clock phase again;
As long as satisfy following formula (1), just main clock phase can be alignd:
t
1+ t
2+ t
3+ Δ t=n*t
sFormula (1)
Wherein:
N is an integer;
t
sBe the active and standby clock cycle;
t
1For clock is distributed chip from the invalid time-delay to recovered clock output of synchronizing signal, this basic fixed of delaying time.As shown in Figure 5, the voltage controlled oscillator that uppermost one road high frequency clock is a clock chip (VoltageControlled Oscillator is called for short VCO) clock, the second road clock is the clock behind the VCO frequency division, the second road clock is synchronizing signal sync down.The synchronizing signal low level is effective, and when synchronizing signal was low level, the output of clock chip was turned off.Synchronizing signal becomes high level and promptly becomes when invalid, and clock distribution chip is not will export clock, and will wait one period regular time, is that chip is intrinsic during this period of time, counts t at once
1, be to equal 14 to 15 cycles behind the VCO frequency division to add 1 VCO output cycle among the figure.
t
2Be the time-delay of PCB cabling between the active and standby plate, promptly the clock of master clock plate through the logic chip arrival time-delay of the logic chip of clock board fully of this clock board, is counted t after the clock distribution chip output of master clock plate
2
t
3Be the time-delay of logic chip, after promptly the logic chip of clock board receives synchronic command fully, resolve,, count t to time-delay to the clock distribution chip output synchronizing signal that is equipped with clock board
3, this section time-delay is the constant time lag of logic chip inside, is a schematic diagram of hardware among Fig. 6, as a d type flip flop, this d type flip flop is input as the clock and the data of master clock plate, is output as synchronizing signal logic chip.Fig. 7 shows the working timing figure of d type flip flop, and data only change state at the rising edge of clock, and desirable state is that two dotted lines of A, B overlap, but reality just has one section time-delay t
3
Δ t sets up and one section delay time of selection formula (1), can be disposed in the process of software initialization clock distribution chip.
Like this, first delay time of mentioning in the above-mentioned steps 140 promptly equals the intrinsic time-delay t of above-mentioned logic chip
1With the time-delay Δ t that is provided with, formula has been considered main time-delay in (1), can reach the requirement of precision.
After mainboard and the slave board Phase synchronization, promptly can carry out active and standby switching, but can cause that the clock of slave board turn-offs output because slave board is initiated synchronic command, clock board transmits the waveform of some frequency possibly, so also will guarantee the Phase synchronization of these signals.For example also will transmit the 10ms ripple between the master/backup clock plate, and the PP2S signal is that pulsewidth is the square wave of 16 19.6608MHZ.Slave board is initiated synchronic command can cause that the clock chip clock of slave board turn-offs output, therefore could switch after after synchronic command finishes, must waiting the synchronous mainboard PP2S of slave board PP2S, can with the 10ms frame head of slave board and frame number and mainboard synchronously, so just can make the PP2S of slave board be synchronized with the PP2S of mainboard.Finish to the minimum 20ms that wants of time that switches initiation from synchronic command, that is to say that the time of a clock switching cost must be greater than 20ms.Be that above-mentioned second delay time is greater than 20ms.This second delay time is optional.And delay time is relevant with the signal that needs to transmit, and might not be 20ms.
After step 160, the logic chip that is equipped with clock board are received and parsed switching command, carry out active and standby switching.
The master clock plate is no longer exported the required timing signal of network element after switching to and being equipped with clock board, and after clock board switches to the master clock plate fully, will the required timing signal of output network element.
According to the present invention, by the clock distribution chip that has synchronizing function main clock phase is alignd, the precision of master and spare clock plate phase position alignment can be controlled at the 1ns magnitude.Novel part of the present invention do not need to be the standby clock phase place is adjusted in real time, only needs to adjust before active and standby switching once to get final product.And the high steady clock crystal of the same frequency on main board and each this plate of self-locking of standby plate, active and standby plate frequency is basic identical.The present invention has abandoned traditional clock active/standby changing method, and switching to clock active/standby provides new thinking.
The present invention does not need master/backup clock is differed judgement, is equipped with the adjustment of clock output phase and makes the main clock phase alignment according to master/backup clock phase difference, therefore the frequency that does not need slave board clock real-time tracking main board clock does not need that very long clock cabling is arranged between slave board and the mainboard.
Claims (10)
1, a kind of method of master/backup clock switching, the system that is applied to comprise the master clock plate and is equipped with clock board, this master clock plate is distributed the same frequency clock source that chip is followed the tracks of this clock board respectively with the clock that is equipped with clock board, and the logic chip by separately realizes the mutual biography of master/backup clock and data, and this method comprises:
When switching master/backup clock, to the logic chip transmission pre-switch instruction of master clock plate, the logic chip of master clock plate sends synchronic command to the logic chip that is equipped with clock board after receiving the pre-switch instruction;
After the logic chip of clock board is received this synchronic command fully, send the efficient synchronization signal of an impulse form to the clock distribution chip that is equipped with clock board;
The clock distribution chip that is equipped with clock board stops clock output when synchronizing signal is effective, after synchronizing signal is invalid, through recovered clock output behind one first delay time, main clock phase is alignd;
After the main clock phase alignment, indicate the master clock plate and be equipped with clock board and carry out active and standby switching.
2, the method for claim 1 is characterized in that:
Described first delay time equals t
1With Δ t sum, wherein t
1Distribute chip from the invalid inherent delay to recovered clock output of synchronizing signal for clock, Δ t is to be the time-delay of clock distribution chip configuration, and Δ t determines by following formula:
t
1+t
2+t
3+Δt＝n*t
s
Wherein:
N is an integer; t
sBe the active and standby clock cycle; t
2The clock that is the master clock plate arrives the time-delay of the logic chip that is equipped with clock board through the logic chip of master clock plate after the clock distribution chip output of master clock plate; t
3Be to be equipped with this clock to receive synchronic command, to the time-delay of output synchronizing signal.
3, the method for claim 1 is characterized in that:
After the main clock phase alignment, wait for one second delay time again after, indicate the master clock plate again and be equipped with clock board and carry out active and standby switching, this second delay time should be realized required time of Phase synchronization greater than other signal that transmits on the active and standby clock board.
4, the method for claim 1 is characterized in that:
Described pre-switch instruction is that the CPU on the master clock plate sends, after the main clock phase alignment, and indication master clock plate and be equipped with clock board and carry out the process of active and standby switching and comprise:
CPU on the master clock plate sends switching command to the logic chip of master clock plate, and the logic chip of master clock plate carries out active and standby switching after receiving this switching command, and sends switching command to the logic chip that is equipped with clock board; After the logic chip of clock board is received this switching command fully, carry out active and standby switching.
5, the method for claim 1 is characterized in that:
After also encoding to the instruction that will send, the logic chip of described master clock plate sends the data of coding back instruction again, be equipped with the data of the logic chip of clock board, recover the instruction that the master clock plate sends after the parsing with the clock sampling master clock plate transmission of master clock plate transmission.
6, a kind of system of master/backup clock switching comprises two active and standby each other clock boards, and every clock board includes clock distribution chip and logic chip, it is characterized in that: also comprise on the every clock board with frequency clock source, wherein:
Described with frequency clock source, be used for reference source as clock distribution chip clocking;
Described clock distribution chip, be used for following the tracks of respectively the same frequency clock source of this clock board, logic chip to this clock board provides clock, the synchronizing signal of sending at the logic chip of this clock board stops clock output when effective, after clock signal is invalid, postpone to recover the output clock again behind one first delay time;
Described logic chip further comprises:
Send part, be used for sending the data that generate behind the clock of this clock board and the command coding, wherein receiving that pre-switch instruction back sends synchronic command to the opposite end clock board this clock board to the opposite end clock board;
Receiving unit, be used to receive the clock and the data of opposite end clock board, the data-signal of receiving with the clock sampling of receiving, recover the instruction that the opposite end clock board is sent after the parsing, receive the efficient synchronization signal that sends an impulse form behind the synchronic command that the opposite end clock board sends to the clock distribution chip of this clock board.
7, system as claimed in claim 6 is characterized in that:
Described first delay time equals t
1With Δ t sum, wherein t
1Distribute chip from the invalid inherent delay to recovered clock output of synchronizing signal for clock, Δ t is to be the time-delay of clock distribution chip configuration, and Δ t determines by following formula:
t
1+t
2+t
3+Δt＝n*t
s
Wherein:
N is an integer; t
sBe the active and standby clock cycle; t
2The clock that is the master clock plate arrives the time-delay of the logic chip that is equipped with clock board through the logic chip of master clock plate after the clock distribution chip output of master clock plate; t
3Be to be equipped with this clock to receive synchronic command, to the time-delay of output synchronizing signal.
8, as claim 6 or 7 described systems, it is characterized in that:
Also comprise CPU on the described every clock board, this CPU is after the logic chip of this clock board sends described pre-switch instruction, wait for behind one second delay time that the logic chip to this clock board sends switching command again, this second delay time should be realized required time of Phase synchronization greater than other signal that transmits on the active and standby clock board.
9, system as claimed in claim 8 is characterized in that:
The transmission part of described logic chip also after receiving switching command, is carried out active and standby switching and the switching command after the opposite end clock board sends coding;
The receiving unit of described logic chip is also carried out active and standby switching after receiving the switching command that the opposite end clock board is sent.
10, as claim 6 or 7 described systems, it is characterized in that:
Adopt two pairs to pass lines mutually and connect between the logic chip of described standby each other two clock boards, a clock board uses a pair of line, and every pair of line comprises a holding wire and a holding wire that is used to transmit this clock board data that is used to transmit this clock board clock.
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|---|---|---|---|
| CN2008101466427A CN101667906B (en) | 2008-09-03 | 2008-09-03 | Method and system for switching main and backup clocks |
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| CN109308230A (en) * | 2017-07-27 | 2019-02-05 | 华为技术有限公司 | A kind of backup method and device |
| CN109428661A (en) * | 2017-08-21 | 2019-03-05 | 中兴通讯股份有限公司 | A kind of main clock phase alignment device and method based on FPGA |
| CN110554731A (en) * | 2019-08-12 | 2019-12-10 | 深圳震有科技股份有限公司 | Clock synchronization control method, intelligent terminal and storage medium |
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