CN101895425B - Master and slave seamless switching device and method - Google Patents
Master and slave seamless switching device and method Download PDFInfo
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- CN101895425B CN101895425B CN201010230638.6A CN201010230638A CN101895425B CN 101895425 B CN101895425 B CN 101895425B CN 201010230638 A CN201010230638 A CN 201010230638A CN 101895425 B CN101895425 B CN 101895425B
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Abstract
The invention discloses a master and slave seamless switching device and a master and slave seamless switching method. The device comprises a master board clock switching control unit, a master board clock phase-locked loop, a slave board clock switching control unit and a slave board clock phase-locked loop, wherein the master board clock switching control unit controls the master board clock phase-locked loop to send clock phase information the first time, and sends a master and slave switching command the subsequent second time; the master board clock phase-locked loop provides clock phase information and stops working after receiving the master and slave switching command; the slave board clock switching control unit forwards the received clock phase information to the slave board clock phase-locked loop and controls the slave board clock phase-locked loop to perform master and slave switching after receiving the master and slave switching command; and the slave board clock phase-locked loop performs phase lock operation according to the clock phase information and outputs a same-phase clock signal according to the master and slave switching command. By utilizing a method for sending clock and control information in a time sharing way through a single signal wire in a master and slave design, the master and slave seamless switching is successfully realized on the master and salve interconnection signal wire.
Description
Technical field
The present invention relates to a kind of active and standby handoff technique, particularly a kind of active and standby seamless switching device and method in a kind of mobile communication.
Background technology
In cordless communication network, the clock of system is had to very high requirement, therefore in the design of communication equipment, adopt the working method of " 1+1 " backup, host apparatus provides synchronised clock for system under normal circumstances, when host apparatus breaks down or artificially initiates to switch, stand-by equipment can be taken over immediately whole system and provide clock signal for system.For realize active and standby seamless switching be in masterslave switchover process on not impact of business, must guarantee that the clock of main board and standby plate keeps phase place consistent with frequency, otherwise can cause the problems such as base station call drop in masterslave switchover moment.
In existing clock active/standby homophase scheme, main board and standby plate all adopt a pair of holding wire to carry out active and standby information interaction, as shown in Figure 1, the clock phase information that wherein clock cable transmits main board is for master/backup clock homophase, data signal line transmits switching controls instruction and the active and standby information of main board, this scheme can meet the requirement of the active and standby seamless switching of radio communication base station well, but clock phase information and switching controls instruction need by clock cable and data signal line, to transmit respectively, so communicating by letter of main board and standby plate needs a pair of holding wire, be difficult to meet the requirement of low-cost compact device.
Summary of the invention
The object of the present invention is to provide a kind of active and standby seamless switching device, for solving, on an active and standby interconnected holding wire, complete the mutual of clock phase information and the instruction of master/backup clock switching controls.
Another object of the present invention is to provide a kind of active and standby seamless handover method, for solving, on an active and standby interconnected holding wire, complete the mutual of clock phase information and switching controls instruction.
According to an aspect of the present invention, provide a kind of active and standby seamless switching device, having comprised:
Main board clock switch control unit, for control main board clock phase-locked loop hoop standby plate clock switch control unit tranmitting data register phase information in the very first time, and to main board clock phase-locked loop and standby plate clock switch control unit, send active and standby switching command in the second time subsequently;
Main board clock phase-locked loop for clock phase information is provided, and quits work when receiving active and standby switching command;
Standby plate clock switch control unit, is transmitted to standby plate clock phase-locked loop by the clock phase information of receiving, and when receiving active and standby switching command, controls standby plate clock phase-locked loop and carry out standby usage switching;
Standby plate clock phase-locked loop, carries out phase-locked operation according to clock phase information, and exports the clock signal of homophase according to active and standby switching command.
When receiving master/backup clock switching command, main board clock switch control unit sends active and standby same phase command to main board timer and standby plate clock switch control unit.
Main board timer starts the timing of the very first time and the second time when receiving described active and standby same phase command.
Standby plate timer starts timing when standby plate clock switch control unit receives the active and standby same phase command of main board clock switch control unit transmission.
Standby plate clock switch control unit starts standby plate clock phase-locked loop and carries out phase-locked operation when the timing of standby plate timer is overtime.
According to a further aspect in the invention, provide a kind of active and standby seamless handover method, comprised the following steps:
A, at very first time main board clock switch control unit, control main board clock phase-locked loop clock phase information is provided, and to standby plate clock switch control unit, send described clock phase information by main board clock switch control unit;
B, standby plate clock switch control unit forward it to standby plate clock phase-locked loop after receiving described clock phase information, and control standby plate clock phase-locked loop and carry out phase-locked operation;
C, at the second time main board clock switch control unit, to main board clock phase-locked loop and standby plate clock switch control unit, send active and standby switching command;
D, main board clock phase-locked loop quit work when receiving described active and standby switching command, standby plate clock switch control unit is when receiving described active and standby switching command, control standby plate clock phase-locked loop and carry out standby usage switching, standby plate clock phase-locked loop is exported the clock signal of homophase according to described active and standby switching command.
Wherein, before steps A, when main board clock switch control unit receives master/backup clock switching command, to main board timer and standby plate clock switch control unit, send active and standby same phase command, main board clock switch control unit starts main board timer.
The very first time is that the active and standby same phase command of main board clock control cell transmission receives the time of this order to standby plate;
The second time was that the active and standby same phase command of main board clock control cell transmission completes the time of master/backup clock homophase to standby plate;
Wherein, the very first time and the second time are the time period, and the second time was greater than the very first time.
When standby plate clock switch control unit receives the active and standby same phase command that main board clock switch control unit sends, standby plate timer starts timing, and when timer timing is overtime, starts standby plate clock phase-locked loop and carry out phase-locked operation.
Standby plate timer timing is the time period, and this time period is less than the difference of the second time and the very first time.
The present invention has following technique effect: the present invention utilizes single holding wire successfully to realize clock phase information and the instruction of master/backup clock switching controls of timesharing transmission main board in active and standby design, thereby effectively reduced the interconnected holding wire between main board and standby plate, not only meet the requirement of master/backup clock homophase, and met the demand of low-cost micro base station.
Accompanying drawing explanation
Fig. 1 is the clock active/standby homophase scheme schematic diagram that prior art provides;
Fig. 2 is the structure chart of clock active/standby seamless switching device provided by the invention;
Fig. 3 is the flow chart of clock active/standby seamless handover method provided by the invention;
Fig. 4 is the active and standby switching flow figure of the main board that provides of the embodiment of the present invention;
Fig. 5 is master/backup clock homophase and the active and standby switching flow figure of the standby plate that provides of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, to a preferred embodiment of the present invention will be described in detail, should be appreciated that following illustrated preferred embodiment, only for description and interpretation the present invention, is not intended to limit the present invention.
Fig. 2 has shown the structure of clock active/standby seamless switching device, as shown in Figure 2, the module that this device is realized active and standby seamless switching mainly contains main board clock switch control unit, main board clock phase-locked loop, main board timer, standby plate clock switch control unit, standby plate clock phase-locked loop and standby plate timer.
Main board clock switch control unit response backstage or artificial master/backup clock switching command of initiating, after receiving this master/backup clock switching command, to main board timer and standby plate switch control unit, send active and standby same phase command, when main board timer receives this active and standby same phase command, start the timing of the very first time and the second time, when standby plate switch control unit receives active and standby same phase command, start standby plate timer and start timing.
Main board clock switch control unit, for control main board clock phase-locked loop hoop standby plate clock switch control unit tranmitting data register phase information in the very first time, and to main board clock phase-locked loop and standby plate clock switch control unit, send active and standby switching command in the second time subsequently.
Wherein, the very first time and the second time are the time period, and the second time was greater than the very first time.Specifically, the very first time is that the active and standby same phase command of main board clock control cell transmission receives the time of this order to standby plate, and now standby plate enters clock homophase wait state; The second time was that the active and standby same phase command of main board clock control cell transmission completes the time of master/backup clock homophase to standby plate.For example, suppose that the very first time is 20ms, the second time was 50ms, at main board clock control cell, send active and standby same phase command and start timing, 20ms constantly standby plate enters clock homophase wait state, and main board clock control cell tranmitting data register phase information now, after 30ms, namely constantly, main board clock control cell sends active and standby switching command to 50ms.
Main board clock phase-locked loop for clock phase information is provided, and quits work when receiving active and standby switching command.
Main board timer starts the timing of the very first time and the second time when receiving active and standby switching command.
Standby plate clock switch control unit, is transmitted to standby plate clock phase-locked loop by the clock phase information of receiving, and when receiving active and standby switching command, controls standby plate clock phase-locked loop and carry out standby usage switching.
Standby plate clock phase-locked loop, carries out phase-locked operation according to clock phase information, and exports the clock signal of homophase according to active and standby switching command.
Clock phase-locked loop is for realizing the Phase synchronization between two clock signals of input and output, when not having clock phase information to be reference-input signal, clock phase-locked loop is output as zero, when receiving clock phase information, input signal and output signal are added to phase discriminator simultaneously and carry out phase demodulation, the error voltage that output is directly proportional to the phase difference of input voltage and output voltage, through the radio-frequency component in this error voltage of loop filter elimination, voltage is controlled in output, this control voltage will change frequency and the phase place of voltage controlled oscillator, frequency towards reference signal input signal is drawn close, finally reach the locking of loop.
Standby plate timer starts timing when standby plate clock switch control unit receives the active and standby same phase command of main board clock switch control unit transmission.
Standby plate timing is the time period, and this time period is less than the difference of the second time and the very first time, if the very first time is 20ms, the second time was 50ms, can suppose that standby plate timing is 10ms, timing, can start standby plate clock phase-locked loop and complete the synchronous of clock according to the clock phase information of the active and standby main control unit transmission of main board during the moment to 10ms.
Fig. 3 has shown the flow process of clock active/standby seamless handover method, as shown in Figure 3:
Step S301, controls main board clock phase-locked loop at the very first time main board clock switch control unit clock phase information is provided, and by main board clock switch control unit to standby plate clock switch control unit tranmitting data register phase information.
Main board clock switch control unit, after receiving backstage or artificial master/backup clock switching command of initiating, sends active and standby same phase command to main board timer and standby plate switch control unit, starts main board timer simultaneously.
The timing of main board timer is during to the very first time, and main board clock phase-locked loop provides the clock phase information of main board, and is sent to standby plate clock switch control unit by main board clock switch control unit.
Step S302, standby plate clock switch control unit forwards it to standby plate clock phase-locked loop after receiving clock phase information, and controls standby plate clock phase-locked loop and carry out phase-locked operation.
The active and standby same phase command time control standby plate timer processed that standby plate clock switch control unit receives the transmission of main board clock switch control unit starts timing, and while reaching predetermined time, standby plate clock phase-locked loop carries out phase-locked operation.
Step S303, sends active and standby switching command at the second time main board clock switch control unit to main board clock phase-locked loop and standby plate clock switch control unit.
Step S304, main board clock phase-locked loop quits work when receiving active and standby switching command, standby plate clock switch control unit is when receiving active and standby switching command, control standby plate clock phase-locked loop and carry out standby usage switching, standby plate clock phase-locked loop is exported the clock signal of homophase according to active and standby switching command.
Fig. 4 has shown the active and standby switching flow of the main board that the embodiment of the present invention provides, as shown in Figure 4:
Step S401, main board clock switch control unit receives master/backup clock switching command to start to carry out active and standby switching, sends active and standby same phase command;
Step S402, main board enters master/backup clock homophase wait state;
Step S403, main board is that standby plate sends active and standby same phase command to the other side's plate;
Step S404, main board starts this plate timer and starts timing;
Step S405, judges whether the value of timer counter is less than or equal to N, if meet in wait state, if Counter Value is greater than N, enters step S406;
Wherein, N calculates according to actual conditions, from main board clock switch control unit send active and standby same phase command time be carved into standby plate to receive this order clock cycle be constantly N clock cycle, N is positive integer;
Step S406, sends this plate clock phase information;
Step S407, judges whether the value of timer counter is less than or equal to L, if meet in wait state, if Counter Value is greater than L, enters step S408;
Wherein, L calculates according to actual conditions, and the time that completes master/backup clock homophase from main board clock switch control unit transmission active and standby same phase command to standby plate is L clock cycle;
Step S408, sends active and standby switching command, carries out active and standby switching, and main board clock phase-locked loop quits work.
Fig. 5 has shown master/backup clock homophase and the active and standby switching flow of the standby plate that the embodiment of the present invention provides, as shown in Figure 5:
Step S501, standby plate power-up initializing;
Step S502, whether the active and standby same phase command to plate that judgement receives is effective, if the invalid state after initialization, if effectively enter step S503;
Step S503, standby plate enters clock homophase wait state;
Step S504, starts this plate timer and starts timing;
Step S505, judges whether the value of timer counter is less than or equal to M, if meet in wait state, if Counter Value is greater than M, enters step S506;
Wherein, M value calculates according to actual conditions, and from standby plate, entering clock homophase wait state to the time that receives main board clock phase information is M clock cycle;
Step S506, homophase standby plate clock phase-locked loop, makes master/backup clock homophase;
Step S507, when receiving the active and standby switching command of main board transmission, carries out active and standby switching, and standby plate clock phase-locked loop starts to export the clock signal of homophase.
Hardware components of the present invention can be realized by FPGA and clock phase-locked loop, FPGA completes the information interaction of the master/slave device of clock switching controls, single line mode, active and standby switching and master/backup clock with equating function, and the adjustment that clock phase-locked loop completes clock phase realizes two plate clock homophase functions.
The implementation procedure of master/backup clock homophase is as follows:
1, the master/backup clock switching command that main board FPGA response CPU sends, enters master/backup clock homophase wait state;
2, host apparatus sends active and standby same phase command by an active and standby interconnected holding wire to standby plate, and open main board timer, this is T10 constantly, because only just carry out the homophase of master/backup clock in the moment of active and standby switching, so when FPGA receives after the switching controls instruction that CPU sends, main board clock switch control unit must first send active and standby same phase command by active and standby interconnected holding wire to standby plate clock switch control unit, allow stand-by equipment enter master/backup clock homophase wait state, this is T11 constantly;
3, when stand-by equipment enters after master/backup clock homophase wait state, start standby plate timer, this is T20 constantly, and starts the clock phase information of waiting for that host apparatus sends, for master/backup clock homophase;
4, the moment T10 that sends active and standby same phase command from main board clock switch control unit enters clock homophase wait state to standby plate, and the clock cycle of T11 is N clock cycle constantly, therefore when the timer of main board count down to N, send interrupt signal, clock active/standby control logic by active and standby interconnected holding wire to stand-by equipment tranmitting data register phase information;
5, standby plate enter clock homophase wait state constantly T20 to the clock cycle that receives the moment T21 of main board clock active/standby phase information be M clock cycle, when the timer of standby plate count down to M, initiate the same phase command of clock, homophase standby plate clock phase-locked loop, completes clock homophase;
6, the moment T10 that main board clock active/standby main control unit sends active and standby same phase command to the clock cycle that standby plate completes the moment T12 of master/backup clock homophase be L clock cycle, when the timer of main board count down to L, send active and standby switching command, when standby plate clock phase-locked loop receives this order, export the clock signal of homophase.
Wherein, the time period from moment T10 to moment T11 is the very first time, from moment T10 to the time period of T12 was the second time constantly.
Although above the present invention is had been described in detail, the invention is not restricted to this, those skilled in the art can carry out various modifications according to principle of the present invention.Therefore, all modifications of doing according to the principle of the invention, all should be understood to fall into protection scope of the present invention.
In sum, the present invention has following technique effect: the present invention has successfully realized clock phase information and the switching controls instruction that utilizes single holding wire timesharing to send main board, thereby effectively reduced the interconnected holding wire between main board and standby plate, not only meet the requirement of master/backup clock homophase, and met the demand of low-cost micro base station.
Claims (10)
1. an active and standby seamless switching device, is characterized in that, comprising:
Main board clock switch control unit, for control main board clock phase-locked loop hoop standby plate clock switch control unit tranmitting data register phase information in the very first time, and to main board clock phase-locked loop and standby plate clock switch control unit, send active and standby switching command in the second time subsequently;
Main board clock phase-locked loop for clock phase information is provided, and quits work when receiving described active and standby switching command;
Standby plate clock switch control unit, is transmitted to standby plate clock phase-locked loop by the described clock phase information of receiving, and when receiving described active and standby switching command, controls standby plate clock phase-locked loop and carry out standby usage switching; And
Standby plate clock phase-locked loop, carries out phase-locked operation according to described clock phase information, and exports the clock signal of homophase according to described active and standby switching command;
Wherein, the described very first time and the second time are the time period.
2. a kind of active and standby seamless switching device according to claim 1, is characterized in that, when described main board clock switch control unit receives master/backup clock switching command, to main board timer and standby plate clock switch control unit, sends active and standby same phase command.
3. a kind of active and standby seamless switching device according to claim 2, is characterized in that, described main board timer starts the timing of the very first time and the second time while receiving described active and standby same phase command.
4. a kind of active and standby seamless switching device according to claim 2, it is characterized in that, described device also comprises standby plate timer, starts timing when standby plate clock switch control unit receives the active and standby same phase command of described main board clock switch control unit transmission.
5. a kind of active and standby seamless switching device according to claim 4, is characterized in that, described standby plate clock switch control unit starts standby plate clock phase-locked loop and carries out phase-locked operation when the timing of standby plate timer is overtime.
6. an active and standby seamless handover method, is characterized in that, comprises the following steps:
A, at very first time main board clock switch control unit, control main board clock phase-locked loop clock phase information is provided, and to standby plate clock switch control unit, send described clock phase information by main board clock switch control unit;
B, standby plate clock switch control unit forward it to standby plate clock phase-locked loop after receiving described clock phase information, and control standby plate clock phase-locked loop and carry out phase-locked operation;
C, at the second time main board clock switch control unit, to main board clock phase-locked loop and standby plate clock switch control unit, send active and standby switching command;
D, main board clock phase-locked loop quit work when receiving described active and standby switching command, standby plate clock switch control unit is when receiving described active and standby switching command, control standby plate clock phase-locked loop and carry out standby usage switching, standby plate clock phase-locked loop is exported the clock signal of homophase according to described active and standby switching command;
Wherein, the described very first time and the second time are the time period.
7. a kind of active and standby seamless handover method according to claim 6, it is characterized in that, before described steps A, when main board clock switch control unit receives master/backup clock switching command, to main board timer and standby plate clock switch control unit, send active and standby same phase command, main board clock switch control unit starts main board timer.
8. a kind of active and standby seamless handover method according to claim 6, is characterized in that,
The described very first time is that the active and standby same phase command of main board clock control cell transmission receives the time of this order to standby plate;
Described the second time is that the active and standby same phase command of main board clock control cell transmission completes the time of master/backup clock homophase to standby plate; And
Wherein, described the second time is greater than the described very first time.
9. a kind of active and standby seamless handover method according to claim 8, it is characterized in that, when standby plate clock switch control unit receives the active and standby same phase command that described main board clock switch control unit sends, standby plate timer starts timing, and when timer timing is overtime, starts standby plate clock phase-locked loop and carry out phase-locked operation.
10. a kind of active and standby seamless handover method according to claim 9, is characterized in that, described standby plate timer timing is the time period, and this time period is less than the difference of the second time and the very first time.
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| CN201010230638.6A CN101895425B (en) | 2010-07-13 | 2010-07-13 | Master and slave seamless switching device and method |
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| CN201010230638.6A CN101895425B (en) | 2010-07-13 | 2010-07-13 | Master and slave seamless switching device and method |
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| CN101895425B true CN101895425B (en) | 2014-03-12 |
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| CN105406984B (en) * | 2015-10-22 | 2019-05-31 | 上海斐讯数据通信技术有限公司 | A kind of system and method for realizing masterslave switchover backboard clock |
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| CN101296063A (en) * | 2007-04-23 | 2008-10-29 | 中兴通讯股份有限公司 | Main/standby switching device, method and single plate |
| CN101521565A (en) * | 2008-02-26 | 2009-09-02 | 华为技术有限公司 | Main/standby system clock seamless switching method, device and communication equipment |
| CN101621371A (en) * | 2008-07-04 | 2010-01-06 | 大唐移动通信设备有限公司 | Clock design method and clock device |
| EP2146287A1 (en) * | 2008-07-16 | 2010-01-20 | STMicroelectronics (Rousset) SAS | Interface between a two-wire bus and a single-wire bus |
| CN101667906A (en) * | 2008-09-03 | 2010-03-10 | 中兴通讯股份有限公司 | Method and system for switching main and backup clocks |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050259609A1 (en) * | 2004-05-20 | 2005-11-24 | Hansquine David W | Single wire bus interface |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101296063A (en) * | 2007-04-23 | 2008-10-29 | 中兴通讯股份有限公司 | Main/standby switching device, method and single plate |
| CN101521565A (en) * | 2008-02-26 | 2009-09-02 | 华为技术有限公司 | Main/standby system clock seamless switching method, device and communication equipment |
| CN101621371A (en) * | 2008-07-04 | 2010-01-06 | 大唐移动通信设备有限公司 | Clock design method and clock device |
| EP2146287A1 (en) * | 2008-07-16 | 2010-01-20 | STMicroelectronics (Rousset) SAS | Interface between a two-wire bus and a single-wire bus |
| CN101667906A (en) * | 2008-09-03 | 2010-03-10 | 中兴通讯股份有限公司 | Method and system for switching main and backup clocks |
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Effective date of registration: 20200717 Address after: 210012 Nanjing, Yuhuatai District, South Street, Bauhinia Road, No. 68 Patentee after: Nanjing Zhongxing Software Co.,Ltd. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee before: ZTE Corp. |