CN101895425A - Master and slave seamless switching device and method - Google Patents
Master and slave seamless switching device and method Download PDFInfo
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- CN101895425A CN101895425A CN2010102306386A CN201010230638A CN101895425A CN 101895425 A CN101895425 A CN 101895425A CN 2010102306386 A CN2010102306386 A CN 2010102306386A CN 201010230638 A CN201010230638 A CN 201010230638A CN 101895425 A CN101895425 A CN 101895425A
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Abstract
The invention discloses a master and slave seamless switching device and a master and slave seamless switching method. The device comprises a master board clock switching control unit, a master board clock phase-locked loop, a slave board clock switching control unit and a slave board clock phase-locked loop, wherein the master board clock switching control unit controls the master board clock phase-locked loop to send clock phase information the first time, and sends a master and slave switching command the subsequent second time; the master board clock phase-locked loop provides clock phase information and stops working after receiving the master and slave switching command; the slave board clock switching control unit forwards the received clock phase information to the slave board clock phase-locked loop and controls the slave board clock phase-locked loop to perform master and slave switching after receiving the master and slave switching command; and the slave board clock phase-locked loop performs phase lock operation according to the clock phase information and outputs a same-phase clock signal according to the master and slave switching command. By utilizing a method for sending clock and control information in a time sharing way through a single signal wire in a master and slave design, the master and slave seamless switching is successfully realized on the master and salve interconnection signal wire.
Description
Technical field
The present invention relates to a kind of active and standby handoff technique, a kind of active and standby seamless switching device and method in particularly a kind of mobile communication.
Background technology
In cordless communication network, clock to system has very high requirement, therefore in the design of communication equipment, adopt the working method of " 1+1 " backup, under normal circumstances host apparatus provides synchronised clock for system, when host apparatus broke down or artificially initiates to switch, stand-by equipment can be taken over whole system immediately and provide clock signal for system.For realize active and standby seamless switching be in the masterslave switchover process to not influence of business, must guarantee that the clock of main board and standby plate keeps phase place consistent with frequency in masterslave switchover moment, otherwise can cause problem such as base station call drop.
Main board and standby plate all adopt a pair of holding wire to carry out active and standby information interaction in the existing clock active/standby homophase scheme, as shown in Figure 1, wherein the clock phase information of clock cable transmission main board is used for the master/backup clock homophase, data signal line transmits the switching controls instruction and the active and standby information of main board, this scheme can satisfy the requirement of the active and standby seamless switching of radio communication base station well, but clock phase information and switching controls instruction need to transmit by clock cable and data signal line respectively, so communicating by letter of main board and standby plate needs a pair of holding wire, is difficult to satisfy the requirement of low-cost compact device.
Summary of the invention
The object of the present invention is to provide a kind of active and standby seamless switching device, be used to solve and on an active and standby interconnected holding wire, finish the mutual of clock phase information and the instruction of master/backup clock switching controls.
Another object of the present invention is to provide a kind of active and standby seamless handover method, be used to solve and on an active and standby interconnected holding wire, finish the mutual of clock phase information and switching controls instruction.
According to an aspect of the present invention, provide a kind of active and standby seamless switching device, having comprised:
Main board clock switch control unit, be used for controlling the main board clock phase-locked loop to standby plate clock switch control unit tranmitting data register phase information, and send active and standby switching command to main board clock phase-locked loop and standby plate clock switch control unit in second time subsequently in the very first time;
The main board clock phase-locked loop is used to provide clock phase information, and quits work when receiving active and standby switching command;
Standby plate clock switch control unit is transmitted to the standby plate clock phase-locked loop with the clock phase information of receiving, and when receiving active and standby switching command, control standby plate clock phase-locked loop carries out active and standby with switching;
The standby plate clock phase-locked loop carries out phase-locked operation according to clock phase information, and exports the clock signal of homophase according to active and standby switching command.
When receiving the master/backup clock switching command, main board clock switch control unit sends active and standby same phase command to main board timer and standby plate clock switch control unit.
The main board timer is when receiving the described active and standby timing of the very first time and second time that begins during with phase command.
The standby plate timer is when active and standbyly picking up counting during with phase command that standby plate clock switch control unit receives that main board clock switch control unit sends.
Standby plate clock switch control unit starts the standby plate clock phase-locked loop and carries out phase-locked operation when the timing of standby plate timer is overtime.
According to a further aspect in the invention, provide a kind of active and standby seamless handover method, may further comprise the steps:
A, provide clock phase information, and send described clock phase information to standby plate clock switch control unit by main board clock switch control unit at very first time main board clock switch control unit control main board clock phase-locked loop;
B, standby plate clock switch control unit forward it to the standby plate clock phase-locked loop after receiving described clock phase information, and control standby plate clock phase-locked loop carries out phase-locked operation;
C, send active and standby switching command to main board clock phase-locked loop and standby plate clock switch control unit at the second time main board clock switch control unit;
D, main board clock phase-locked loop quit work when receiving described active and standby switching command, standby plate clock switch control unit is when receiving described active and standby switching command, control standby plate clock phase-locked loop carries out active and standby with switching, and the standby plate clock phase-locked loop is exported the clock signal of homophase according to described active and standby switching command.
Wherein, before steps A, send active and standby same phase command to main board timer and standby plate clock switch control unit when main board clock switch control unit receives the master/backup clock switching command, main board clock switch control unit starts the main board timer.
The very first time is that the main board clock control cell sends the active and standby time that receives this order with phase command to standby plate;
Second time was that the main board clock control cell sends the active and standby time of finishing the master/backup clock homophase with phase command to standby plate;
Wherein, the very first time and second time are the time period, and second time is greater than the very first time.
When standby plate clock switch control unit receive that main board clock switch control unit sends active and standby during with phase command the standby plate timer pick up counting, and startup standby plate clock phase-locked loop carries out phase-locked operation when the timer timing is overtime.
Standby plate timer timing is the time period, and should the time period less than the difference of second time and the very first time.
The present invention has following technique effect: the present invention utilizes single holding wire to realize that successfully timesharing sends the clock phase information and the instruction of master/backup clock switching controls of main board in active and standby design, thereby effectively reduced the interconnected holding wire between main board and standby plate, not only satisfy the requirement of master/backup clock homophase, and satisfied the demand of low-cost compact base station.
Description of drawings
Fig. 1 is the clock active/standby homophase scheme schematic diagram that prior art provides;
Fig. 2 is the structure chart of clock active/standby seamless switching device provided by the invention;
Fig. 3 is the flow chart of clock active/standby seamless handover method provided by the invention;
Fig. 4 is the active and standby switching flow figure of the main board that provides of the embodiment of the invention;
Fig. 5 is the master/backup clock homophase and the active and standby switching flow figure of the standby plate that provides of the embodiment of the invention.
Embodiment
, should be appreciated that following illustrated preferred embodiment only is used for description and interpretation the present invention, and be not used in qualification the present invention a preferred embodiment of the present invention will be described in detail below in conjunction with accompanying drawing.
Fig. 2 has shown the structure of clock active/standby seamless switching device, as shown in Figure 2, this device realizes that the module of active and standby seamless switching mainly contains main board clock switch control unit, main board clock phase-locked loop, main board timer, standby plate clock switch control unit, standby plate clock phase-locked loop and standby plate timer.
Main board clock switch control unit response backstage or artificial master/backup clock switching command of initiating, send active and standby same phase command to main board timer and standby plate switch control unit after receiving this master/backup clock switching command, active and standbyly begin the timing of the very first time and second time during with phase command when the main board timer receives this, active and standbyly start the standby plate timer during with phase command and pick up counting when the standby plate switch control unit receives.
Main board clock switch control unit, be used for controlling the main board clock phase-locked loop to standby plate clock switch control unit tranmitting data register phase information, and send active and standby switching command to main board clock phase-locked loop and standby plate clock switch control unit in second time subsequently in the very first time.
Wherein, the very first time and second time are the time period, and second time is greater than the very first time.Specifically, the very first time is that the main board clock control cell sends and active and standbyly to receive time of this order with phase command to standby plate, and this moment, standby plate entered clock homophase wait state; Second time was that the main board clock control cell sends the active and standby time of finishing the master/backup clock homophase with phase command to standby plate.For example, suppose that the very first time is 20ms, second time was 50ms, then send and active and standbyly pick up counting with phase command at the main board clock control cell, 20ms constantly standby plate enters clock homophase wait state, this moment main board clock control cell tranmitting data register phase information, after 30ms, just the 50ms moment, the main board clock control cell sends active and standby switching command.
The main board clock phase-locked loop is used to provide clock phase information, and quits work when receiving active and standby switching command.
The main board timer begins the timing of the very first time and second time when receiving active and standby switching command.
Standby plate clock switch control unit is transmitted to the standby plate clock phase-locked loop with the clock phase information of receiving, and when receiving active and standby switching command, control standby plate clock phase-locked loop carries out active and standby with switching.
The standby plate clock phase-locked loop carries out phase-locked operation according to clock phase information, and exports the clock signal of homophase according to active and standby switching command.
Clock phase-locked loop is the Phase synchronization that is used to realize between two clock signals of input and output, when not having clock phase information to be reference-input signal, clock phase-locked loop is output as zero, when receiving clock phase information, input signal and output signal are added to phase discriminator simultaneously and carry out phase demodulation, the error voltage that output is directly proportional with the phase difference of input voltage and output voltage, through the radio-frequency component in this error voltage of loop filter elimination, output control voltage, this control voltage will make the frequency of voltage controlled oscillator and phase place change, frequency towards the reference signal input signal is drawn close, and reaches the locking of loop at last.
The standby plate timer is when active and standbyly picking up counting during with phase command that standby plate clock switch control unit receives that main board clock switch control unit sends.
The standby plate timing is the time period, and should the time period less than the difference of second time and the very first time, if the very first time is 20ms, second time was 50ms, can suppose that the standby plate timing is 10ms, timing, can start the standby plate clock phase-locked loop and finish the synchronous of clock according to the clock phase information of the active and standby main control unit transmission of main board during the moment to 10ms.
Fig. 3 has shown the flow process of clock active/standby seamless handover method, as shown in Figure 3:
Step S301 provides clock phase information at very first time main board clock switch control unit control main board clock phase-locked loop, and by main board clock switch control unit to standby plate clock switch control unit tranmitting data register phase information.
Main board clock switch control unit sends active and standby same phase command to main board timer and standby plate switch control unit after receiving backstage or artificial master/backup clock switching command of initiating, start the main board timer simultaneously.
The timing of main board timer is during to the very first time, and the main board clock phase-locked loop provides the clock phase information of main board, and is sent to standby plate clock switch control unit by main board clock switch control unit.
Step S302, standby plate clock switch control unit forwards it to the standby plate clock phase-locked loop after receiving clock phase information, and control standby plate clock phase-locked loop carries out phase-locked operation.
Standby plate clock switch control unit receives active and standby the picking up counting with phase command time control system standby plate timer of main board clock switch control unit transmission, and the standby plate clock phase-locked loop carries out phase-locked operation when reaching preset time.
Step S303 sends active and standby switching command at the second time main board clock switch control unit to main board clock phase-locked loop and standby plate clock switch control unit.
Step S304, the main board clock phase-locked loop quits work when receiving active and standby switching command, standby plate clock switch control unit is when receiving active and standby switching command, control standby plate clock phase-locked loop carries out active and standby with switching, and the standby plate clock phase-locked loop is exported the clock signal of homophase according to active and standby switching command.
Fig. 4 has shown the active and standby switching flow of the main board that the embodiment of the invention provides, as shown in Figure 4:
Step S401, main board clock switch control unit receive the master/backup clock switching command to begin to carry out active and standby switching, sends active and standby same phase command;
Step S402, main board enter master/backup clock homophase wait state;
Step S403, main board are that standby plate sends active and standby same phase command to the other side's plate;
Step S404, main board start this plate timer and pick up counting;
Step S405 judges whether the value of timer counter is less than or equal to N, then is in wait state if satisfy, if Counter Value then enters step S406 greater than N;
Wherein, N calculates according to actual conditions, from main board clock switch control unit send active and standby with phase command the time be carved into standby plate to receive this order clock cycle constantly be N clock cycle, N is a positive integer;
Step S406 sends this plate clock phase information;
Step S407 judges whether the value of timer counter is less than or equal to L, then is in wait state if satisfy, if Counter Value then enters step S408 greater than L;
Wherein, L calculates according to actual conditions, and sending the active and standby time of finishing the master/backup clock homophase with phase command to standby plate from main board clock switch control unit is L clock cycle;
Step S408 sends active and standby switching command, carries out active and standby switching, and the main board clock phase-locked loop quits work.
Fig. 5 has shown the master/backup clock homophase and the active and standby switching flow of the standby plate that the embodiment of the invention provides, as shown in Figure 5:
Step S501, the standby plate power-up initializing;
Step S502 judges active and standby whether effective with phase command to plate receive, if the invalid state that then is in after the initialization, if effectively then enter step S503;
Step S503, standby plate enter clock homophase wait state;
Step S504 starts this plate timer and picks up counting;
Step S505 judges whether the value of timer counter is less than or equal to M, then is in wait state if satisfy, if Counter Value then enters step S506 greater than M;
Wherein, the M value calculates according to actual conditions, and entering clock homophase wait state to the time that receives main board clock phase information from standby plate is M clock cycle;
Step S506, homophase standby plate clock phase-locked loop makes the master/backup clock homophase;
Step S507 when receiving the active and standby switching command of main board transmission, carries out active and standby switching, and the standby plate clock phase-locked loop begins to export the clock signal of homophase.
Hardware components of the present invention can be realized by FPGA and clock phase-locked loop, FPGA finishes the information interaction of the master/slave device of clock switching controls, single line mode, active and standby switching and master/backup clock with equating function, and the adjustment that clock phase-locked loop is finished clock phase realizes two plate clock homophase functions.
The implementation procedure of master/backup clock homophase is as follows:
1, main board FPGA responds the master/backup clock switching command that CPU sends, and enters master/backup clock homophase wait state;
2, host apparatus sends active and standby same phase command by an active and standby interconnected holding wire to standby plate, and open the main board timer, this is T10 constantly, because only just carry out the homophase of master/backup clock in the moment of active and standby switching, so after FPGA receives the switching controls instruction that CPU sends, main board clock switch control unit must send active and standby same phase command by active and standby interconnected holding wire to standby plate clock switch control unit earlier, allow stand-by equipment enter master/backup clock homophase wait state, this is T11 constantly;
3, after stand-by equipment enters master/backup clock homophase wait state, start the standby plate timer, this is T20 constantly, and begins the clock phase information of waiting for that host apparatus sends, is used for the master/backup clock homophase;
4, sending active and standby moment T10 with phase command from main board clock switch control unit enters clock homophase wait state to standby plate the clock cycle of T11 is N clock cycle constantly, therefore when the timer of main board count down to N, send interrupt signal, the clock active/standby control logic by active and standby interconnected holding wire to stand-by equipment tranmitting data register phase information;
5, standby plate enter clock homophase wait state constantly T20 to clock cycle of the moment T21 that receives main board clock active/standby phase information be M clock cycle, when the timer of standby plate count down to M, initiate the same phase command of clock, homophase standby plate clock phase-locked loop is finished the clock homophase;
6, main board clock active/standby main control unit send active and standby moment T10 with phase command to the clock cycle that standby plate is finished the moment T12 of master/backup clock homophase be L clock cycle, when the timer of main board count down to L, send active and standby switching command, export the clock signal of homophase when the standby plate clock phase-locked loop receives this order.
Wherein, the time period from moment T10 to moment T11 is the very first time, and the time period from moment T10 to moment T12 was second time.
Although above the present invention is had been described in detail, the invention is not restricted to this, those skilled in the art can carry out various modifications according to principle of the present invention.Therefore, all modifications of doing according to the principle of the invention all should be understood to fall into protection scope of the present invention.
In sum, the present invention has following technique effect: the present invention has successfully realized utilizing single holding wire timesharing to send clock phase information and the switching controls instruction of main board, thereby effectively reduced the interconnected holding wire between main board and standby plate, not only satisfy the requirement of master/backup clock homophase, and satisfied the demand of low-cost micro base station.
Claims (10)
1. an active and standby seamless switching device is characterized in that, comprising:
Main board clock switch control unit, be used for controlling the main board clock phase-locked loop to standby plate clock switch control unit tranmitting data register phase information, and send active and standby switching command to main board clock phase-locked loop and standby plate clock switch control unit in second time subsequently in the very first time;
The main board clock phase-locked loop is used to provide clock phase information, and quits work when receiving described active and standby switching command;
Standby plate clock switch control unit is transmitted to the standby plate clock phase-locked loop with the described clock phase information of receiving, and when receiving described active and standby switching command, control standby plate clock phase-locked loop carries out active and standby with switching; And
The standby plate clock phase-locked loop carries out phase-locked operation according to described clock phase information, and exports the clock signal of homophase according to described active and standby switching command.
2. a kind of active and standby seamless switching device according to claim 1 is characterized in that, sends active and standby same phase command to main board timer and standby plate clock switch control unit when described main board clock switch control unit receives the master/backup clock switching command.
3. a kind of active and standby seamless switching device according to claim 2 is characterized in that described device also comprises the main board timer, when receiving the described active and standby timing of the very first time and second time that begins during with phase command.
4. a kind of active and standby seamless switching device according to claim 2, it is characterized in that, described device also comprises the standby plate timer, when active and standbyly picking up counting during with phase command that standby plate clock switch control unit receives that described main board clock switch control unit sends.
5. a kind of active and standby seamless switching device according to claim 4 is characterized in that, described standby plate clock switch control unit starts the standby plate clock phase-locked loop and carries out phase-locked operation when the timing of standby plate timer is overtime.
6. an active and standby seamless handover method is characterized in that, may further comprise the steps:
A, provide clock phase information, and send described clock phase information to standby plate clock switch control unit by main board clock switch control unit at very first time main board clock switch control unit control main board clock phase-locked loop;
B, standby plate clock switch control unit forward it to the standby plate clock phase-locked loop after receiving described clock phase information, and control standby plate clock phase-locked loop carries out phase-locked operation;
C, send active and standby switching command to main board clock phase-locked loop and standby plate clock switch control unit at the second time main board clock switch control unit;
D, main board clock phase-locked loop quit work when receiving described active and standby switching command, standby plate clock switch control unit is when receiving described active and standby switching command, control standby plate clock phase-locked loop carries out active and standby with switching, and the standby plate clock phase-locked loop is exported the clock signal of homophase according to described active and standby switching command.
7. a kind of active and standby seamless handover method according to claim 6, it is characterized in that, before described steps A, send active and standby same phase command to main board timer and standby plate clock switch control unit when main board clock switch control unit receives the master/backup clock switching command, main board clock switch control unit starts the main board timer.
8. a kind of active and standby seamless handover method according to claim 6 is characterized in that,
The described very first time is that the main board clock control cell sends the active and standby time that receives this order with phase command to standby plate;
Described second time is that the main board clock control cell sends the active and standby time of finishing the master/backup clock homophase with phase command to standby plate; And
Wherein, the very first time and second time are the time period, and second time is greater than the very first time.
9. a kind of active and standby seamless handover method according to claim 8, it is characterized in that, when standby plate clock switch control unit receive that described main board clock switch control unit sends active and standby during with phase command the standby plate timer pick up counting, and startup standby plate clock phase-locked loop carries out phase-locked operation when the timer timing is overtime.
10. a kind of active and standby seamless handover method according to claim 9 is characterized in that, described standby plate timer timing is the time period, and should the time period less than the difference of second time and the very first time.
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| CN201010230638.6A CN101895425B (en) | 2010-07-13 | 2010-07-13 | Master and slave seamless switching device and method |
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| CN201010230638.6A CN101895425B (en) | 2010-07-13 | 2010-07-13 | Master and slave seamless switching device and method |
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| CN101895425A true CN101895425A (en) | 2010-11-24 |
| CN101895425B CN101895425B (en) | 2014-03-12 |
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| CN105406984A (en) * | 2015-10-22 | 2016-03-16 | 上海斐讯数据通信技术有限公司 | System and method of realizing main/standby switching backboard clock |
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| CN101895425B (en) | 2014-03-12 |
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Effective date of registration: 20200717 Address after: 210012 Nanjing, Yuhuatai District, South Street, Bauhinia Road, No. 68 Patentee after: Nanjing Zhongxing Software Co.,Ltd. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee before: ZTE Corp. |