CN107396326A - A kind of method and master clock system for generating System Frame Number - Google Patents
A kind of method and master clock system for generating System Frame Number Download PDFInfo
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- CN107396326A CN107396326A CN201710652739.4A CN201710652739A CN107396326A CN 107396326 A CN107396326 A CN 107396326A CN 201710652739 A CN201710652739 A CN 201710652739A CN 107396326 A CN107396326 A CN 107396326A
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- frame number
- system frame
- master clock
- relative time
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
- H04W4/06—Selective distribution of broadcast services, e.g. multimedia broadcast multicast service [MBMS]; Services to user groups; One-way selective calling services
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
- H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/04—Arrangements for maintaining operational condition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention proposes a kind of master clock system, including the first master clock transmission board and the second master clock transmission board run simultaneously with active/standby mode；First master clock transmission board connects identical external reference clock source with the second master clock transmission board；When the first master clock transmission board or the second master clock transmission board are as mainboard, according to the external reference clock source signals of reception, clock signal and System Frame Number are generated；Pps pulse per second signal and absolute time signal are sent to slave board；When the first master clock transmission board or the second master clock transmission board are as slave board, according to the external reference clock source signals of reception, or the pps pulse per second signal and absolute time signal that mainboard is sent, generate the clock signal with frequency with phase with the clock signal of mainboard generation, and the System Frame Number identical System Frame Number of generation and mainboard generation.Using said system, the master clock transmission board that active/standby mode works can be made to generate identical System Frame Number when working alternately.
Description
Technical field
The present invention relates to wireless communication technology field, more particularly to a kind of method for generating System Frame Number and master clock system
System.
Background technology
Multimedia broadcast/multicast service (the evolved Multimedia Broadcast/ of evolution
MulticastService, eMBMS) be it is a kind of by mobile cellular network from a particular source into particular range it is multiple
User equipment transmits the technology of identical data, and descending point-to-multipoint service can be transmitted using eMBMS technologies.When base station uses
During eMBMS technical transmission data, multiple cells launch same waveform in synchronization, i.e. all cells positioned at some position are equal
Identical content is transmitted simultaneously using identical Radio Resource, so as to obtain merging gain.Using eMBMS technical transmissions
Data need different base station to transmit identical data in identical System Frame Number, it is therefore desirable to ensure different base station when identical
The System Frame Number for carving generation is identical.
It is general to use 1+1 backup mode to configure master clock transmission board for base station in order to ensure base station reliability.Work as base station
Master clock transmission board when breaking down, standby master clock transmission board is started working, and System Frame Number is generated for base station.But
It is that master clock transmission board and standby master clock transmission board are when completing work alternating, the frequent system-frame generated
Number inconsistent situation, cause different base station different in the System Frame Number mutually generated in the same time, and then influence data transfer.
The content of the invention
The defects of based on above-mentioned prior art and deficiency, when the present invention proposes a kind of method for generating System Frame Number and master control
Master slave system, base station can be made to generate consistent System Frame Number before and after masterslave switchover occurs for master clock transmission board.
A kind of master clock system, including：
The the first master clock transmission board and the second master clock transmission board run simultaneously with active/standby mode；First master
Control clock transfer plate connects identical external reference clock source with the second master clock transmission board；
When the first master clock transmission board or the second master clock transmission board are as mainboard, it is specifically used for：
According to the external reference clock source signals of reception, clock signal and System Frame Number are generated；Pulse per second (PPS) is sent to slave board
Signal and absolute time signal；
When the first master clock transmission board or the second master clock transmission board are as slave board, it is specifically used for：
It is raw according to the external reference clock source signals of reception, or the pps pulse per second signal and absolute time signal that mainboard is sent
Clock signal into the clock signal generated with the mainboard with frequency with phase, and the System Frame Number of generation and mainboard generation
Identical System Frame Number.
Preferably, the first master clock transmission board or the second master clock transmission board are joined according to the outside of reception
Clock source signals are examined, when generating System Frame Number, are specifically used for：
According to the external reference clock source signals of reception, absolute time is calculated；
According to the absolute time, relative time is calculated；
By the relative time, modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
Preferably, the first master clock transmission board connects identical synchronization with the second master clock transmission board
Source；When the first master clock transmission board or the second master clock transmission board are as mainboard, it is additionally operable to：
Receive the pps pulse per second signal that the synchronisation source is sent；
When the pps pulse per second signal interrupts, according to the external reference clock source signals of reception, absolute time is calculated；
According to the absolute time, relative time is calculated；
By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；
When the pps pulse per second signal arrives again, the relative time initial value enters with the System Frame Number cycle of setting
The processing of row modulo operation, obtains System Frame Number.
Preferably, the second that the first master clock transmission board or the second master clock transmission board are sent according to mainboard
During the System Frame Number identical System Frame Number of pulse signal and absolute time signal, generation and mainboard generation, it is specifically used for：
When the pps pulse per second signal that mainboard is sent interrupts, the absolute time signal that mainboard is sent is received, and according to described exhausted
To time signal, absolute time is confirmed；
According to the absolute time, relative time is calculated；
By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；
When the pps pulse per second signal arrives again, the relative time initial value enters with the System Frame Number cycle of setting
The processing of row modulo operation, obtains System Frame Number.
Preferably, the first master clock transmission board and the second master clock transmission board work on power at the same time
When, mainboard and slave board are distinguished by main and standby competition.
A kind of method for generating System Frame Number, applied to master clock transmission board, the master clock transmission board and outside
Reference clock source connects with synchronisation source, and this method includes：
According to the external reference clock source signals of reception, absolute time is calculated；
According to the absolute time, relative time is calculated；
By the relative time, modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
Preferably, this method also includes：
Receive the pps pulse per second signal that the synchronisation source is sent；
When the pps pulse per second signal interrupts, according to the external reference clock source signals of reception, absolute time is calculated；
According to the absolute time, relative time is calculated；
By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；
When the pps pulse per second signal arrives again, the relative time initial value enters with the System Frame Number cycle of setting
The processing of row modulo operation, obtains System Frame Number.
A kind of method for generating System Frame Number, applied to master clock transmission board, the master clock transmission board and conduct
Other master clock transmission boards connection of mainboard, this method include：
When the pps pulse per second signal that mainboard is sent interrupts, the absolute time signal that mainboard is sent is received, and according to described exhausted
To time signal, absolute time is confirmed；
According to the absolute time, relative time is calculated；
By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；
When the pps pulse per second signal arrives again, the relative time initial value enters with the System Frame Number cycle of setting
The processing of row modulo operation, obtains System Frame Number.
A kind of device for generating System Frame Number, applied to master clock transmission board, the master clock transmission board and outside
Reference clock source connects with synchronisation source, and the device includes：
First computing unit, for the external reference clock source signals according to reception, absolute time is calculated；
Second computing unit, for according to the absolute time, relative time to be calculated；
Modulo operation unit, for by the relative time, modulo operation processing to be carried out with the System Frame Number cycle of setting,
Obtain System Frame Number.
Preferably, the device also includes：
Signal receiving unit, the pps pulse per second signal sent for receiving the synchronisation source；
First computing unit, it is additionally operable to when the pps pulse per second signal interrupts, according to the external reference clock of reception
Source signal, absolute time is calculated；
Second computing unit, it is additionally operable to, according to the absolute time, relative time be calculated；When will be described relative
Between, plus the Timing Advance of setting, obtain relative time initial value；
The modulo operation unit, it is additionally operable to when the pps pulse per second signal arrives again, by the relative time initial value,
Modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
A kind of device for generating System Frame Number, applied to master clock transmission board, the master clock transmission board and conduct
Other master clock transmission boards connection of mainboard, the device include：
Time receiving unit, when the pps pulse per second signal for being sent when mainboard interrupts, receive the absolute time that mainboard is sent
Signal, and according to the absolute time signal, confirm absolute time；
3rd computing unit, for according to the absolute time, relative time to be calculated；
4th computing unit, for by the relative time, plus the Timing Advance of setting, at the beginning of obtaining relative time
Value；
Operation processing unit, for when the pps pulse per second signal arrives again, by the relative time initial value, with setting
The System Frame Number cycle carry out modulo operation processing, obtain System Frame Number.
Master clock system proposed by the present invention, the first master clock transmission board and the second master clock transmission board are with active and standby
Mode is run simultaneously, and the first master clock transmission board and the second master clock transmission board are given birth to according to identical external reference clock source
Into System Frame Number.And mainboard sends pps pulse per second signal and absolute time signal to slave board, and when main board failure, slave board can root
The System Frame Number identical System Frame Number of the generation of pps pulse per second signal and absolute time signal and mainboard generation that are sent according to mainboard, by
This ensure that master clock system when active and standby plate is switched, can generate identical System Frame Number always.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is a kind of structural representation of master clock system provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic flow sheet of method for generating System Frame Number provided in an embodiment of the present invention；
Fig. 3 is the schematic flow sheet of the method for another generation System Frame Number provided in an embodiment of the present invention；
Fig. 4 is the schematic flow sheet of the method for another generation System Frame Number provided in an embodiment of the present invention；
Fig. 5 is a kind of structural representation of device for generating System Frame Number provided in an embodiment of the present invention；
Fig. 6 is the structural representation of the device of another generation System Frame Number provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Shown in Figure 1 the embodiment of the invention discloses a kind of master clock system, the system includes：
The the first master clock transmission board 101 and the second master clock transmission board 102 run simultaneously with active/standby mode；It is described
First master clock transmission board 101 and the second master clock transmission board 102 connection identical external reference clock source；
Specifically, the first master clock transmission board 101 and the second master clock transmission board 102 pass for identical master clock
Input board, for the external reference clock source signals according to reception, generate clock signal and frame synchronizing signal, wherein frame synchronizing signal
Including System Frame Number (SystemFrame Number, SFN).
First master clock transmission board 101 and the second master clock transmission board 102 are run simultaneously, due to the first master clock
The master clock transmission board 102 of transmission board 101 and second connects identical external reference clock source signals, therefore, when the first master control
When the master clock transmission board 102 of clock transfer plate 101 and second is working properly, the clock signal and frame synchronizing signal of generation are
Identical.
Although the first master clock transmission board 101 and the second master clock transmission board 102 are run simultaneously, the first master control
The master clock transmission board 102 of clock transfer plate 101 and second still has point of mainboard and slave board.The clock signal and frame of generation are same
Signal output is walked to baseband board, and by master clock transmission board used by baseband board as mainboard；And generate clock signal and
Frame synchronizing signal, but not by master clock transmission board used by baseband board as slave board.Mainboard and slave board are to base band
While plate exports clock signal and frame synchronizing signal, activestandby state signal is exported respectively to baseband board, so that baseband board is clear and definite
Which is mainboard, preferential clock signal and frame synchronizing signal using mainboard output.
When the master clock transmission board 102 of the first master clock transmission board 101 or described second is as mainboard, specifically
For：
According to the external reference clock source signals of reception, clock signal and System Frame Number are generated；Pulse per second (PPS) is sent to slave board
Signal and absolute time signal；
Specifically, when the first master clock transmission board 101 or the second master clock transmission board 102 are as mainboard, not only
Clock signal and System Frame Number are generated according to the external reference clock source signals of reception, also to slave board transmission pps pulse per second signal and absolutely
To time signal.
Wherein, pps pulse per second signal is the signal for being 1 second in cycle for being generated after locking phase processor of mainboard itself clock module.It is main
Plate sends pps pulse per second signal to slave board, and clock is corresponded to pps pulse per second signal so that slave board controls the crystal oscillator of itself clock module to export
Clock signal of the source with frequency with phase.
When the master clock transmission board 102 of the first master clock transmission board 101 or described second is as slave board, specifically
For：
It is raw according to the external reference clock source signals of reception, or the pps pulse per second signal and absolute time signal that mainboard is sent
Clock signal into the clock signal generated with the mainboard with frequency with phase, and the System Frame Number of generation and mainboard generation
Identical System Frame Number.
Specifically, when the first master clock transmission board 101 or the second master clock transmission board 102 are as slave board, not only
Can be generated according to the external reference clock source signals of reception with mainboard identical clock signal and System Frame Number, and can also root
The pps pulse per second signal and absolute time signal sent according to mainboard, generation and mainboard identical clock signal and System Frame Number.So
The benefit of setting is, when slave board clock module breaks down, pps pulse per second signal and absolute time that slave board is sent according to mainboard
Signal, the System Frame Number identical System Frame Number of generation and mainboard generation, and the clock signal of generation and mainboard generation are the same as frequency
With the clock signal of phase.
It should be noted that System Frame Number is the value of a real-time change, the above-mentioned System Frame Number with mainboard generation
Identical System Frame Number, refer to the System Frame Number with mainboard generation, the System Frame Number changed according to identical rule.
In the master clock system that the embodiment of the present invention proposes, the first master clock transmission board and the transmission of the second master clock
Plate is run simultaneously with active/standby mode.First master clock transmission board and the second master clock transmission board are according to identical external reference
Clock source generates System Frame Number, and mainboard sends pps pulse per second signal and absolute time signal to slave board, standby when main board failure
The System Frame Number identical system that the pps pulse per second signal and absolute time signal generation that plate can be sent according to mainboard generate with mainboard
System frame number, thereby ensures that master clock system when active and standby plate is switched, can generate identical System Frame Number always.
Optionally, in another embodiment of the present invention, the first master clock transmission board 101 or the second master clock pass
Input board 102 when generating System Frame Number, is specifically used for according to the external reference clock source signals of reception：
According to the external reference clock source signals of reception, absolute time is calculated；According to the absolute time, calculate
To relative time；By the relative time, modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
Specifically, external reference clock source signals can provide temporal information for master control clock transfer plate, master clock passes
Input board is therefrom resolved to current time, i.e. absolute time.
Relative time be in units of 10 milliseconds, above-mentioned absolute time relative to the time reference being pre-configured with time
Value.For example, it is assumed that current time is 3 seconds January 1 day 12 point 0 minute in 2017, the time reference being pre-configured with is on January 1st, 2017
12 points 0 second 0 minute, then relative time calculate as 300.
In embodiments of the present invention, the initialization system frame number cycle be 1024, i.e., 10.24 seconds.
The relative time being calculated and the System Frame Number of setting are subjected to modulo operation, System Frame Number can be calculated,
I.e.
SFN={ relative time } mod { SFN cycles }
Wherein, mod is modulo operation.
Optionally, in another embodiment of the present invention, the first master clock transmission board 101 and the second master clock pass
Input board 102 connects identical synchronisation source；When the first master clock transmission board 101 or the second master clock transmission board 102 are as master
During plate, it is additionally operable to：
Receive the pps pulse per second signal that the synchronisation source is sent；
Specifically, when the first master clock transmission board 101 or the second master clock transmission board 102 are as mainboard, first
The master clock transmission board 102 of master clock transmission board 101 or second receives pps pulse per second signal from synchronisation source.
When the pps pulse per second signal interrupts, according to the external reference clock source signals of reception, absolute time is calculated；
According to the absolute time, relative time is calculated；By the relative time, plus the Timing Advance of setting, phase is obtained
To time initial value；
Specifically, when pps pulse per second signal interrupts, the embodiment of the present invention reads absolute time, and according to be pre-configured with when
Between benchmark go out relative time, then the relative time calculated add 1 second, as relative time initial value.When this is relative
Between initial value be stored in SFN initial registers.
For example, it is assumed that current time is 3 seconds January 1 day 12 point 0 minute in 2017, the time reference being pre-configured with is 2017 1
Month 1 day 12 points 0 second 0 minute, then the SFN initial registers values write during 1PPS was interrupted 3 seconds January 1 day 12 point 0 minute in 2017 are
400。
When the pps pulse per second signal arrives again, the relative time initial value enters with the System Frame Number cycle of setting
The processing of row modulo operation, obtains System Frame Number.
Specifically, when next pps pulse per second signal arrives, the embodiment of the present invention reads storage from SFN initial registers
Relative time initial value, according to the relative time initial value, by formula
SFN={ relative time } mod { SFN cycles }
System Frame Number is calculated.
Said process realizes the calibration to System Frame Number so that the System Frame Number and external clock source signal of mainboard generation
Matching completely.When system judges to need re-synchronization SFN once, calibration is performed as procedure described above.Motherboard hardware is patrolled
As long as having the legal relative time initial value being newly written in volume judgement SFN initial registers, will be arrived automatically in pps pulse per second signal
When coming, relative time initial value is read, System Frame Number is calculated.
Judgement of the mainboard to the opportunity of calibration system frame number, by the way that clock module clock is contrasted with pps pulse per second signal
Confirm, when clock module clock and pps pulse per second signal mismatch, System Frame Number is calibrated.Or simple mode is,
When each pps pulse per second signal interrupts, calibration process is carried out to System Frame Number.
Optionally, in another embodiment of the present invention, the first master clock transmission board 101 or the second master clock pass
The pps pulse per second signal and absolute time signal that input board 102 is sent according to mainboard, generate the System Frame Number phase with mainboard generation
With System Frame Number when, be specifically used for：
When the pps pulse per second signal that mainboard is sent interrupts, the absolute time signal that mainboard is sent is received, and according to described exhausted
To time signal, absolute time is confirmed；
Specifically, in embodiments of the present invention, the first master clock transmission board 101 and the second master clock transmission board 102
Between configure host-standby communication link, for transmitting absolute time signal.When slave board clock exception, the absolute of reception can be passed through
Time signal, and the pps pulse per second signal that mainboard is sent, generate System Frame Number, ensure that active and standby plate can generate identical system-frame
Number.
When mainboard sends pps pulse per second signal to slave board to interrupt, mainboard sends absolute time by host-standby communication chain road direction slave board
Between signal.Slave board confirms absolute time according to the absolute time signal of reception.
According to the absolute time, relative time is calculated；By the relative time, plus the time advance of setting
Amount, obtains relative time initial value；
Specifically, after absolute time is determined, the embodiment of the present invention calculates phase according to the time reference being pre-configured with
To the time, then the relative time calculated is added 1 second, as relative time initial value.At the beginning of the relative time initial value is stored to SFN
In value register.
For example, it is assumed that current time is 3 seconds January 1 day 12 point 0 minute in 2017, the time reference being pre-configured with is 2017 1
Month 1 day 12 points 0 second 0 minute, then the SFN initial registers values write during 1PPS was interrupted 3 seconds January 1 day 12 point 0 minute in 2017 are
400。
When the pps pulse per second signal arrives again, the relative time initial value enters with the System Frame Number cycle of setting
The processing of row modulo operation, obtains System Frame Number.
Specifically, when next pps pulse per second signal arrives, the embodiment of the present invention reads storage from SFN initial registers
Relative time initial value, according to the relative time initial value, be calculated according to formula S FN={ relative time } mod { SFN cycles }
System Frame Number.
Said process realizes the calibration to System Frame Number so that mainboard is identical with the System Frame Number that slave board generates.
When slave board judges to need re-synchronization SFN once, calibration is performed as procedure described above.As long as slave board hardware logic judges
There is the legal relative time initial value being newly written in SFN initial registers, phase will be read automatically when pps pulse per second signal arrives
To time initial value, System Frame Number is calculated.
Judgement of the slave board to the opportunity of calibration system frame number, by by the absolute time signal of clock module clock or reception
Contrast confirmation is carried out with the pps pulse per second signal of reception, when clock module clock or the absolute time signal of reception and the second arteries and veins of reception
When rushing signal mismatch, System Frame Number is calibrated.Or simple mode is, when each pps pulse per second signal interrupts,
Calibration process is carried out to System Frame Number.
Optionally, in another embodiment of the present invention, the first master clock transmission board 101 and the second master clock pass
When input board 102 works on power at the same time, mainboard and slave board are distinguished by main and standby competition.
Specifically, in embodiments of the present invention, respectively as mainboard and the first master clock transmission board 101 of slave board and
Communication link status signal in place, fine or not status signal, activestandby state letter are built between two master clock transmission boards 102
Number.When the first master clock transmission board 101 and the second master clock transmission board 102 are reached the standard grade simultaneously, the transmission of the first master clock
The master clock transmission board 102 of plate 101 and second carries out main and standby competition, which determines as mainboard, which is as slave board.
When the first master clock transmission board 101 and the second master clock transmission board 102 carry out main and standby competition, respectively to right
Side's transmission status signal in place, fine or not status signal, activestandby state signal, verify whether other side is in place, state quality.Need simultaneously
Additionally to check whether clock module is normal, in the case of other situations all identicals, clock module is normal, using the teaching of the invention it is possible to provide meet
The master clock transmission board prioritized contention of index request clock is mainboard.In the first master clock transmission board 101 and the second master control
After clock transfer plate 102 distinguishes mainboard and slave board role, active and standby signal is sent to other side, tell other side itself be mainboard or
Slave board, meanwhile, activestandby state signal is sent to baseband board, it is mainboard to make which clear and definite master clock transmission board of baseband board, which
Master clock transmission board is slave board.
The embodiment of the invention discloses a kind of method for generating System Frame Number, applied to master clock transmission board, the master
Control clock transfer plate is connected with external reference clock source and synchronisation source, and shown in Figure 2, this method includes：
S201, the external reference clock source signals according to reception, are calculated absolute time；
S202, according to the absolute time, relative time is calculated；
S203, by the relative time, carry out modulo operation processing with the System Frame Number cycle of setting, obtain system-frame
Number.
Specifically, in the present embodiment each step specific works content, refer to the content of the embodiment of said system,
Here is omitted.
Optionally, in another embodiment of the present invention, shown in Figure 3, this method also includes：
S301, receive the pps pulse per second signal that the synchronisation source is sent；
When the pps pulse per second signal interrupts, step S302, the external reference clock source signals according to reception are performed, are calculated
Obtain absolute time；
S303, according to the absolute time, relative time is calculated；
S304, by the relative time, plus the Timing Advance of setting, obtain relative time initial value；
When the pps pulse per second signal arrives again, perform step S305, by the relative time initial value, be with setting
The system frame number cycle carries out modulo operation processing, obtains System Frame Number.
Specifically, in the present embodiment each step specific works content, refer to the content of the embodiment of said system,
Here is omitted.
In embodiments of the present invention, master clock transmission board is according to the pps pulse per second signal of reception, to calculate relative time, and
Legal relative time initial value is calculated before the arriving of next pps pulse per second signal.When next pps pulse per second signal arrives
When, System Frame Number is calculated according to relative time initial value.Above-mentioned processing procedure realizes the calibration to System Frame Number so that main
The System Frame Number of control clock transfer plate generation keeps matching with clock signal.
It is described applied to master clock transmission board the embodiment of the invention discloses the method for another generation System Frame Number
Master clock transmission board is connected with other master clock transmission boards as mainboard, and shown in Figure 4, this method includes：
When the pps pulse per second signal that mainboard is sent interrupts, perform step S401, receive the absolute time signal that mainboard is sent,
And according to the absolute time signal, confirm absolute time；
S402, according to the absolute time, relative time is calculated；
S403, by the relative time, plus the Timing Advance of setting, obtain relative time initial value；
When the pps pulse per second signal arrives again, perform step S404, by the relative time initial value, be with setting
The system frame number cycle carries out modulo operation processing, obtains System Frame Number.
Specifically, in the present embodiment each step specific works content, refer to the content of the embodiment of said system,
Here is omitted.
In embodiments of the present invention, the pulse per second (PPS) sent as the master clock transmission board of slave board according to the mainboard of reception
Signal, to calculate relative time, and legal relative time initial value is calculated before the arriving of next pps pulse per second signal.When
Next pps pulse per second signal temporarily, System Frame Number to be calculated according to relative time initial value.Above-mentioned processing procedure realizes standby
Calibration of the plate to System Frame Number so that the System Frame Number that the master clock transmission board as slave board generates and the master control as mainboard
The System Frame Number of clock transfer plate generation keeps matching.
The embodiment of the invention discloses a kind of device for generating System Frame Number, applied to master clock transmission board, the master
Control clock transfer plate is connected with external reference clock source and synchronisation source, and shown in Figure 5, the device includes：
First computing unit 501, for the external reference clock source signals according to reception, absolute time is calculated；
Second computing unit 502, for according to the absolute time, relative time to be calculated；
Modulo operation unit 503, for by the relative time, with the System Frame Number cycle progress modulo operation of setting
Reason, obtains System Frame Number.
Specifically, in the present embodiment unit specific works content, refer to the content of said system embodiment, this
Place repeats no more.
Optionally, in another embodiment of the present invention, the device also includes：
Signal receiving unit, the pps pulse per second signal sent for receiving the synchronisation source；
First computing unit, it is additionally operable to when the pps pulse per second signal interrupts, according to the external reference clock of reception
Source signal, absolute time is calculated；
Second computing unit, it is additionally operable to, according to the absolute time, relative time be calculated；When will be described relative
Between, plus the Timing Advance of setting, obtain relative time initial value；
The modulo operation unit, it is additionally operable to when the pps pulse per second signal arrives again, by the relative time initial value,
Modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
The embodiment of the invention also discloses the device of another generation System Frame Number, applied to master clock transmission board, institute
State master clock transmission board to be connected with other master clock transmission boards as mainboard, shown in Figure 6, the device includes：
Time receiving unit 601, when the pps pulse per second signal for being sent when mainboard interrupts, receive the absolute time that mainboard is sent
Between signal, and according to the absolute time signal, confirm absolute time；
3rd computing unit 602, for according to the absolute time, relative time to be calculated；
4th computing unit 603, for by the relative time, plus the Timing Advance of setting, obtaining relative time
Initial value；
Operation processing unit 604, for when the pps pulse per second signal arrives again, by the relative time initial value, with
The System Frame Number cycle of setting carries out modulo operation processing, obtains System Frame Number.
Specifically, in the present embodiment unit specific works content, refer to the content of said system embodiment, this
Place repeats no more.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (11)
- A kind of 1. master clock system, it is characterised in that including：The the first master clock transmission board and the second master clock transmission board run simultaneously with active/standby mode；During first master control Clock transmission board connects identical external reference clock source with the second master clock transmission board；When the first master clock transmission board or the second master clock transmission board are as mainboard, it is specifically used for：According to the external reference clock source signals of reception, clock signal and System Frame Number are generated；Pps pulse per second signal is sent to slave board And absolute time signal；When the first master clock transmission board or the second master clock transmission board are as slave board, it is specifically used for：According to the external reference clock source signals of reception, or the pps pulse per second signal and absolute time signal that mainboard is sent, generation with Clock signal of the clock signal of the mainboard generation with frequency with phase, and generation are identical with the System Frame Number of mainboard generation System Frame Number.
- 2. system according to claim 1, it is characterised in that the first master clock transmission board or second master control Clock transfer plate when generating System Frame Number, is specifically used for according to the external reference clock source signals of reception：According to the external reference clock source signals of reception, absolute time is calculated；According to the absolute time, relative time is calculated；By the relative time, modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
- 3. system according to claim 2, it is characterised in that the first master clock transmission board and second master control Clock transfer plate connects identical synchronisation source；When the first master clock transmission board or the second master clock transmission board are made For mainboard when, be additionally operable to：Receive the pps pulse per second signal that the synchronisation source is sent；When the pps pulse per second signal interrupts, according to the external reference clock source signals of reception, absolute time is calculated；According to the absolute time, relative time is calculated；By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；When the pps pulse per second signal arrives again, the relative time initial value is taken with the System Frame Number cycle of setting Modular arithmetic is handled, and obtains System Frame Number.
- 4. system according to claim 1, it is characterised in that the first master clock transmission board or second master control The pps pulse per second signal and absolute time signal that clock transfer plate is sent according to mainboard, the System Frame Number of generation and mainboard generation During identical System Frame Number, it is specifically used for：When the pps pulse per second signal that mainboard is sent interrupts, the absolute time signal that mainboard is sent is received, and according to the absolute time Between signal, confirm absolute time；According to the absolute time, relative time is calculated；By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；When the pps pulse per second signal arrives again, the relative time initial value is taken with the System Frame Number cycle of setting Modular arithmetic is handled, and obtains System Frame Number.
- 5. according to the method for claim 1, it is characterised in that the first master clock transmission board and second master control When clock transfer plate works on power at the same time, mainboard and slave board are distinguished by main and standby competition.
- A kind of 6. method for generating System Frame Number, it is characterised in that applied to master clock transmission board, the master clock transmission Plate is connected with external reference clock source and synchronisation source, and this method includes：According to the external reference clock source signals of reception, absolute time is calculated；According to the absolute time, relative time is calculated；By the relative time, modulo operation processing is carried out with the System Frame Number cycle of setting, obtains System Frame Number.
- 7. according to the method for claim 6, it is characterised in that this method also includes：Receive the pps pulse per second signal that the synchronisation source is sent；When the pps pulse per second signal interrupts, according to the external reference clock source signals of reception, absolute time is calculated；According to the absolute time, relative time is calculated；By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；When the pps pulse per second signal arrives again, the relative time initial value is taken with the System Frame Number cycle of setting Modular arithmetic is handled, and obtains System Frame Number.
- A kind of 8. method for generating System Frame Number, it is characterised in that applied to master clock transmission board, the master clock transmission Plate is connected with other master clock transmission boards as mainboard, and this method includes：When the pps pulse per second signal that mainboard is sent interrupts, the absolute time signal that mainboard is sent is received, and according to the absolute time Between signal, confirm absolute time；According to the absolute time, relative time is calculated；By the relative time, plus the Timing Advance of setting, relative time initial value is obtained；When the pps pulse per second signal arrives again, the relative time initial value is taken with the System Frame Number cycle of setting Modular arithmetic is handled, and obtains System Frame Number.
- A kind of 9. device for generating System Frame Number, it is characterised in that applied to master clock transmission board, the master clock transmission Plate is connected with external reference clock source and synchronisation source, and the device includes：First computing unit, for the external reference clock source signals according to reception, absolute time is calculated；Second computing unit, for according to the absolute time, relative time to be calculated；Modulo operation unit, for by the relative time, carrying out modulo operation processing with the System Frame Number cycle of setting, obtaining System Frame Number.
- 10. device according to claim 9, it is characterised in that the device also includes：Signal receiving unit, the pps pulse per second signal sent for receiving the synchronisation source；First computing unit, it is additionally operable to when the pps pulse per second signal interrupts, is believed according to the external reference clock source of reception Number, absolute time is calculated；Second computing unit, it is additionally operable to, according to the absolute time, relative time be calculated；By the relative time, Plus the Timing Advance of setting, relative time initial value is obtained；The modulo operation unit, it is additionally operable to when the pps pulse per second signal arrives again, by the relative time initial value, with setting The fixed System Frame Number cycle carries out modulo operation processing, obtains System Frame Number.
- 11. a kind of device for generating System Frame Number, it is characterised in that applied to master clock transmission board, the master clock passes Input board is connected with other master clock transmission boards as mainboard, and the device includes：Time receiving unit, when the pps pulse per second signal for being sent when mainboard interrupts, the absolute time signal that mainboard is sent is received, And according to the absolute time signal, confirm absolute time；3rd computing unit, for according to the absolute time, relative time to be calculated；4th computing unit, for by the relative time, plus the Timing Advance of setting, obtaining relative time initial value；Operation processing unit, for when the pps pulse per second signal arrives again, by the relative time initial value, it is with setting The system frame number cycle carries out modulo operation processing, obtains System Frame Number.
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| CN201710652739.4A CN107396326A (en) | 2017-08-02 | 2017-08-02 | A kind of method and master clock system for generating System Frame Number |
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| CN201710652739.4A CN107396326A (en) | 2017-08-02 | 2017-08-02 | A kind of method and master clock system for generating System Frame Number |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110554731A (en) * | 2019-08-12 | 2019-12-10 | 深圳震有科技股份有限公司 | Clock synchronization control method, intelligent terminal and storage medium |
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