CN1155359A - Apparatus and method for clock alignment and switching - Google Patents

Abstract

In a telecommunication system (figure 1) having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals (CLOCK A and CLOCK B) and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals (CLOCK A and CLOCK B) and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path (DELAY PATH A) having a programmable delay value, which delays it and produces a first output timing signal. A second delay path (DELAY PATH B) receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of the phase relationship therebetween.

Description

Clock alignment and device for switching and method

The technical background of invention

The present invention generally speaking relates to the timing circuit field.Or rather, the present invention relates to clock alignment and device for switching and method.

Background of invention

In synchronous circuit was used, clock signal was extremely important.Particularly, telecommunication switching system needs reliable timing signal, with the digital data signal of true(-)running and zero defect transmission.For fear of the caused fault of mistake, and, can provide redundant timing signal for the ease of system fault diagnosis and test because of loss of clock and LOF and so on.Adopt redundant timing signal, system can detect existing when error state being arranged with timing signal, with the operation of backup timing signal.The all right manual switching timing of technical staff is so that carry out system diagnostics, maintenance and/or repairing.In the telecommunication system that transmits high-speed data, even an error code also is unallowable.Can to see, to switch to other clock signals in order showing from one with clock signal, clock signal must be synchronous fully on frequency and phase place, to avoid producing error code in the data transmission.

Therefore, make circuit between two or more timing signals, carry out accurate phase alignment and the needs of switching increase day by day.Influence of temperature variation when in addition, the also necessary compensating circuit of sort circuit moves.

Summary of the invention

According to clock alignment provided by the invention and device for switching and method, eliminate or reduced substantially not possess the shortcoming of the system of this ability.

One aspect of the present invention is, circuit comprises that a reference clock selects and commutation circuit, is used for a redundant timing signal is appointed as used, and other redundant timing signals are inactive in addition.Respectively will be now with timing signal and non-existing with timing signal offer made timing signal for generating can be by first delay path of the retardation of program setting.One phase detectors are connected with second delay path with first delay path, receive delay existing usefulness and non-existing with the output timing signal, and produce and represent the status signal of phase relation therebetween.Controller is connected with phase detectors, is used for controlling the length of delay of first delay path and second delay path, thereby carries out the phase alignment of timing signal according to status signal.

Another aspect of the present invention is that telecommunication system can have a plurality of timing subsystems that receive and distribute redundant timing signal.The circuit that provides is breaking down or when receiving instruction, redundant timing signal is being calibrated, and switched between redundant timing signal.This timing signal calibration and commutation circuit comprise that one selects and commutation circuit, be used for receiving the first and second redundant timing signals, and one in the redundant timing signal is appointed as used, and other signals are inactive, and provide existing with timing signal as the output timing reference signal.Select and commutation circuit also according to detection failure or clock switching command, switch existing with the non-timing mark signal of now using, and export timing reference signal.Offer with timing signal with existing that have can be by first delay path of program setting length of delay, this delay path now postpones this with timing signal, and produces the first output timing signal.The reception of second delay path is non-now uses redundant timing signal, and produces the second output timing signal.This circuit also comprise receive non-existing with and existing with the output timing signal, and produce phase detectors of the status signal of phase relation between these two signals of expression.This circuit also provides the temperature-compensating of the surveyed influence of variations in temperature on measurement and the compensating delay path.

Another aspect of the present invention is, the method of calibrating between the first and second redundant timing signals and switching comprises that a conduct of at first selecting in first and second timing signals now uses timing signal, and another is as the non-timing signal of now using, and provides the existing timing signal of using as the output timing base.Secondly, its detect existing with and the non-phase relation of now using between the timing signal, and increase progressively the non-time delay of now using timing signal, up to non-now with timing signal on the phase place with now align with timing signal till.This circuit is also according to mistake and a certain clock switching command now used in the timing signal, switch existing with and the non-timing signal of now using, and export timing reference signal.

The accompanying drawing summary

With reference to accompanying drawing, the present invention may be better understood.Wherein,

Fig. 1 is the simplified block diagram that timing signal distributes in the comprehensive cross connect switching system;

Fig. 2 is higher level's block diagram of an embodiment of the present invention;

Fig. 3 is existing block diagram with clock multiplexer and master phase detector;

Fig. 4 is the block diagram of an embodiment of delay path;

Fig. 5 is the more more detailed block diagram of an embodiment of coarse delay level;

Fig. 6 is the more more detailed block diagram of an embodiment of middle delay-level;

Fig. 7 is the more more detailed block diagram of an embodiment of thin delay-level;

Fig. 8 is the simplified block diagram of an embodiment of temperature-compensation circuit;

Fig. 9 is the more more detailed block diagram of an embodiment of temperature-compensation circuit;

Figure 10 is higher level's simplified flow chart of an embodiment of clock alignment process;

Figure 11 A and 11B are the flow charts that the non-usefulness of clock alignment circuit is decided the embodiment of main portion operation;

Figure 12 is the non-existing flow chart that partly moves embodiment with subordinate of clock alignment circuit;

Figure 13 is that the clock alignment circuit is now with the flow chart of part around operation embodiment;

Figure 14 is the flow chart of temperature-compensating process embodiment;

Figure 15 be temperature-compensation circuit clock cycle measuring process embodiment flow chart;

Figure 16 is the flow chart of thick-thin retardation ratio measuring process embodiment;

Figure 17 is the simplified block diagram of another embodiment of clock alignment circuit;

Figure 18 is the block diagram of phase detectors embodiment;

Figure 19 is the block diagram of the Phase Processing device embodiment of phase detectors;

Figure 20 is the flow chart of function of temperature compensation control process embodiment;

Figure 21 is the flow chart of temperature sensing process embodiment;

Figure 22 is the flow chart of temperature than computational process embodiment.

The detailed description of invention

By 1-20 with reference to the accompanying drawings, will make the reader understand preferred embodiment of the present invention and advantage thereof better, among each figure, identical label is used for the identical and corresponding parts of mark.

Referring to Fig. 1, the comprehensive multimachine structure digital cross-connection system shown in the figure has been described the possible running environment of the present invention.Two or more reference clock signals 12 are offered regularly subsystem 14-18 of broadband, wideband and arrowband.The reference clock signal 12 that can comprise clock and frame information has amount of redundancy, and a signal is staggered the time and can be switched mutually.In telecommunication environment, very important by system integrity and reliability that this amount of redundancy provides.As shown in the figure, redundant reference clock 12 can be drawn by the signal that receives from network, produce the DS1 signal such as low speed unit 30 from DS1 selection at interval, perhaps high-speed cells frame 32 selects to produce DS1 and E1 signal from the light signal (as OC-3 or OC-12 signal) that receives.Reference signal 12 also can the source for the regularly supply arrangement (BITS) of playing a game.

Each is subsystem 14-18 reception redundant reference clock regularly, selects a conduct now to use clock signal, and according to the existing clock generating timing signal of selecting of using.The timing signal of drawing is distributed to interconnection array 20-24 by level subsequently.If now cause some mistake, can carry out switching to another timing reference signal so with clock signal.Because system maintenance, diagnosis and repairing also can switching timings.Mistake in the transfer of data, two phase-locked reference clock signals are enough to calibration, thereby the timing signal of being arranged switches in the phase distortion that produces in the final clock output less than predetermined value.For comprehensive multimachine structure interconnection environment, target is the phase distortion that produces less than 1 nanosecond.

Referring to Fig. 2, reference clock 12 (hereinafter being called clock A and clock B) is received by clock alignment circuit 40, shows with clock signal selection, internal clock signal calibration and show to switch with clock signal.Clock alignment circuit 40 comprises existing with clock selection circuit 42, and it determines which reference clock signal is existing with clock signal (or now using clock), and which signal is non-signal (or the non-clock of the now using) signal of now using.Can lose damage (LOC), frame by the estimation clock loses other corresponding states or the situation of damage (LOF) and timing signal and selects.If current is existing with clock generation LOC or LOF situation, other reference clock (if zero defect) just is selected as new showing clock signal so.LOC and LOF situation can be judged by circuit well known in the art or other devices.Can also now use clock selecting according to some other situation of not describing herein.Another kind method is can be by now with the control signal input of clock selection circuit 42, and for example clock selection signal is initialized as default selection when manually being provided with now with clock selecting or switch power supply.

Clock alignment circuit 40 also comprises clock alignment control circuit 44, the operation of its difference control lag path A and delay path B (46 and 48).But adopt the delay path A or the B of program setting, make non-clock delay one amount of calculation of now using, thereby realize consistent with the phase place of now using clock in a nanosecond.Now use clock multiplexer and phase detector circuit 50 to provide control signal, to change caused retardation to delay path A and B (46 and 48).Control signal can comprise lifting/lowering instruction, renewal and phase locking status signal.All can influence the retardation of introducing by each delay element in delay path A and B 46 and 48 because process, temperature and voltage (abbreviating PTV as) change, change so also provide a compensating circuit 52 to be used for these PTV.Because temperature is the principal element that influences these variations, compensating circuit 52 is called temperature-compensation circuit 52 herein.

Referring to Fig. 3, there is shown existing more more detailed block diagram with clock multiplexer and phase detector circuit 50.The output that multiplexer 100 receives from delay path A and delay path B, and now using under the clock selecting signal controlling with the existing of clock selection circuit 42, select one of them as now using clock.Should existing be subordinate to delay path with preferable length of delay with clock.The identical output of self-dalay path A and B in the future offers master phase detector 102, and decision is now with clock and the non-phase relation of now using between the clock.The phase relation that depends on detection, master phase detector 102 produces lifting/lowering A, lifting/lowering B or phase locking status signal.The lifting/lowering signal now is used for increasing or reducing the propagation delay in this path with delay path by accordingly non-, and makes reference clock can not be locked in the phase differences of 180 degree.If now with clock and non-be synchronous substantially on phase place now with clock, the phase locking status signal that this is indicated so just must be arranged, thereby need not further calibration path delay.Phase detectors 102 may need " balance " state, that is, locking and not lock-out state detection from from each clock along, the time span of appearance is roughly the same.

Referring to Fig. 4, there is shown the more detailed block diagram of delay path 46 and 48.But delay path 46 and 48 delays with program setting are incorporated into existing usefulness and the non-reference clock of now using, and can be built into the continuous series of being made up of coarse delay level 110, middle delay-level 112 and thin delay-level 114.As by title meaned, delay-level 110-114 is built into and the various resolution of propagation delay value can be incorporated into the delay element that goes in the path of reference clock.For example, coarse delay level 110 can comprise a string 22 delay element,, each delay element can be according to process, temperature and voltage (PTV) situation, and the delay of 10-29 nanosecond is incorporated into delay path; Middle delay-level 112 can comprise 15 delay elements, and each element has 1.4 nanoseconds delay under typical PTV situation; Thin delay-level 114 can comprise 128 delay elements, and each element has 0.2 nanosecond delay under typical PTV situation.For the unlimited meticulous operational mode that hereinafter will describe, total thin retardation can be bigger than a coarse delay.

As shown in Figure 4, coarse delay level 110 produces the output X and the Y of two delays, and here, output X links to each other with the clock input of middle delay-level 112, and output Y links to each other with a clock input of thin delay-level 114.The second clock of thin delay-level 114 is imported therefrom delay-level 112 receive clocks output.Therefore, form two parallel delay lines: one by carse, medium and small delay-level 110-114, and another is only by coarse delay level 110 and delay-level 114 carefully.These two lines are referred to as the main path part in this article and from the path part, main path is partly represented the non-delay path institute's band signal of usefulness now and showed with the consistent path of the signal on the delay path here.Represent the consistent path of signal on institute's band signal and the main path part from the path part.As hereinafter will be more Verbose Mode, main delay line and can be used for compensating the unlimited delay scope that is essentially from delay line.

As shown in Figure 4, thin delay-level 114 also receives preferable tap registers value, existing with clock sign and master phase detector state.When non-now with clock when now using clock consistent, preferable tap registers contains and is useful on existing fixed reference length of delay with clock.Preferable retardation provides permanent datum, makes phase drift minimum when switching between two clock references.When switching clock, preferable values of tap is got back in current existing delay drift with clock (before being non-current clock), and current non-now follow the tracks of and aligning with it with clock.Preferable retardation can be in the delay scope center of delay path or closely this center certain a bit.From now notifying each delay path with the existing of clock with the clock sign, whether it has been chosen as is now used the path.Master phase detector state signal can comprise the signals such as renewal, lifting/lowering and locking from 102 outputs of master phase detector.Then, thin delay-level 114 produces several delayed control signals, and these signals are offered coarse delay level 110 and middle delay-level 112.Thin delay-level 114 is the final delay amount in output delay path also.

Referring to Fig. 5, there is shown the more more detailed block diagram of coarse delay level 110.Coarse delay level 110 comprises the array of the coarse delay element 120-126 of tap, and these elements are connected with 132 with two output multiplexers 130 respectively, and delayed clock X and Y is provided.As hereinafter inciting somebody to action in greater detail, X and Y output are controlled, and as main delay line with from delay line.Main delay line and make clock alignment circuit 40 alternately have the ability of compensation infinite delay scope from the use of delay line.Particularly under thin delay resolution, coarse delay controller 134 is from now with clock selection circuit 42, now receive control signals, control output multiplexer 130 and 132 with clock multiplexer and phase detector circuit 50 and from thin delay-level 114.In addition, coarse delay controller 134 produces a thick lock-out state, and indication has realized the phase locking between clock signal on the coarse delay level.

Referring to Fig. 6, the simplified block diagram of delay-level 112 in there is shown.Middle delay-level 112 comprises the array of delay element 140-146 in, and these elements are from coarse delay level 110 receive delay clock X, and its tap output links to each other with output multiplexer 148.The multiplexed tap of delay element 140-146 is selected in middle delay controller 150 controls.Middle delay controller 150 is also from now using clock selection circuit 42, now using clock multiplexer and phase detector circuit 50 and thin delay-level 114 to receive control signals.The lock-out state signal is indicated the phase place unanimity on middle delay level as output in providing.

Illustrated among Fig. 7 and had the thin delay-level 114 more complicated than coarse delay level 110 and middle delay-level 112.Thin delay-level 114 comprises respectively to be exported from the delayed clock of coarse delay level 110 and middle delay-level 112.By switch 168, will be from the control signal of local phase detectors 166 or master phase detector 102: phase locking and lifting/lowering signal offer thin delay element piece 160 and 162.Switch 168 is subjected to the control of master/slave thin delay selection signal, and this signal is also controlled the output multiplexer 164 of output delay master clock.

Fig. 8 is the functional-block diagram of temperature-compensation circuit 52.There is the multiplexer 190 of three inputs from clock A, clock B and an external reference source, to select clock reference, as temperature-compensating.The output of multiplexer 190 is offered coarse delay level 192, and the output of this grade offers a clock input of local phase detectors 198.The output that further output of multiplexer 190 is offered the second coarse delay level, 194, the second coarse delay levels 194 offers thin delay-level 196.The output of thin delay-level 196 is imported as second clock, offers local phase detectors 198.So, produce two delay paths, one comprises coarse delay level 192, and another comprises coarse delay level 194 and thin delay-level 196.Local phase detectors 198 comprise the phase locking status signal, and as lifting/lowering and phase-locked signal, these signals offer microprocessor 200, as storage and/or calculating.

Referring to Fig. 9, illustrate in greater detail temperature-compensation circuit 52 among the figure.Delay element 202-208 array links to each other with the second output multiplexer 212 with the first output multiplexer 210.The output of first multiplexer 210 links to each other with first input of local phase detectors 198, and the output of second multiplexer 212 links to each other with second input of phase detectors 198, forms two delay paths.Thin delay-level 196 also comprises a delay element array (not shown), to link to each other with the similar mode of the middle delay-level 112 of Fig. 6.The output of local phase detectors 198 is provided to a microprocessor (Fig. 8), is used for control and calculates purpose.

Referring to Figure 10, the flow chart 300 of simplification provides basic clock alignment logic and program.After rising power supply or resetting, shown in square frame 302, check the state of clock A.If clock A is a zero defect, then its corresponding delay path, i.e. delay path A, be considered to used, and shown in square frame 306 and 308 like that, existing by appropriate selection signal is offered with clock multiplexer 100 (Fig. 3), thus it is exported as now using clock.Therefore, the delay path that program setting is same is introduced predetermined delay amount.Shown in square frame 310 like that, predetermined delay amount can be to be stored in register, the preferable setting in the promptly preferable tap registers (PTR).When carrying out two switchings between the clock reference, preferable retardation provides a fixing reference point, makes the phase drift minimum.The preferable retardation of thin delay-level can be carefully postpone the scope center or closely this center certain a bit, and the preferable retardation of coarse delay level is near the minimum value of this scope.Therefore now obtain the length of delay that PTR deposits with delay path, but not now use delay path (being delay path B in this example) be configured to make non-now with clock with now use clock consistent.

Shown in square frame 312 and 316, calibration process adopts the control signal from master phase detector 102, comes the calibration delay value, on the non-clock of usefulness is now being showed with clock by phase locking.Can change up to phase relation by increasing progressively the non-retardation of now using in the delay path, retardation is return once increase progressively.The variation of phase relation can be to be related to the lagging phase relation from leading phase.By the calibration delay amount, up to an initial phase lock, and continue to carry out phase alignment along identical direction, inconsistent once more up to clock signal, realize the thin calibration that postpones.Subsequently, the length of delay in this path is defined as mean value between locking delayed value and the non-locking length of delay.Should carry out this thin calibration operation that postpones with " balance " phase detectors.More accurate phase alignment is provided, the delay path with various resolution delay elements preferably is provided, be here with the mode of the resolution of refinement progressively the calibration reference clock realize calibrating.Simultaneously, shown in square frame 314 and 318, the existing of reference clock checked with state, whether necessary to determine that clock reference switches.When a timing signal causes error situation, perhaps this switches and carries out system diagnostics, maintenance and/or when repairing, carry out benchmark and switch when needs.

If as square frame 304 was judged, clock A was not free from mistakes at the beginning, if perhaps as square frame 314 and 318 are judged, variation has taken place with state in the existing of reference clock, and clock B becomes and now uses clock so.Shown in square frame 322-326 like that, then select delay path B, and be labeled as the existing path of use, select to export the output of clock, and delay path B be set at length of delay in the preferable tap registers (PTR) as delay path B.Shown in square frame 328 and 332, clock A (being the non-reference clock of now using now) needs to follow the tracks of and be locked on the phase place of clock B.Shown in square frame 330 and 334,, also check showing of reference clock to use state at this run duration.

It is further noted that shown in square frame 310 and 326 after will now being set at preferable values of tap with delay path, non-now the tracking with the propagation delay of delay path now used clock, and aims at it.In order to realize phase locking, progressively start delay level 110-114 (Fig. 4) is output as phase locking up to two delay paths from coarse to fine.Also can adopt selected delay-level (such as only being coarse delay level and thin delay-level 110 and 114) to realize phase alignment.

As shown in Figure 4, in delay circuit 46 and 48, provide master delay path and from delay path.What Figure 11 A and 11B described is non-resetting and path calibration operation 350 with main path part in the delay path now.As top the summary, non-showing with the clock signal on the delay path with existing consistent with the clock signal on the delay path.Particularly, non-now with the clock signal on the delay path main portion with existing consistent with the signal on the delay path, but not existing with following the tracks of signal on the main path from part on the path, and aligning with it.Using to phase alignment of master and slave path part provides the unlimited delay scope that is essentially.

In the square frame 352, the length of delay initialization of the middle storage of register (not shown) that the coarse delay level 110 of main path and thin delay-level 114 usefulness are appropriate.Shown in square frame 354, start coarse delay controller 134 (Fig. 5).Shown in square frame 356, check output (Fig. 3) from master phase detector (MPD) 102, see whether there is the lagging phase relation between two phase signals.If exist, shown in square frame 358, coarse delay value is added 1, become next coarse delay coarse delay value.Coarse delay in the repetition square frame 356 in phase relation status checkout and the square frame 358 increases progressively, and now uses clock signal up to non-existing no longer lagging behind with clock signal.Subsequently, shown in square frame 360, check 102 outputs of master phase detector, see non-ly now whether now use clock signal now in advance with clock signal.The variation of phase relation shown in the delay among Fig. 4 control like that, use to export and represent from reach/falling of thin delay-level 114.

Shown in square frame 362,, so just increase coarse delay if non-showing now used clock in advance with clock signal.Shown in square frame 364, increase progressively coarse delay, now now use clock signal no longer in advance up to non-with clock signal, at this moment, coarse delay subtracts 1.In fact these steps have postponed the non-edge of now using clock, intersect with now using the clock edges of signals up to it.Step 364 is return the non-clock edge of now using, and is non-existing with before the clock edge thereby this edge directly appears at, and here, the increase meeting of fine delay makes with meticulousr resolution and non-ly now uses the clock marginal delay, thereby calibrates two clock edges more accurately.

In square frame 366 and 368, start the thin delay controller 160 or 162 (Fig. 7) of main path part, and the output (Fig. 3) of check master phase detector 102, judges non-now whether phase place is consistent with delay path and the main path of now the using delay path signal on partly.If clock is consistent, then continue the output of check master phase detector 102, no longer consistent up to clock, at this moment, in square frame 370, determine the phase relation between the clock.If non-showing or not do not used clock edge in advance with clock edge, then should reduce the non-length of delay of now using delay path.So, shown in square frame 372 and 374 like that, judge also do not reach minimum thin length of delay after, length of delay successively decreases.If reached minimum thin length of delay, then set MINTAP (minimum tap) variable, indicate this state.

If in square frame 370, judge and non-ly now now use the clock edge in advance with the clock edge, so non-ly now need more the delay with the path.Shown in square frame 378 and 380, when also not reaching maximum thin length of delay, the incremental delay value.If reached maximum thin the delay, then shown in square frame 382, set MAXTAP (maximum tap) variable.At last, the major state in check path.If state variable also is set, carry out loop so and turn back to square frame 368, whether the check phase place is consistent, carries out non-existing usefulness/subordinate phase alignment algorithm otherwise change, and its flow process is seen shown in Figure 12.

Referring to Figure 12, there is shown non-existing with the control and the logic flow 400 of delay path from the path part.Non-now with being controlled usually of delay path from the path part, thus the main portion of delay path followed, and aim at it.In the square frame 402, the length of delay that usefulness is deposited makes thick, thin delay-level 110 and 114 initialization from the path part.Subsequently shown in square frame 404, coarse delay value set for the coarse delay value of main path part equate.Then, judge whether be provided with master control MINTAP or MAXTAP state variable in square frame 406, these two variablees represent that the thin delay-level of main path is arranged on minimum delay value or maximum delay value.If the two is not all set, then carry out loop and get back to square frame 404.Otherwise, shown in square frame 408 like that, increase progressively coarse delay value when being provided with MAXTAP, length of delay successively decreases when perhaps being provided with MINTAP.

Subsequently, shown in square frame 410, start thin delay controller 160 or 162, begin to calibrate from the path.Then, shown in square frame 412 like that, whether check is judged consistent with the main path signal from path signal from the state output of local phase detectors (LPD) 166.If clock is inconsistent, then shown in square frame 414, judge the phase relation between the clock.If from path signal hysteresis main path signal, then as shown in square frame 416, thin length of delay successively decreases.Otherwise, if, then shown in square frame 418, increase progressively thin length of delay from the leading main path signal of path signal.Calibrate thin length of delay by this way, till in square frame 412, determining the clock edges unanimity, at this moment carry out and enter square frame 420, the master and slave state of check path part.If the slave mode in path is constant, then carry out loop and get back to square frame 412, otherwise the path part just becomes the main path part.

Referring to Figure 13, there is shown a flow process of upgrading preferable tap registers (PTR) 450 algorithms.When ruuning situation has changed the delay feature of delay path, such as when influence of temperature change during effective delay of delay path, can upgrade or change preferable tap and deposit length of delay.At square frame 452, whether judgement now reaches its maximum or minimum with the thin delay of master control of delay path.If the thin delay of master control is not maximum or minimum, but equal the value of preferable tap registers, shown in square frame 454 and 456, do not need to operate again so.If master control postpones not to be in the value of preferable tap registers, then shown in square frame 458, calibration is thin to be postponed realizing unanimity, and carries out loop and get back to square frame 452.If it is maximum or minimum that the thin delay of master control has reached, then shown in square frame 460, check master control coarse delay judges that whether it is for maximum or minimum.If reached maximum or minimum, the subordinate coarse delay is set for equaled predetermined tap position so.Shown in square frame 462, coarse delay is set for a certain value that equals the middle place of coarse delay scope.The master control coarse delay is not in maximum or minimum then as square frame 464, carefully increases progressively the subordinate coarse delay when postponing to be in maximum down, and perhaps thin delay is in the subordinate coarse delay of hour successively decreasing.

In the square frame 466, the centre tap position is also set in the thin delay of subordinate for.In square frame 468, judge whether slave clock is consistent with master clock subsequently.If inconsistent, then shown in square frame 470 and 472, subordinate is thin to postpone to be in maximum or hour, subordinate coarse delay value increasing or decreasing.If thin the delay is in maximum, then increase progressively the subordinate coarse delay.Otherwise, if carefully postpone in minimum the subordinate of then successively decreasing coarse delay.If judge that in square frame 470 subordinate carefully postpones neither in minimum, also not in maximum, NO WRAP (acyclic around) variable is set then, and exports according to the lock-out state of the local phase detectors 166 of thin delay, the increasing or decreasing subordinate carefully postpones, realization phase locking.Repeat the step among the square frame 470-474, consistent up to the clock signal on the part of path with the signal on the main path part.At this moment,, then shown in square frame 478-482, read, and this value is written in the preferable tap registers from the value in path delay if as judging in the square frame 476, NO WRAP variable is set, and the NO WRAP variable that resets.In the square frame 484, then switch main path part and from the path part, promptly once for from the path part be the main path part now, and once be that main path part is from the path part now.Algorithm operating finishes in square frame 486.

Operation like this can be essentially unlimited retardation and be used for existing coming the variation of compensate for propagation delay with clock path, and non-existing have with clock path be essentially unlimited delay scope, follow the tracks of and now use clock.Note the master control coarse delay and carefully postpone to reach maximum or hour, subordinate coarse delay and thin the delay are set in the centre of its scope, thereby can determine the new clock signal edge that is used for phase alignment.In case realized phase locking, then switch master and slave path, thereby main path no longer is in its maximum or minimum delay.

As mentioned above, can upgrade preferable tap register value, to compensate the variation that postpones feature in the delay path that causes owing to process, temperature and change in voltage.In general, when temperature rose, the value of effective delay of delay element also rose in the delay path.Equally, when temperature descended, the value of effective delay of delay element also descended.Particularly like this for cmos device.What Figure 14 described is the highest flow chart of temperature-compensating 500.Shown in square frame 502,, carry out temperature-compensating by at first measuring a clock cycle with regard to delay element in the temperature-compensation circuit delay path.This measurement can carried out aspect coarse delay resolution and the thin delay resolution.Secondly, shown in square frame 504, determine the thin delay number of each coarse delay.By these two kinds of measurements, shown in square frame 506 and following equation, can then determine the thin delay number of each clock cycle:

Subsequently, shown in square frame 508, this temperature survey and previous same measurement are compared.This relatively can obtain to represent the ratio of each thin delay element relative delay variation:

If the relative delay changes greater than 1, then need more delay element, make reference clock postpone one-period than in the past.This expression is owing to change, and the delay of each thin delay element reduces.On the other hand, if this ratio less than 1, then makes reference clock postpone one-period than in the past with the minimizing delay element, this represents the increase of the delay of each delay element.Shown in square frame 510, adopt this information, can calibrate preferable tap setting, to compensate this variation:

=new PTR

Equation (3) can get the preferable tap registers value under the carefully delay situation, and this can easily become the preferable tap registers value of coarse delay and thin delay with the thin delay number conversion of each coarse delay value.In the square frame 512, before the repeated temperature compensation, there is the predetermined stand-by period of a length.Under typical service conditions and variations in temperature, the stand-by period that is about one minute is appropriate.

Also continue to have described among the figure with temperature-compensation circuit 52 and measured the step of a clock cycle now using clock referring to Figure 15 referring to Fig. 9.In the square frame 520, coarse delay multiplexer 210 is set, makes the composite signal that wherein produces can not cause delay.It is zero that this step makes the retardation in the delay path that only has coarse delay level 192 effectively,, this delay path is referred to as first delay path herein.Subsequently, calibration is at first sought the clock signal edge by the delay in second delay path of coarse delay level 194, realizes calibration then.In the square frame 522, check the phase locking state output of local temperature phase detectors (TPD) 198, judge second path signal, first path signal that whether lags behind.If just shown in square frame 524, increase progressively the second path coarse delay.Increase progressively the second path coarse delay by this way, up to second path signal, first path signal that no longer lags behind.If shown in square frame 526 like that, leading first path signal of present second path signal then still increases progressively the second path coarse delay, up to its no longer leading first path signal.At this moment, two clock signals are in the coarse delay, and phase place is inconsistent.Subsequently, shown in square frame 530 like that, make the coarse delay in second path subtract 1, make clock signal along being in the first path clock signal along the front.Can add thin delay now, to realize the phase alignment unanimity.

Shown in square frame 532, check local temperature phase detectors 532 outputs, judge and whether realized phase locking.If the phase place of signal is inconsistent, then shown in square frame 534-538 like that, according to the phase relation between first path signal and second path signal, increasing or decreasing second path carefully postpones.Calibrate thin delay element by this way, find phase place unanimity between the binary signal up to square frame 532.Subsequently, shown in square frame 540, storage representative makes thick, the thin length of delay in second path of required retardation of delayed reference clock clock cycle.

Figure 16 describes thick-thin flow chart than measurement 504.Shown in square frame 552 and 554 like that, coarse delay multiplexer 212 is set to length of delay M, and coarse delay multiplexer 210 is set to length of delay M+1 (referring to Fig. 9).So coarse delay 192 is littler by 1 than coarse delay 194.Then, shown in square frame 556-560 like that, will carefully postpone 196 and be initialized as zero, and increase progressively coarse delay 196, phase place unanimity between first path signal and second path signal.After realizing the phase place unanimity, the thin number that postpones of thin length of delay representative of thin delay-level 196 equals a coarse delay.Shown in square frame 562, this value is stored as the conversion factor that temperature delay calculates.Computing finishes at square frame 564.

Figure 17 has the clock alignment of PTV compensation and another preferred embodiment of commutation circuit 600.Redundant reference clock A and B are received by source of delay multiplexer 602 and 604, are used for reference clock is assigned to the first delay path A 610 and the second delay path B 612.As described above, each delay path A 610 can comprise thick continuously, the thin delay-level 614-624 of neutralization that different delay increments are provided with B 612.With the output of delay path A 610 and B 612, promptly internal reference A and internal reference B offer each phase detectors A 630 and B 632.Also internal reference A and internal reference B are offered an output multiplexer 634, this multiplexer of may command selects now to use clock signal from reference clock A and clock B and internal reference A and internal reference B.Output multiplexer 634 is subjected to face to select the control of circuit 640, and this circuit selects a conduct now to use the reference clock signal of clock (delay or do not postpone).Preferable tap registers 644 is connected with 624 with thin delay-level 618, produces preferable retardation.

Temperature-compensation circuit 650 comprises multiplexer 652, and it is a pair of to selecting A and the B from reference clock and internal reference, is provided to temperature phase detectors 654.The output of temperature phase detectors 654 is offered multiplexer 660 and 662, and their select 654 outputs of temperature phase detectors and from the output of phase detectors 630 and 632, and are transferred to appropriate delay path A 610 and B 612, as control signal.Such structure, temperature-compensation circuit 650 do not need special-purpose delay path to carry out various measurements, and adopt non-showing among delay path A 610 and the B 612 to realize this purpose with delay path.The control of multiplexer 602,604,652,660 and 662 controlled devices 670, this controller can receive control signal and status signal from microprocessor 672 by bus 674.

After the system reset, make delay path A 610 be initialized as identical predetermined amount of delay with B 612.Coarse delay level 614 and 620 can be set to zero, and middle delay-level and thin delay-level 616,618,622 and 624 can all be set to the mid point of each self-dalay scope.Select clock A and clock B respectively, and be fed to delay path A and B by multiplexer 602 and 604.Can clock A be chosen as the existing clock of using with default mode, also can under amiss situation, make face select circuit 640 to select the zero defect reference clock, as now using clock.

For the ease of discussing, suppose that clock A is for using clock by showing of delay path A 610.Clock B is by delay path B 612.Phase detectors B 632 detects the phase relation of now using between clock and the internal reference B, thereby can produce the phase alignment status signal, comes the retardation of each grade among the B 612 of control lag path.Operation by this way, internal reference B follows the tracks of and now uses clock, and aims at it.

If face is selected calibration of circuit 640 telltable clocks and commutation circuit 600 switching reference clock signals, clock B just becomes the existing clock of using so, and internal reference A and this are now used clock alignment.

Carry out the temperature-compensating process termly, influence of temperature variation when moving to detect delay path 610 and 612.As mentioned above, the non-delay circuit (being delay path B 612 in this example) of now using is temporarily borrowed from phase calibration process, as the thin delay number of measuring a clock cycle and each coarse delay.This is by selecting the output from temperature phase detectors 650 rather than phase detectors B 632, realizing as the control signal that offers delay path B 612.The measured value that obtains is subsequently as the variable that postpones in the tap setting, to compensate the above-mentioned variation that causes owing to temperature.

The chief component that the subnanosecond phase alignment that obtains requires is the realization of phase detectors 630,632 and 654.Referring to Figure 18, the six cycle phase detectors of being realized are used for judging that the inside face benchmark is with respect to the phase position of now using benchmark.Phase detectors 630,632 and 654 are lost damage (LOC) detector 674 and output processor 676 is formed by Phase Processing device 672, clock.

Each of 672 pairs of Incoming clock references of Phase Processing device is taken a sample to rising edge, and judges the inside face benchmark and now use relative phase position between the benchmark, that is, whether the inside face benchmark is ahead of or lags behind is now used benchmark.Phase detectors 672 produce the phase clock signal of absolute distance between the rising edge of rising edge that phase directional vector with encoding phase positional information and expression now use benchmark and inside face benchmark subsequently.Phase Processing device 672 will be for a more detailed description in conjunction with Figure 19 hereinafter.

Clock lose decrease detector 674 can be with being clock now and realizing by 2 bit shift register (not shown) that the phase clock signal of Phase Processing device 672 resets with benchmark.When not making the phase place of reset shift register, going into signal, move into logic level " 1 " by register.When logic level " 1 " appears at last of shift register, trigger phase clock and lose the loss state, then produce phase locking, that is, inside face with now use benchmark consistent on phase place.

Phase register output processor 676 is responsible for producing the control signal that is used for downlink delays path control circuit, specifically, is exactly lifting/lowering, renewal and phase-locked signal.The lifting/lowering signal produces according to the phase directional vector.For example, when the phase directional vector was " 10 " (the inside face benchmark is now used benchmark in advance), the lifting/lowering home position signal represented that downlink delays path control circuit should add delay in the specific part of delay line.When the phase directional vector is " 01 " (inside face benchmark lag behind now use benchmark), the lifting/lowering signal resets, and expression downlink delays path control circuit should deduct delay from the specific part of delay line.When the phase directional vector was " 00 " or " 11 ", the lifting/lowering signal kept its current state.

Renewal and phase clock signal can be produced by one six recurrent state controller (not shown).For example, during some state, produce update signal and come indicating downlink delay path control circuit, come the specific part of updating delay line according to the lifting/lowering signal.During another state, if phase clock is lost the damage situation, phase clock signal is set then, indicating downlink delay path circuit comes the Interrupt Process process, because at this moment realized phase alignment.In addition, if phase clock signal works, then cancel state machine controller (not shown) and update signal, and make them remain on its reset mode.Referring to Figure 19, direction register that phase information uses and logic " or (the OR) " door 688 that produces phase clock signal have been handled in the maintenance that Phase Processing device 672 comprises the rising edge detector 678 and 680 that is used for each timing base, handle three logics " or non-(NOR) " door 682-686 that phase information uses, be illustrated as d type flip flop 690 and 692.The reset function that " with (AND) " door 694 and NOR gate 696 are carried out rising edge detector 678 and 680.

The d type flip flop 678 and 680 input logic levels " 1 " that trigger by rising edge arrive clock end, detect the rising edge of timing base.In case detect this rising edge, then it is handled, produce phase directional information and phase clock, trigger and the storage phase information with clock.The phase information that produces and deposit represents that internal reference is in advance or lags behind and now use benchmark.If rising edge detector 678 triggered before rising edge detector 680 is in advance now with benchmark, then phase directional information representation internal reference.Identical therewith, if rising edge detector 680 triggered before rising edge detector 678, then phase directional information representation internal reference lags behind and now uses benchmark.In addition, when triggering the rising edge detector, also produce phase clock signal.

The rising edge of phase clock is to detect from the rising edge from arbitrary benchmark to obtain.The trailing edge of phase clock produces by rising edge detector 678 and 680 is resetted.Because the width of phase clock is the accurate measurement of distance in real time between each clock reference rising edge, so it is very important.When the rising edge of each clock reference became more approaching, because the propagation delay of OR-gate 688 is greater than the pulse duration of phase clock, thereby the phase clock pulse became littler, and final the disappearance.When phase clock disappeared, each clock reference was considered to homophase, that is, the propagation delay much smaller than 1 nanosecond OR-gate 688 in they and the ASIC(Application Specific Integrated Circuit) design environment is approaching.In addition, the phase clock of can fully capacitively packing into makes phase directional register 690 and 692 can deposit enough phase information establishing times definitely.

Rising edge register 678 and 680 is to be resetted by a kind of situation in following two kinds of situations: when each timing base has a kind of phase relation except that 180 degree and when they have really 180 spend phase relation the time.When having the phase relation of non-180 degree, rising edge register 678 and 680 resets when two phase all is in logic level " 1 ".When having the phase relation of 180 degree, resetting of first kind of situation is invalid, because AND gate 688 can not produce logic level " 1 ".So when having 180 degree phase relations, any in the rising edge detector 678 and 680 all resets when triggering.Be important to note that 180 degree reset signals must fully capacitively pack into, thereby can be triggered during the phase relations at non-180 degree.

Referring to Figure 20, among the figure, illustrate in greater detail the temperature-compensating process 700 of circuit 600.The temperature compensation algorithm flow process of setting up comprises initialization loop and temperature control loop road.In the square frame 702 that the initialization loop begins, judge which reference clock is chosen as now to use clock.If be clock A now, shown in square frame 704, carry out the various measurements of temperature-compensating with delay path B 612 so with clock.Otherwise,, then shown in square frame 706, measure with delay path A 610 if be clock B now with clock.Measure the time interval of now using clock according to thin delay (Current Temperatures), same, can obtain existing effective delay length according to thin delay with delay path (current length).Shown in square frame 708, keep these to measure as the original value of measuring original temperature and original length.The details of temperature sensing and will be described below as shown in figure 21.In the square frame 710, check and now use clock judge whether the reference clock switching has taken place.For example, if clock A is chosen as the existing clock of using at the beginning, and the inspection in the square frame 710 to judge existing be clock B with clock now, then reference clock switches and takes place, and the beginning of square frame 702 initialization loops is got back in execution.Otherwise algorithm flow enters the temperature control loop road.

When now not switching to other timing reference signal as yet, shown in square frame 710-714, adopt non-existing delay (current coarse delay) of measuring the clock cycle (Current Temperatures) and single coarse delay element with delay path with clock.Shown in square frame 716, adopt these measurements to add the measurement result that obtains in square frame 704 or 706, can calculate, existing to calibrate with the retardation in the delay path, compensate because the caused variation of temperature change.The details of calculating is seen shown in Figure 20, and is described below.The result of temperature computation be a state variable " renewal " (UPDATE), whether expression must be upgraded or calibrate with delay path existing.In square frame 718, check this variable.If must upgrade, then shown in square frame 720, with the original value of clock cycle with now be updated to and equal currency (or new value) with delay path length.Subsequently, algorithm flow waited for that preset time at interval before turning back to the beginning of temperature control loop road.

Referring to Figure 21, among the figure more detailed description detected temperatures process 740.As mentioned above, the delay length of the measurement of clock cycle, coarse delay element and now carrying out in non-now with delay path with effective delay length of delay path.Employing is chosen as existing example with clock with clock A, and then delay path B 612 is the non-delay path of now using.Shown in square frame 742 and 744, will now offer temperature phase detectors 654 (Figure 17) with clock and internal reference B, whether consistent on phase place to judge them.Lock-out state represents that all levels of delay path B612 appropriately calibrate with clock with existing.Shown in square frame 746,,, can search for and obtain the keyed end of delay path if lock-out state is failed as precautionary measures.If also not locking then shown in square frame 748 and 750, is got back to error state.

When non-at different levels when all locking in now with delay path, shown in square frame 752, obtain the thick tap of each level.The value of middle tap and thin tap.This thin delay aspect that is created in slightly, neutralizes need make existing with required retardation of clock cycle of clock delay.Subsequently, values of tap is converted to only and to be one in thin the delay.If coarse delay is less than its maximum, then shown in square frame 754 and 756, coarse delay increases progressively one-level.In addition, shown in square frame 758, coarse delay is successively decreased.Subsequently, shown in square frame 760, after regaining the phase place unanimity, obtain new middle delay values of tap and the thin values of tap that postpones.This just according to middle delay and thin delay the (tap and new thin tap in new), obtains effective delay of coarse delay.Then, shown in square frame 762,, non-ly now can make himself and now use delay path corresponding with delay path by the cancellation temperature sensor.Subsequently, shown in square frame 764, read existing with the delay path values of tap (now with thick tap, existing with in tap and now use thin tap).

These measured values have been arranged, can shown in square frame 766-770, calculate the several temperature compensating parameter.Can calculate the retardation of a coarse delay element according to the less delayed element:

Coarse delay=| (middle tap+thin tap)-(tap in new+new thin tap) | (4)

Also can accounting temperature measure according to middle tap and thin tap:

Temperature=(coarse delay * thick tap)+middle tap+thin tap (5)

Now can calculate by following formula with the delay length of delay path:

Postpone length=(coarse delay * now use thick tap)+existing with in tap+now use thin tap (6)

Subsequently, the detected temperatures algorithm finishes in square frame 772.

Equation (4) produces reference value and measured value to (6), can calcuating correction value according to these values, and to revise the delay of delay path 610 and 612, the influence of compensation temperature.Referring to Figure 22, there is shown the algorithm flow 778 of calcuating correction value.In the square frame 780, temperature is than calculating with following formula:

The temperature ratio is defined as original temperature or the beginning temperature is removed by current measured value or subsequent measurement.Thereby, the percentage that this thermometer temperature indicating degree increases or reduces.In general, when temperature rises, by the delay increase of each macrostructure.Similarly, when temperature descends, postpone to reduce.Yet rate of change can be different in carse, medium and small delay-level.In a kind of rate of change of the coarse delay level structure faster than middle delay-level and thin delay-level, because effective delay of equivalent single coarse delay element needs more thin delay element, the delay length of coarse delay element rises.In addition, because the length of equivalence clock cycle needs less coarse delay element and less thin delay element, so the overall measurement value descends.So when temperature rose, measured temperature descended, vice versa.

Subsequently, shown in square frame 782, the temperature ratio that calculates is added to senior filter, detect serious temperature fluctuation.If measured temperature greater than such as original measurement value 120% or less than 80% of original measurement value, think that then Current Temperatures is invalid, and executive termination.In the square frame 784, a mistake filter is arranged, shelter the phase detectors mistake.For example, if phase detectors 654 (Figure 17) have+/-1 thin intrinsic error rate that postpones tap, then think the temperature ratio greater than 98% but less than 101%, and ignore current measured value.

Secondly, the temperature ratio according to calculating carries out the estimation of delay path position.Determine new temperature ratio, thereby when multiplying each other, produce delay path because temperature and the estimated value that moves in theory with current delay path length.Shown in square frame 786, read the existing delay path of using, to judge carse, medium and small length of delay (thick tap, middle tap and thin tap).Subsequently, shown in square frame 788, check delay path, judge whether it is long.The long delay path definition is the delay path that comprises the thick values of tap of non-zero, and short delay path is the delay path that comprises zero thick values of tap.Because delay path comprises the thick values of tap of non-zero, new temperature ratio is inversely proportional to the temperature ratio, and delay path does not comprise coarse delay value, and new temperature is proportional to the temperature ratio than directly, so make above-mentioned differentiation.If delay path is not long, then shown in square frame 796, with new temperature than set for square frame 780 in the temperature calculated than equating.If delay path is long, then as shown in square frame 790, than whether greater than 100%, set new temperature ratio according to temperature.If the temperature ratio is not more than 100%, then:

New temperature ratio=100%+ (100%-temperature ratio) (8) is shown in square frame 792.If the temperature ratio is greater than 100%, then

New temperature ratio=100%-(temperature is than-100%) (9) is shown in square frame 794.

Thereby shown in square frame 798, new delay path length can be calculated by following formula:

New delay path length=current delay path length * new temperature in square frame 800 and 802, is calculated the poor of new, old delay path than (10) subsequently, and this difference is distributed on the middle delay-level by following example rule:

(if (temperature than＞100%) and (delay line=weak point) or

((temperature is than＜100%) and (delay line=length))

Δ delay path length=new delay path length then

Tap in new=middle tap+Δ delay path length

(if (temperature than＜100%) and (delay line=weak point)) or

((temperature is than＞100%) and (delay line=length))

Δ delay path length=former delay path length-Xin delay line length

Tap in new=middle tap-Δ delay line length

Attention has only middle delay-level to be used for compensates in this implementation.Subsequently, shown in square frame 804, come the updating delay path with new values of tap.Subsequently, shown in square frame 806, use the new length in following formula computing relay path:

New delay path length=(coarse delay * thick tap)+new middle tap+thin postpone (11)

The update mode variable also is configured to " 1 " at this point, upgrades thereby can carry out the delay path tap.Subsequently, as shown in square ENGTH frame 808, get back to and upgrade and new delay path length.

Although above describe the present invention and advantage thereof in detail, should be appreciated that under situation about not departing from by the invention spirit and scope defined in the claim hereinafter, can do various variations, replacement and variation to the foregoing description.

Claims (40)

1. the calibration first redundant timing signal and second redundant timing signal and the circuit that switches between binary signal is characterized in that it comprises:

Select and commutation circuit, be used for receiving the described first redundant timing signal and the second redundant timing signal, and one in the described redundant timing signal is appointed as used, and that another is appointed as is inactive;

But be connected and have first delay path of program setting length of delay with described selection circuit, be used for receiving and describedly now use redundant timing signal, and produce the first output timing signal;

But be connected and have second delay path of program setting length of delay with described selection circuit, be used for receiving and describedly non-ly now use redundant timing signal, and produce the second output timing signal;

With described first delay path and the phase detectors that second delay path is connected, be used for receiving described existing with and non-existing with the output timing signal, and the status signal of phase relation is therebetween represented in generation;

With the controller that described phase detectors are connected, be used for controlling the length of delay that the described program of described first delay path and second delay path can be set, thereby according to described status signal, to described existing with and non-showing carry out phase alignment with timing signal.

2. circuit as claimed in claim 1 is characterized in that, described selection and commutation circuit be according to the described detection mistake of now using in the timing signal, switch described existing with the non-timing mark signal of now using.

3. circuit as claimed in claim 1 is characterized in that, described selection and commutation circuit be according to the clock switching command, switch described existing with the non-timing mark signal of now using.

4. circuit as claimed in claim 1 is characterized in that, described selection circuit with default method select existing with the non-timing signal of now using.

5. circuit as claimed in claim 1 is characterized in that, described first delay path and second delay path comprise respectively:

Coarse delay circuit with a plurality of coarse resolution delay elements, and

The thin delay circuit that is connected and has a plurality of thin resolution delay elements with described coarse delay circuit.

6. circuit as claimed in claim 1 is characterized in that, described first delay path and second delay path comprise respectively:

Have a plurality of coarse resolution delay elements coarse delay circuit,

The middle delay circuit that is connected and has a plurality of intermediate-resolution delay elements with described coarse delay circuit, and

Be connected and have the thin delay circuit of a plurality of thin resolution delay elements with described intermediate retardation circuit.

7. circuit as claimed in claim 1 is characterized in that, described first delay path and second delay path comprise respectively:

But under coarse resolution program setting be the coarse delay level that increases progressively,

But be connected with described coarse delay level and under intermediate-resolution program setting be the middle delay-level that increases progressively, and

But with described in delay-level is connected and under resolution carefully program setting be the thin delay-level that increases progressively.

8. circuit as claimed in claim 1 is characterized in that, it also comprises with described first delay path and is connected with described second delay path, and storage is used to postpone the described preferable tap registers of now using the preferable length of delay of timing signal.

9. circuit as claimed in claim 8 is characterized in that it also comprises according to variations in temperature, changes the temperature-compensation circuit of the described preferable length of delay of storing in the described preferable tap registers.

10. circuit as claimed in claim 1 is characterized in that it also comprises according to variations in temperature, but but the temperature-compensation circuit of the described program setting length of delay of the delay path of the described program setting of calibration.

11. circuit as claimed in claim 10 is characterized in that, described temperature-compensation circuit comprises:

But but receive described existing with timing signal and produce the delay timing signal of the length of delay that has postponed a program setting program setting temperature delay path,

But with the temperature phase register that described program setting temperature delay path is connected, be used to receive described timing signal and the described delay timing signal now used, and produce the temperature phase-locked signal of phase locking between the described binary signal of expression, and

The control circuit that is connected with described temperature phase register, but be used to control the delay in described program setting temperature delay path, with the described clock cycle of now using timing signal of periodic measurement, the clock cycle of more described measurement, and computing relay calibrator quantity.

12. circuit as claimed in claim 11, it is characterized in that, but the temperature delay path of described program setting comprises the first parallel delay path part and the second parallel delay path part, be used for postponing discriminatively described now with timing signal with produce first and postpone now now to use timing signal with the timing signal and second delay, and described temperature phase register receives described first and postpones now now to use timing signal with the timing signal and second delay, and indicates its phase alignment.

13. circuit as claimed in claim 1, it is characterized in that, postpone describedly non-ly now to comprise the first parallel delay path part and second that is designated as main path part and the subordinate path part delay path part that walks abreast with described second delay path of redundant timing circuit, but the described first and second parallel delay paths partly receive described non-existing with timing signal and have the length of delay of program setting, described controller is also controlled described main path part and subordinate path part, now described main path part timing signal is carried out phase alignment with described, and further described subordinate path part timing signal is carried out phase alignment with described main path part timing signal with timing signal.

14. circuit as claimed in claim 13 is characterized in that, described controller is according to described main path part and centre, subordinate path obtains phase locking and described main path partly reaches maximum or minimum delay, switches described master and slave path part sign.

15. circuit as claimed in claim 1 is characterized in that, described controller calculates average delay value, but and control the length of delay of the described program setting of described second delay path, thereby calibrate the described non-timing signal of now using with timing signal with described showing.

16. circuit as claimed in claim 1 is characterized in that, described phase register comprises:

First signal and secondary signal that reception is used to calibrate, and the Phase Processing device of generation phase directional vector and phase clock,

Be connected with described phase detectors, lose the clock that decreases signal and lose the damage circuit to receive described phase clock and to produce phase clock, and

Lose the damage circuit with described Phase Processing device and clock and be connected, and lose the output processor that decreases signal generation delay path control signal according to described phase directional vector and phase locking.

17. one kind has a plurality of receptions and distributing in the timing subsystem telecommunication system of redundant timing signal, the circuit that is used for calibrating the first redundant timing signal and the second redundant timing signal and switches between binary signal is characterized in that it comprises:

Select and commutation circuit, be used for receiving the described first redundant timing signal and the second redundant timing signal and one in the described redundant timing signal is appointed as existing usefulness and another is appointed as non-existing using, and provide the described timing signal of now using as the output timing reference signal, described selection and commutation circuit are also in response to detecting mistake or clock switching signal, switch described now with timing mark signal and the non-timing mark signal of now using, and output timing reference signal;

First delay path, it is connected with described selection circuit, but has the length of delay of program setting, receives describedly now to use redundant timing signal, and produces the first output timing signal;

Second delay path, it is connected with described selection circuit, but has the length of delay of program setting, receives describedly non-ly now to use redundant timing signal, and produces the second output timing signal;

Phase detectors, it is connected with second delay path with described first delay path, receive described existing using and export timing signal and non-existing with the output timing signal, and the status signal of phase relation between the described binary signal is represented in generation;

Temperature-compensation circuit, it is connected with described second delay path with described first delay path, and measures influence of temperature variation on the described delay path;

Controller, it is connected with described phase detectors, but be used for controlling the length of delay of the program setting of described first delay path and second delay path, thereby described output timing signal is carried out phase alignment according to described status signal, described controller also is connected with described temperature-compensation circuit, be used for the described influence that records according to variations in temperature on the described delay path, but the length of delay of the described program setting of calibration.

18. circuit as claimed in claim 17 is characterized in that, described first delay path and described second delay path comprise respectively:

Coarse delay circuit with a plurality of coarse resolution delay elements;

Be connected with described coarse delay circuit, and have the middle delay circuit of a plurality of intermediate-resolution delay elements;

Be connected with described middle delay circuit, and have the thin delay circuit of a plurality of thin resolution delay elements.

19. circuit as claimed in claim 17 is characterized in that, described first delay path and described second delay path comprise respectively:

But program setting is the coarse delay level that increases progressively under coarse resolution;

Be connected with described coarse delay level, but and under intermediate-resolution program setting be the middle delay-level that increases progressively;

With described in delay-level is connected, but and under resolution carefully program setting be the thin delay-level that increases progressively.

20. circuit as claimed in claim 17 is characterized in that, it also comprises with described first delay path and is connected with described second delay path, and storage is used to postpone the described preferable tap registers of now using the preferable length of delay of timing signal.

21. circuit as claimed in claim 20 is characterized in that, it also comprises according to variations in temperature, changes the temperature-compensation circuit of the described preferable length of delay of storing in the described preferable tap registers.

22. circuit as claimed in claim 17 is characterized in that, but but it also comprises the temperature-compensation circuit of calibrating the described program setting length of delay of described program setting delay path according to variations in temperature.

23. circuit as claimed in claim 22 is characterized in that, described temperature-compensation circuit comprises:

But but receive the described existing program setting temperature delay path that also produces the delay timing signal of the length of delay that has postponed a program setting with timing signal;

The temperature phase detectors, but it be connected with the temperature delay path of described program setting, receiving described timing signal and the described delay timing signal now used, and produce the temperature phase-locked signal of phase locking between the described binary signal of expression;

Control circuit, it is connected with described temperature phase detectors, but is used for the delay in described program setting temperature delay path of the described clock cycle of now using timing signal of periodic measurement with control, the more described clock cycle that records, and computing relay calibration in view of the above.

24. circuit as claimed in claim 22, it is characterized in that, but the temperature delay path of described program setting comprises the first parallel delay path part and the second parallel delay path part, be used for postponing discriminatively described existing with timing signal and produce first and postpone now now to use timing signal with the timing signal and second delay, and described temperature phase detectors receive described first and second and postpone now to use timing signal, and indicate its phase alignment.

25. circuit as claimed in claim 17 is characterized in that, described first delay path and second delay path comprise the first parallel delay path part and the second parallel delay path part respectively.

26. the method for calibrating and switching between the first redundant timing signal and the second redundant timing signal is characterized in that it comprises following step:

Select a conduct in described first timing signal and the second timing signal now to use timing signal, and another is as the non-timing signal of now using, and provides the described timing signal of now using as the output timing base;

Detect described now with timing signal and the non-phase relation of now using timing signal;

The described non-timing signal of now using of incremental delay is up to described non-now consistent on phase place with the described timing signal of now using with timing signal;

According to described existing, switch described now with timing signal and non-timing signal and the described output timing base now used with timing signal or clock switching command.

27. method as claimed in claim 26 is characterized in that, described incremental delay step comprises following step:

Provide the described timing signal of now using to first delay path;

Provide the described non-timing signal of now using to second delay path;

Controllably make described showing postpone a preferable retardation with timing signal;

Incrementally calibrate the delay of described second delay path, until the phase place unanimity.

28. method as claimed in claim 27 is characterized in that, the described calibration steps that increases progressively comprises following step:

Determine described now with timing signal and non-each edge of now using in the timing signal;

Determine the described edge that is determined the forward position phase place and the back along phase relation;

Respectively according to described forward position phase place and back, the described non-delay of now using timing signal of increasing or decreasing along phase relation.

29. method as claimed in claim 27 is characterized in that, it also comprises following step:

Regularly the change detected temperature is to the described influence of now using the delay of timing signal;

According to the detected influence of described transformation temperature, calibrate described preferable retardation.

30. method as claimed in claim 29 is characterized in that, described transformation temperature influence detects step and comprises following step:

Now offer described first delay path and second delay path with described with timing signal;

The described timing signal of now using on described second delay path of incremental delay, consistent on phase place up to described first delay path with the described timing signal of now using on described second delay path;

Retardation is poor in record and more described first delay path and second delay path.

31. method as claimed in claim 29 is characterized in that, described transformation temperature influence detects step and comprises following step:

Now offer described first delay path and temperature delay path with described with timing signal;

The described timing signal of now using on the described temperature delay of the incremental delay path, consistent on phase place up to described first delay path with the described timing signal of now using on the temperature delay path;

Record and retardation poor wherein.

32. method as claimed in claim 30 is characterized in that, it also comprises according to described retardation relatively, calculates the step to the delay calibration of described delay path.

33. method as claimed in claim 31 is characterized in that, it also comprises according to described retardation relatively, calculates the step to the delay calibration of described delay path.

34. method as claimed in claim 26 is characterized in that, it also comprises following step:

Specify described non-be main timing signal and subordinate timing signal now with timing signal;

Postpone described main timing signal adjustablely, thereby obtain consistent with the described phase place of timing signal of now using;

Postpone described subordinate timing signal adjustablely, thereby obtain consistent with the phase place of described main timing signal.

35. method as claimed in claim 34, it is characterized in that, it also comprises according to obtaining phase locking and described main path between described main timing signal and the subordinate timing signal and partly reaches a certain maximum or minimum delay, switches described main mark and described subordinate sign.

36. method as claimed in claim 26 is characterized in that, it also comprises following step:

After described incremental delay step, store first length of delay;

Continue the described non-timing signal of now using of incremental delay, up to described non-now with timing signal and described now use the timing signal phase place inconsistent till, and store second length of delay;

Calculate the mean value of described first length of delay and second length of delay, and make the described non-existing average magnitude that postpones described calculating with timing signal.

37. the integrated circuit calibrating and switch the first redundant timing reference signal and the second redundant timing reference signal is characterized in that it comprises:

Be used for from the described first redundant timing reference signal and the second redundant timing reference signal, selecting a circuit of now using timing base;

Receive the described first redundant timing reference signal, but and make the retardation of described signal delay first program setting and produce first delay line of the first internal reference timing signal;

Receive the described second redundant timing reference signal, but and make the retardation of described signal delay one second program setting and produce second delay line of the second internal reference timing signal;

First phase detectors, it is connected with described first delay line, if and to specify the described second redundant timing reference signal be described when now using timing base, according to the described phase relation of now using between timing base and the described first internal reference timing signal, produce first group of delay line control signal, and described first delay line postpones the described first redundant timing reference signal according to described delay line control signal;

Second phase detectors, it is connected with described second delay line, if and to specify the described first redundant timing reference signal be described when now using timing base, according to the described phase relation of now using between timing base and the described second internal reference timing signal, produce second group of delay line control signal, and described second delay line postpones the described second redundant timing reference signal according to described delay line control signal;

Switch the described existing circuit of selecting with timing base according to instruction or mistake.

38. integrated circuit as claimed in claim 37 is characterized in that, it also comprises process, temperature and the voltage compensating circuit that abbreviates PTV as.

39. integrated circuit as claimed in claim 38, it is characterized in that, described PTV compensating circuit comprises second phase detectors, described second phase detectors are connected with second delay line with described first delay line, to detect the described phase relation of now using between timing base and the first internal timing reference signal or the second internal reference timing signal, and, produce one group of compensating delay line control signal according to this phase relation.

40. integrated circuit as claimed in claim 37 is characterized in that, comprises respectively in described first phase detectors and second phase detectors:

The Phase Processing device, it receives described internal reference timing signal and describedly now uses timing base, and produces the phase relation between the described binary signal and represent described internal reference timing signal and the described phase clock of now using time lag between the timing base;

Clock is lost the damage detector, and it receives described phase clock and the described timing base of now using, and the damage signal is lost in generation one when not having described phase clock;

Output processor, it is lost with described Phase Processing device and clock and decreases detector and be connected, and according to described phase directional, now with timing base and the described damage signal of losing, produces described delay line control signal.

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