CN110456256B - In-situ aging sensor based on backup circuit and aging monitoring method - Google Patents

In-situ aging sensor based on backup circuit and aging monitoring method Download PDF

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CN110456256B
CN110456256B CN201910841513.8A CN201910841513A CN110456256B CN 110456256 B CN110456256 B CN 110456256B CN 201910841513 A CN201910841513 A CN 201910841513A CN 110456256 B CN110456256 B CN 110456256B
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combinational logic
logic unit
backup
circuit
time
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CN110456256A (en
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赵天津
黄乐天
李强
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University of Electronic Science and Technology of China
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    • G01—MEASURING; TESTING
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Abstract

The invention discloses an in-situ aging sensor based on a backup circuit and an aging monitoring method.A backup combinational logic unit which is the same as the original circuit combinational logic unit is arranged, and the in-situ aging sensor further comprises the backup combinational logic unit, a plurality of multiplexers and a counter; at different times ti(i ═ 0, 1, 2, · · ·) respectively testing said original circuit combined logic unit and said backup combined logic unit to obtain different time tiThe total delay values of the next two; will tnTotal delay value of the two at time and tmComparing the total delay values of the two at the moment, correcting the contrast value of the combinational logic unit of the original circuit by using the contrast value of the backup combinational logic unit to obtain the total delay value from the moment tmTo time tnThe aging coefficients of the original circuit combinational logic cells. The aging measurement with high precision is realized, the influence of the process and the temperature on the aging monitoring is counteracted, the high reliability of the military electronic equipment circuit is ensured, and the hidden danger of the circuit can be found in time.

Description

In-situ aging sensor based on backup circuit and aging monitoring method
Technical Field
The invention relates to the field of circuit aging monitoring, in particular to an in-situ aging sensor based on a backup circuit and an aging monitoring method suitable for military electronic equipment.
Background
Integrated circuits face more and more challenges in the nanometer era, and particularly, as the integration degree is improved, the change of device parameters with time will bring more and more influences (such as abrasion, crystal defect accumulation, radiation, aging and the like), so that random effects in nanotechnology become larger, and thus the random effects in the circuits are represented as variability, which results in more serious error rate and serious influence on the reliability of the circuits.
The military electronic equipment has higher requirements on the reliability of circuits, particularly the control operation circuit represented by a processor, and the aging performance of the control operation circuit is mainly reflected in the time sequence increase of a critical path: on one hand, the failure of the circuit is that the length of the key path exceeds the clock period, so that the trigger samples wrong signal values, and therefore, whether the key path exceeds the clock period or not is detected to be a wide aging monitoring means; on the other hand, failures are also manifested in that as aging progresses, originally hidden manufacturing defects in the circuit are caused, such as open-circuit short-circuits of interconnection lines, and the like.
The on-chip aging sensors adopted by the current circuit aging monitoring are mainly replica circuit aging sensors, in-situ aging sensors based on path delay measurement and in-situ aging sensors based on time sequence error monitoring. The traditional replica circuit aging sensor is greatly influenced by the process deviation of an integrated circuit, so that the replica circuit cannot accurately represent the aging condition of the original circuit, and the measurement result is unreliable; due to the uncertainty of the circuit temperature changing along with the load, the traditional in-situ aging sensor cannot accurately measure the real aging condition of the circuit; the in-situ aging sensor based on the path delay measurement needs to introduce a delay chain, which brings larger chip area overhead, thereby generating larger influence on the performance of the monitored circuit.
Disclosure of Invention
In order to solve the problems, the invention provides an aging monitoring method based on a backup circuit, which is characterized in that a backup combinational logic unit which is the same as the original circuit combinational logic unit is arranged, the original circuit combinational logic unit is accessed between two stages of registers to normally work in a non-test state, and the backup combinational logic unit is in an idle state; at different times ti(i ═ 0, 1, 2, · · ·) respectively testing said original circuit combined logic unit and said backup combined logic unit to obtain different time tiThe total delay values of the next two; will tnTotal delay value of the two at time and tmComparing the total delay values of the two at the time (n > m), correcting the comparison value of the combinational logic unit of the original circuit by using the comparison value of the backup combinational logic unit, and obtaining the total delay value at the time tmTo time tnThe aging coefficient lambda, t of the original circuit combinational logic unitnThe total delay value of the time of day combinational logic cell is expressed as:
Figure BDA0002193867520000021
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000022
is tnThe total delay value of the time of day combinational logic cells,
Figure BDA0002193867520000023
is tnAt the moment of time the temperature is high,
Figure BDA0002193867520000024
is tmTime temperature, α being a constant, DpathFor combining the path delays of logic cells, DloopIs the feedback delay of the combinational logic cell.
The method for testing the original circuit combinational logic unit and the backup combinational logic unit comprises the following steps:
testing an original circuit combinational logic unit: connecting the backup combinational logic unit between the two stages of registers to enable the circuit to continue to work normally, and simultaneously connecting the combinational logic unit of the original circuit to a ring oscillator; enabling the oscillator to count each oscillation period and calculate the total delay value D of the combined logic unit of the original circuit in the current state according to the count valueroo；
Backup of the combinational logic unit test step: the original circuit combinational logic unit is positioned between the two stages of registers to ensure that the circuit works normally, and the backup combinational logic unit is connected to a ring oscillator; enabling the oscillator to count each oscillation period and calculate the total delay value D of the backup combinational logic unit in the current state according to the count valuerob。
The method for forming the ring oscillator comprises the following steps: connecting the output of the path to be tested of the combinational logic unit with an enabling signal, then connecting the output of the path to be tested to the input of the path, inverting the input and the output of the path to be tested, connecting the input of the other paths with a constant signal, and only activating the path to be tested.
The total delay value D of the original circuit combinational logic unitrooAnd the total delay value D of the backup combinational logic cellrobAre calculated according to the following formula:
Figure BDA0002193867520000025
in the formula, DroIs the total delay value of the combinational logic cell, fbaseIs a reference clock frequency, NbaseTo count the duration period, NROIs a count value.
The correction process includes obtaining a temperature increase ratio: the backup circuit is in an inactive state for a long time, the total delay value is only influenced by temperature, the aging coefficient lambda is 1, and t is comparednThe total delay value and t of the time backup combinational logic unitmThe total delay value of the backup combinational logic unit at the moment obtains the temperature increase ratio beta:
Figure BDA0002193867520000026
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000027
is tnThe total delay value of the combinational logic unit is backed up at a time,
Figure BDA0002193867520000028
is tmThe total delay value of the combinational logic unit is backed up at a time,
Figure BDA0002193867520000029
is tnThe moment in time backups the combinational logic cell ring oscillator count value,
Figure BDA00021938675200000210
is tmBacking up the count value of the ring oscillator of the combinational logic unit at any moment;
correcting tnThe total delay value of the combinational logic unit of the original circuit at the moment: the total delay value of the original circuit combinational logic unit is influenced by circuit aging and temperature, and the influence of the temperature on the test value is eliminated by introducing a backup circuit, so that the corrected total delay value is obtained:
Figure BDA0002193867520000031
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000032
for corrected tnTotal delay value of combinational logic cell of time original circuit, fbaseIs a reference clock frequency, NbaseIn order to count the duration of the period,
Figure BDA0002193867520000033
is tnThe time original circuit combines the count value of the logic unit ring oscillator,
Figure BDA0002193867520000034
is tnThe moment in time backups the combinational logic cell ring oscillator count value,
Figure BDA0002193867520000035
is tmThe moment backups the combinational logic unit ring oscillator count value.
Obtaining an aging coefficient lambdanThe method comprises the following steps: combining the original circuits into a logic unit tnTotal delay value of time and tmAnd comparing the total delay values at the moment, eliminating the influence of feedback delay, and obtaining the variation of the path delay:
Figure BDA0002193867520000036
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000037
is tmThe total delay value of the combinational logic unit of the original circuit at the moment;
at a time tmBased on the path delay of (a), the path aging at the subsequent time is measured to obtain the time tmTo time tnAging of the original circuit combinational logic cellCoefficient:
Figure BDA0002193867520000038
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000039
is tmTime path delay Dpath。
The in-situ aging sensor based on the backup circuit comprises an original circuit combinational logic unit, a plurality of multiplexers and a counter, wherein the original circuit combinational logic unit is connected between two stages of registers to normally work; the output end of the first-stage register is respectively connected with the first input end of the first multiplexer and the first input end of the second multiplexer, the output end of the first multiplexer is connected with the input end of the original circuit combinational logic unit, and the output end of the original circuit combinational logic unit is respectively connected with the first input end of the third multiplexer, the first input end of the fourth multiplexer and the second input end of the first multiplexer; the output end of the second multiplexer is connected with the input end of the backup combinational logic unit, and the output ends of the backup combinational logic unit are respectively connected with the second input end of the third multiplexer, the second input end of the fourth multiplexer and the second input end of the second multiplexer; the output end of the fourth multiplexer is connected with the counter.
The invention has the beneficial effects that: under the test mode, the alternate working and alternate measurement of the backup circuit and the original circuit ensure that the performance of the circuit is not influenced, the influence of the process and the temperature on aging monitoring is counteracted, the high-precision aging measurement is realized, the high reliability of the military electronic equipment circuit is ensured, and the hidden danger of the circuit can be found in time.
Drawings
FIG. 1 is a schematic diagram of a circuit in-situ aging sensor structure based on a backup circuit;
FIG. 2 is a schematic structural diagram in a non-test state;
FIG. 3 is a schematic diagram of the structure of the original circuit combinational logic unit under test;
FIG. 4 is a schematic diagram of a test state of a backup combinational logic unit;
FIG. 5 is a diagram of the overall process of testing;
FIG. 6 is a schematic diagram of a ring oscillator configuration;
FIG. 7 is a schematic diagram of a ring oscillator;
FIG. 8 is a timing chart of a measurement process according to the first embodiment;
FIG. 9 is a flow chart of a fastest aging rate path determination;
FIG. 10 is a schematic view of the second embodiment.
Detailed Description
In order to make the technical solutions of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
Modern digital integrated circuits are designed in RTL level, i.e. register transmission level, whether in pipeline structure or any other structure, the basic unit of circuit logic is basically composed of a combination logic circuit between a register and a register, and the aging of the circuit is often generated in the unit part of the combination logic circuit. In order to effectively offset the influence of process, voltage and temperature on aging monitoring and ensure the circuit performance during online test as much as possible, the invention provides an in-situ aging sensor based on a backup circuit and an aging monitoring method.
The aging monitoring method based on the backup circuit is characterized in that a backup combinational logic unit which is the same as the original circuit combinational logic unit is arranged, the original circuit combinational logic unit is connected between two stages of registers to normally work under a non-test state, and the backup combinational logic unit is in an idle state; at different times ti(i ═ 0, 1, 2, · · ·) respectively testing said original circuit combined logic unit and said backup combined logic unit to obtain different time tiThe total delay values of the next two; will tnTotal delay value of the two at time and tmComparing the total delay values of the two at the time (n > m), correcting the comparison value of the combinational logic unit of the original circuit by using the comparison value of the backup combinational logic unit, and obtaining the total delay value at the time tmTo time tnThe aging coefficient lambda, t of the original circuit combinational logic unitnThe total delay value of the time of day combinational logic cell is expressed as:
Figure BDA0002193867520000041
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000042
is tnThe total delay value of the time of day combinational logic cells,
Figure BDA0002193867520000043
is tnAt the moment of time the temperature is high,
Figure BDA0002193867520000044
is tmTime temperature, α being a constant, DpathFor combining the path delays of logic cells, DloopIs the feedback delay of the combinational logic cell.
In the in-situ aging sensor based on the backup circuit, the original circuit combinational logic unit is connected between two stages of registers to normally work and comprises the backup combinational logic unit, a plurality of multiplexers and a counter; the output end of the first-stage register is respectively connected with the first input end of the first multiplexer and the first input end of the second multiplexer, the output end of the first multiplexer is connected with the input end of the original circuit combinational logic unit, and the output end of the original circuit combinational logic unit is respectively connected with the first input end of the third multiplexer, the first input end of the fourth multiplexer and the second input end of the first multiplexer; the output end of the second multiplexer is connected with the input end of the backup combinational logic unit, and the output ends of the backup combinational logic unit are respectively connected with the second input end of the third multiplexer, the second input end of the fourth multiplexer and the second input end of the second multiplexer; the output end of the fourth multiplexer is connected with the counter.
In this embodiment, the backup combinational logic unit is completely the same as the original circuit combinational logic unit in the RTL level code, the circuit composition is the same after the circuit synthesis, and the physical positions after the layout and wiring are adjacent to each other, different functions of the circuit are realized by controlling the input and output of the backup combinational logic unit and the original circuit combinational logic unit, and the backup circuit has three states in total, instead of the original circuit operating state, the cold standby state and the oscillation test state.
The equivalent circuit diagram in the non-test state, i.e. the normal working state of the circuit, is shown in fig. two, the original circuit combinational logic unit is accessed between the two stages of registers to work normally by controlling the selection ports of the multiplexers at the input and output positions, and the backup combinational logic unit is controlled by the power gate to remove the V _ DD thereof, so that the BTI aging caused by the input fixation is avoided.
The testing process of the original circuit combinational logic unit and the backup combinational logic unit is as follows:
testing an original circuit combinational logic unit: connecting the backup combinational logic unit between the two stages of registers to enable the circuit to continue to work normally, and simultaneously connecting the combinational logic unit of the original circuit to a ring oscillator; enabling the oscillator to count each oscillation period and calculate the total delay value D of the combined logic unit of the original circuit in the current state according to the count valueroo；
As shown in fig. three, the backup combinational logic unit is connected between the two stages of registers by controlling the multiplexer, so that the circuit continues to work normally, meanwhile, the specific output of the original combinational logic unit is connected with the input to form a ring oscillator, and the oscillation signal is used as the clock to be connected into the counter, so that the counter of each oscillation period is increased by 1. The oscillation frequency of the ring oscillator is finally calculated by reading the counter value generated by oscillation within a fixed time, and the true and accurate delay of the circuit in the current state can be calculated by the oscillation frequency of the oscillator.
Backup of the combinational logic unit test step: the original circuit combinational logic unit is positioned between the two stages of registers to ensure that the circuit works normally, and the backup combinational logic unit is connected to a ring oscillator; enabling the oscillator, counting each oscillation period, and counting according to the count valueCalculating the total delay value D of the backup combinational logic unit in the current staterob。
As shown in the fourth figure, the original circuit is connected between the registers to work normally, and meanwhile, the backup circuit is connected into the ring oscillator to test the oscillation frequency, and then the circuit delay is calculated.
The test overall process of this embodiment is as shown in fig. five, where the circuit performs the original circuit test state from the non-test state, so that the original circuit starts to vibrate, the counter is enabled to count, the count value of the acquisition counter is counted, and the counter is reset after sampling is completed; and preparing to enter a test state of the backup circuit, enabling the backup circuit to start oscillation, enabling the counter to count, and resetting the counter after sampling of the count value of the acquisition counter to finish the test.
The method for forming the ring oscillator comprises the following steps: connecting the output of the path to be tested of the combinational logic unit with an enabling signal, then connecting the output of the path to be tested to the input of the path, inverting the input and the output of the path to be tested, connecting the input of the other paths with a constant signal, and only activating the path to be tested.
As shown in fig. six, a path with the fastest aging rate to be tested needs to be found out through a specific algorithm, the input of the path is connected to the output, and meanwhile, through analysis of circuit logic, other related inputs of the circuit are set to be in a specific state, so that the circuit is equivalent to a string of odd number of inverter chains, and thus the ring oscillator is formed. Taking a chain of nand gates in (a) as an example, connecting an output to one input of the first stage nand gate, setting the other inputs to be '1', and placing the inputs and outputs of other logic paths unrelated to the critical path in a floating manner, so as to equivalently become the inverter chain ring oscillator shown in (b).
As shown in fig. seven, the delay of the entire ring oscillator is made up of two parts: one is the path delay D in combinational logicpathThis is also the delay that ultimately needs to be measured; second, the delay D of the interconnection line fed back to the AND gate from RO _ OUTloopD can be considered to be the result of the feedback circuit being activated only during the measurement phase, due to the control of the enable signal ENloopHas little change in the value of (A), also is afterThe facets offset this delay by calculation and then get DpathAccurate delay provides a condition. Thus, one cycle requires two DpathAnd two Dloop：
Figure BDA0002193867520000061
The total delay value D of the original circuit combinational logic unitrooAnd the total delay value D of the backup combinational logic cellrobAre calculated according to the following formula:
Figure BDA0002193867520000062
in the formula, DroIs the total delay value of the combinational logic cell, fbaseIs a reference clock frequency, NbaseTo count the duration period, NROIs a count value.
FIG. eight shows a timing chart of the measurement process of this embodiment, in which the counting time is
Figure BDA0002193867520000063
Counter output NROPeriod of oscillation
Figure BDA0002193867520000064
Then the path delay
Figure BDA0002193867520000065
Thus from t1Time to t2Time DpathThe increment of (d) can be expressed as:
Figure BDA0002193867520000066
Figure BDA0002193867520000071
the path delay of the time of day is,
Figure BDA0002193867520000072
is t1The path delay of the time of day, the aging increase being reflected by the delay increment, and the delay increment eliminating DloopThe influence of (c).
It is clear to those skilled in the art that temperature variation affects the threshold voltage and electron mobility of CMOS devices, but among them the most significant effect on delay is the change in mobility, and the circuit delay gain ratio is a multiple (1.2-2.0) of the temperature gain ratio. From the above, the feedback section DloopHardly subject to aging, then:
Figure BDA0002193867520000073
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000074
is tnThe total delay value of the combinational logic cell of the original circuit at the moment,
Figure BDA0002193867520000075
is tmThe total delay value of the combinational logic cell of the original circuit at the moment,
Figure BDA0002193867520000076
is tnAt the moment of time the temperature is high,
Figure BDA0002193867520000077
is tmTime temperature, α being a constant, DpathFor combining the path delays of logic cells, DloopIs the feedback delay of the combinational logic cell.
The correction process includes obtaining a temperature increase ratio: the backup circuit is in an inactive state for a long time, the total delay value is only affected by temperature, the aging coefficient lambda is 1,
Figure BDA0002193867520000078
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000079
is tnThe total delay value of the combinational logic unit is backed up at a time,
Figure BDA00021938675200000710
is tmThe total delay value of the combinational logic unit is backed up at a time,
Figure BDA00021938675200000711
is tnAt the moment of time the temperature is high,
Figure BDA00021938675200000712
is tmThe time temperature, α, is constant.
By comparing tnThe total delay value and t of the time backup combinational logic unitmThe total delay value of the backup combinational logic unit at the moment obtains the temperature increase ratio beta:
Figure BDA00021938675200000713
in the formula (I), the compound is shown in the specification,
Figure BDA00021938675200000714
is tnThe total delay value of the combinational logic unit is backed up at a time,
Figure BDA00021938675200000715
is tmThe total delay value of the combinational logic unit is backed up at a time,
Figure BDA00021938675200000716
is tnThe moment in time backups the combinational logic cell ring oscillator count value,
Figure BDA00021938675200000717
is tmBacking up the count value of the ring oscillator of the combinational logic unit at any moment;
correcting tnTime of day original electricityTotal delay value of way combinational logic cell: the total delay value of the original circuit combinational logic unit is influenced by circuit aging and temperature, and the influence of the temperature on the test value is eliminated by introducing a backup circuit, so that the corrected total delay value is obtained:
Figure BDA00021938675200000718
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000081
for corrected tnTotal delay value of combinational logic cell of time original circuit, fbaseIs a reference clock frequency, NbaseIn order to count the duration of the period,
Figure BDA0002193867520000082
is tnThe time original circuit combines the count value of the logic unit ring oscillator,
Figure BDA0002193867520000083
is tnThe moment in time backups the combinational logic cell ring oscillator count value,
Figure BDA0002193867520000084
is tmThe moment backups the combinational logic unit ring oscillator count value.
Obtaining an aging coefficient lambdanThe method comprises the following steps: combining the original circuits into a logic unit tnTotal delay value of time and tmAnd comparing the total delay values at the moment, eliminating the influence of feedback delay, and obtaining the variation of the path delay:
Figure BDA0002193867520000085
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000086
is tmTotal delay value of combinational logic unit of original time circuit；
At a time tmBased on the path delay of (a), the path aging at the subsequent time is measured to obtain the time tmTo time tnThe aging coefficient of the original circuit combinational logic unit is as follows:
Figure BDA0002193867520000087
in the formula (I), the compound is shown in the specification,
Figure BDA0002193867520000088
is tmTime path delay Dpath。
The method for finding the fastest aging path is shown in figure nine, static time sequence analysis is carried out on a netlist file synthesized by an EDA tool to obtain a path set with the highest delay, meanwhile, simulation is carried out on a circuit netlist to obtain the temperature, the duty ratio and the inversion rate of each node in a circuit, the average temperature, the average duty ratio and the average inversion rate of each path are calculated by combining a key path, the average duty ratio and the average inversion rate are reordered, the path with the highest value is sequentially screened, and finally a target path set is obtained.
The overall structure of the second embodiment of the scheme applied to the RISC-V processor core aging sensor is shown in figure ten, and because the CPU realizes uniform delay of each stage of circuits among pipelines as far as possible at the beginning of design, a backup circuit which is the same as the original circuit needs to be constructed in each stage of circuit, test results of each stage of circuit are collected through a monitoring system interface, calculation is carried out, and the aging degree of each stage of circuit is monitored in real time.
In the test mode, the invention ensures that the performance of the circuit is not influenced through the alternate work and alternate measurement of the backup circuit and the original circuit, the influence of the process can be fundamentally eliminated through the aging measurement of the original circuit, and the influence of the temperature on the aging measurement data of the original circuit can be effectively corrected by using the test data of the backup circuit, thereby realizing the high-accuracy and high-precision monitoring on the aging of the combinational logic inside the processor, effectively solving the deviation caused by the process and the temperature of the integrated circuit and simultaneously ensuring the smaller influence of the online test on the performance of the processor.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.

Claims (5)

1. The aging monitoring method based on the backup circuit is characterized in that: setting a backup combinational logic unit which is the same as the original circuit combinational logic unit, wherein the original circuit combinational logic unit is accessed between two stages of registers to normally work in a non-test state, and the backup combinational logic unit is in an idle state; at different times tiRespectively testing the original circuit combinational logic unit and the backup combinational logic unit to obtain different moments tiThe total retardation values of the two following, i ═ 0, 1, 2 ·; will tnTotal delay value of the two at time and tmThe total delay values of the two are compared at the moment, n>m, correcting the contrast value of the combinational logic unit of the original circuit by using the contrast value of the backup combinational logic unit to obtain the contrast value from the time tmTo time tnAging coefficient lambda of the original circuit combinational logic celln，tnThe total delay value of the time of day combinational logic cell is expressed as:
Figure FDA0003078274220000011
in the formula (I), the compound is shown in the specification,
Figure FDA0003078274220000012
is tnThe total delay value of the time of day combinational logic cells,
Figure FDA0003078274220000013
is tnAt the moment of time the temperature is high,
Figure FDA0003078274220000014
is tmTime temperatureDegree, α is a constant, DpathFor combining the path delays of logic cells, DloopIs the feedback delay of the combinational logic cell;
the correction process comprises the following steps:
obtaining a temperature amplification ratio: the backup circuit is in an inactive state for a long time, the total delay value is only affected by temperature, and the aging coefficient lambda isnIs 1 by comparing tnThe total delay value and t of the time backup combinational logic unitmThe total delay value of the backup combinational logic unit at the moment obtains the temperature increase ratio beta:
Figure FDA0003078274220000015
in the formula (I), the compound is shown in the specification,
Figure FDA0003078274220000016
is tnThe total delay value of the combinational logic unit is backed up at a time,
Figure FDA0003078274220000017
is tmThe total delay value of the combinational logic unit is backed up at a time,
Figure FDA0003078274220000018
is tnThe moment in time backups the combinational logic cell ring oscillator count value,
Figure FDA0003078274220000019
is tmBacking up the count value of the ring oscillator of the combinational logic unit at any moment;
correcting tnThe total delay value of the combinational logic unit of the original circuit at the moment: the total delay value of the original circuit combinational logic unit is influenced by circuit aging and temperature, and the influence of the temperature on the test value is eliminated by introducing a backup circuit, so that the corrected total delay value is obtained:
Figure FDA00030782742200000110
in the formula (I), the compound is shown in the specification,
Figure FDA00030782742200000111
for corrected tnTotal delay value of combinational logic cell of time original circuit, fbaseIs a reference clock frequency, NbaseIn order to count the duration of the period,
Figure FDA00030782742200000112
is tnThe time original circuit combines the count value of the logic unit ring oscillator,
Figure FDA00030782742200000113
is tnThe moment in time backups the combinational logic cell ring oscillator count value,
Figure FDA00030782742200000114
is tmBacking up the count value of the ring oscillator of the combinational logic unit at any moment;
obtaining an aging coefficient lambdanThe method comprises the following steps: combining the original circuits into a logic unit tnTotal delay value of time and tmAnd comparing the total delay values at the moment, eliminating the influence of feedback delay, and obtaining the variation of the path delay:
Figure FDA0003078274220000021
in the formula (I), the compound is shown in the specification,
Figure FDA0003078274220000022
is tmThe total delay value of the combinational logic unit of the original circuit at the moment;
at a time tmBased on the path delay of (a), the path aging at the subsequent time is measured to obtain the time tmTo time tnThe aging coefficient of the original circuit combinational logic unit is as follows:
Figure FDA0003078274220000023
in the formula (I), the compound is shown in the specification,
Figure FDA0003078274220000024
is tmTime path delay Dpath。
2. The backup circuit based aging monitoring method of claim 1, wherein: the method for testing the original circuit combinational logic unit and the backup combinational logic unit comprises the following steps:
testing an original circuit combinational logic unit: connecting the backup combinational logic unit between the two stages of registers to enable the circuit to continue to work normally, and simultaneously connecting the combinational logic unit of the original circuit to a ring oscillator; enabling the oscillator to count each oscillation period and calculate the total delay value D of the combined logic unit of the original circuit in the current state according to the count valueroo；
Backup of the combinational logic unit test step: the original circuit combinational logic unit is positioned between the two stages of registers to ensure that the circuit works normally, and the backup combinational logic unit is connected to a ring oscillator; enabling the oscillator to count each oscillation period and calculate the total delay value D of the backup combinational logic unit in the current state according to the count valuerob。
3. The backup circuit based aging monitoring method of claim 2, wherein: the method for forming the ring oscillator comprises the following steps: connecting the output of the path to be tested of the combinational logic unit with an enabling signal, then connecting the output of the path to be tested to the input of the path, inverting the input and the output of the path to be tested, connecting the input of the other paths with a constant signal, and only activating the path to be tested.
4. The backup circuit based aging monitoring method of claim 2, wherein: original circuit groupTotal delay value D of the combinational logic cellrooAnd the total delay value D of the backup combinational logic cellrobAre calculated according to the following formula:
Figure FDA0003078274220000025
in the formula, DroIs the total delay value of the combinational logic cell, fbaseIs a reference clock frequency, NbaseTo count the duration period, NROIs a count value.
5. The in-situ aging sensor based on the backup circuit according to any one of the methods of claims 1 to 4, wherein the combinational logic unit of the original circuit is connected between two stages of registers to normally work, and the method is characterized in that: the device comprises a backup combinational logic unit, a plurality of multiplexers and a counter; the output end of the first-stage register is respectively connected with the first input end of the first multiplexer and the first input end of the second multiplexer, the output end of the first multiplexer is connected with the input end of the original circuit combinational logic unit, and the output end of the original circuit combinational logic unit is respectively connected with the first input end of the third multiplexer, the first input end of the fourth multiplexer and the second input end of the first multiplexer; the output end of the second multiplexer is connected with the input end of the backup combinational logic unit, and the output ends of the backup combinational logic unit are respectively connected with the second input end of the third multiplexer, the second input end of the fourth multiplexer and the second input end of the second multiplexer; the output end of the fourth multiplexer is connected with the counter.
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