CN101079687A - A clock adjustment algorithm based on minimum two multiplexing model - Google Patents

Abstract

The invention discloses a clock modulating algorism based on minimum square law pattern, which comprises the following steps: building mathematical model of phase difference; adopting phase-detector result of front N s to control the frequency of high-stability crystal per s; reserving the phase-detector result as parameter of next second preestimation; compensating the accumulated phase difference through 2 delta phase-detector result; controlling the frequency fluctuation of high-stability crystal within little scale; affirming the output precision of clock.

Description

A kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING

Technical field

The present invention relates to a kind of clock adjustment algorithm, can be used for adopting and revise the clockwork that the highly stable crystal method provides the high precision clock source, belong to communication technical field based on LEAST SQUARES MODELS FITTING.

Background technology

Digital synchronous network is the basis of the normal operation of digital communication network, also is the important means that ensures miscellaneous service network operation quality.It is listed as three big supporting networks of telecommunications network with telecommunication management network, signaling network, has critical role in telecommunications network.

For any communication equipment, all need clock to provide operating frequency, so clock performance is an importance that influences equipment performance for it.Clock often is called as the heart of equipment.Performance during clock work is mainly by two aspect decisions: the quality of self performance and external synchronization signal.And the quality of external synchronization signal is guaranteed by digital synchronous network.After equipment was formed system and network, digital synchronous network is necessary for system and network provides accurate timing, and to ensure its normal operation, whether the precision of interior each nodal clock of net influences a digital communication network job normal.

The digital communication network of China is in large scale, has a very wide distribution, and controls jointly so digital synchronous network generally will receive several primary resource clocks.If take time link to come the transmit timing signal, so along with the growth of Digital Transmission distance, transmission impairment increases gradually, reliability reduces gradually.And utilization is assemblied in the GPS receiver tracking UTC (UTC Universal Time Coordinated) on the reference clock, realize continuous adjustment to reference clock, make it the long run frequency accuracy that is consistent with UTC, thereby the purpose that reaches each reference clock synchronous operation and the whole network high level of synchronization is practicable, also is convenient and practical.And, in digital synchronous network, adopting GPS configuration baseline clock, implementation method is simple, and lock in time, the precision height improved the whole network performance, and cost is but cheap relatively, and is convenient to maintenance management, so gps clock is used widely in reference clock.

GPS is the abbreviation of the prefix abbreviation NAVSTAR/GPS of English Navigation Satellite Timing and Ranging/Global PositionSystem.Its implication is, when utilizing navigation satellite to survey and range finding, constitutes global positioning system, and this GPS (Global Position System) abbreviates GPS as.The space segment of gps system is made up of 24 satellites, and being evenly distributed on 6 elevations angle is on the orbital plane of 55 degree.The user of gps system receives the spread-spectrum signal of satellite transmission, measure the radio wave propagation time and obtain the distance of satellite to receiver antenna, utilize space three balls to intersect the principle of a bit, resolving with the receiver location is the equation of unknown number, thus the position of the receiver that knows for sure.It can provide continuously for global user, real-time, high accuracy three-dimensional Position, Velocity and Time information, can satisfy the needs of various different users.Gps system partly is made up of overhead satellites, tracking and monitoring station, ground, ground satellite data injection station, central station and data communication network etc.The user only need buy the GPS receiver, just can enjoy free navigation, time service and positioning service.Current, gps clock has become one of time delivery system that spread scope is the widest in the world, precision is the highest, gps clock that commercial receiver receives and universal time UCT (Universal Co-ordinated Time) keep high level of synchronization, and full accuracy can reach 20ns.But the reliability of civilian gps clock is not protected, and its owner does not guarantee precision and the reliability of GPS, and civilian users is assumed no responsibility.And more or less there are following errors in the gps clock that the GPS receiver receives: (1) ephemeris error: the error of giving the satellite position of newspaper in the gps signal, (2) satellite clock correction: the deviation of giving the satellite atomic clock of newspaper in the gps signal, (3) ionospheric error: because the error that the gps signal that the atmospheric ionization effect layer causes receives, (4) tropospheric error: because the error that the gps signal that the atmosphere convection effect layer causes receives, (5) multipath error: because reflected signal enters the error that gps signal that receiver antenna causes receives, (6) receiver error: because thermal noise, the measured value error that hardware deviation between software and each passage etc. causes, the very few error of (7) tracking satellite: the satellite of GPS receiver locking produces timing error less than 4 under certain conditions.Therefore, in actual applications, the precision and the stability of the clock signal that the GPS receiver produces are difficult to be guaranteed.The clock accuracy that common GPS receiver provides represents that with probability level receiver produces the error Normal Distribution of pulse per second (PPS) (1PPS).MOTOROLAUT ONCORE type receiver for example, statistical accuracy is 50ns (1 σ).The indignant rate that the pulse per second (PPS) deviation Normal Distribution of representing this receiver, gps clock error fall within the 1 σ scope (50ns) is 0.6828, and the indignant rate that falls within the 2 σ scopes (100ns) is 0.9546; The indignant rate that falls within the 3 σ scopes (150ns) is 0.9974.But under the condition of satellite losing lock or satellite clock experiment saltus step, gps clock error even reach tens milliseconds up to a hundred.

In order to contend with gps system, Russia has constructed GLONASS (Global Orbiting NavigationSatellite System) navigation system.It is higher that this system offers the precision of civilian clock signal, but the receiver price is more expensive, and same Russia does not guarantee precision and the reliability of GLONASS yet, civilian users is also assumed no responsibility, and the cost height, be difficult to obtain wide popularization and application.

Except gps clock and GLONASS clock, other conventional clock frequency generating method can be crystal, rubidium clock etc., and this class clock stability is higher, and the random drift in the single time interval is very little, but long playing cumulative errors are bigger.Crystal can wear out, and is subject to the external environment variable effect, long-term precision drift influence; Also can produce deviation after the long-term use of atomic clock, need timing alignment.And gps system is because the needs of its operating characteristic, regularly self clock system revised, so himself clock system long-term stability, having to external world, physical factor changes insensitive characteristic.Crystal or rubidium clock are long term reference with GPS, can obtain low cost, high performance reference clock.

For promoting the application of gps clock, need the two aspect problems that solve:

(1) gps clock is monitored in real time, pulse per second (PPS) sequence precision is assessed, guarantee the accuracy of output;

(2) gps clock is carried out error compensation, to improve the precision of output clock.

For solving above 2 problems, a kind of method be adopt several different satellite clock systems as: gps system and GLONASS system carry out mutual twin check, to improve the precision and the reliability of clock, this method realizes complicated, cost height, another kind of method are to adopt the gps clock method of punctual clock (atomic clock, crystal oscillator clock or CPU internal clocking) synchronously, proofread and correct punctual clock by gps clock when normally moving, under the GPS desynchronizing state, replace gps clock by punctual clock.When adopting crystal oscillator clock or CPU internal clocking as punctual clock, this method can only eliminate GPS in short-term losing lock produce than large deviation, can not eliminate SA and disturb and wait the less deviation that produces.As improving clock accuracy, need to adopt the atomic clock higher that gps clock is relatively monitored synchronously than gps clock precision, this method cost height is difficult to promote and realizes.

Summary of the invention

The purpose of this invention is to provide a kind of clock adjustment algorithm that guarantees clock output accuracy based on LEAST SQUARES MODELS FITTING.

For realizing above purpose, technical scheme of the present invention provides a kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING, it is characterized in that, adopts the program of C language establishment, runs in the clock synchronization device, and its method is:

A kind of gps clock adjustment algorithm based on LEAST SQUARES MODELS FITTING is characterized in that, adopts the program of C language establishment, runs in the clock synchronization device, and its method is:

The first step: according to the control initial value DA of the calculation of parameter D/A conversion chip of voltage-controlled crystal (oscillator), with electric control crystal on this initial value;

Second step: the pulse per second (PPS) of constant temperature highly stable crystal is alignd with the pulse per second (PPS) of GPS receiver, begin to follow the tracks of;

The 3rd step: according to the crystal voltage change adjustment crystal that phasemeter is got it right and answered, phase lag is accelerated frequency, and phase place reduces frequency in advance, begins to enter the process of quick tracking GPS, and this process continues half an hour,

Note last 400 times phase data, i.e. the biased sequence Y of formula 9; Establish crystal control this moment voltage D/A value after half an hour and be DA, record s time series X is that formula 2 values get 400;

The 4th step: each second estimated the phase difference of this second by linear regression algorithm by the phase data of preceding X-1 second It is formula 14, calculating this control magnitude of voltage offset Δ DA1 to crystal according to the calculated relationship of the corresponding relation of phase place and frequency and highly stable crystal frequency and control voltage is formula 15, Control Parameter with the voltage of this offset correction crystal is DA+ Δ DA1, adjusts the back X that finishes and progressively increases; The DA value was updated to DA=DA+ Δ DA1 after adjustment finished;

The 5th step: (when using MOTOROLA VP ONCORE is 2 σ units if differ by more than 100ns this second, it is 95.46% that the probability of this second of time identified result (lead-lag) accuracy equals the indignant rate that the GPS pulse per second (PPS) falls within the 2 σ scopes) time can think that phase difference is excessive, must carry out certain phase compensation, the phase place of compensation is the part that exceeds 100ns, calculated relationship according to the corresponding relation of phase place and frequency and highly stable crystal frequency and control voltage is calculated this control magnitude of voltage offset Δ DA2 (seeing formula 15) to crystal, is DA+ Δ DA2 with the Control Parameter of this offset correction crystal voltage; The DA value was not upgraded after adjustment finished;

The 6th step: repeated for the 4th step and revise repeatedly, time is long more, and number of samples is many more, and the voltage control parameter DA of the each second of voltage-controlled crystal (oscillator) will be along fuctuation within a narrow range about certain central value at this moment, totally level off to a horizontal linear, overcome the influence that GPS pulse per second (PPS) shake brings by linear regression.

The simple and practical method that the present invention adopts the high accuracy crystal oscillator that gps clock is monitored and proofreaied and correct is set up the measurement model of gps clock error, proposes a kind of production method of high precision clock, and successfully is applied in the clock synchronization device.

The GPS receiver in normal working conditions, only there is the shake of single pulse per second (PPS) in the error Normal Distribution of its clock, but from for a long time, there are not cumulative errors in gps clock.And the shake in the highly stable crystal short time is very little, but has bigger cumulative errors.The precision of gps clock and crystal oscillator clock is complementary, if the two is compared analysis, make the two reference each other, utilize the long-term accuracy characteristic of GPS that highly stable crystal is proofreaied and correct, adopt mathematical statistic method to estimate the error of the two, and then error carried out online Active Compensation, can realize high precision clock.

When specific implementation, adopt: the high accuracy crystal oscillator is carried out frequency division, produce the pulse per second (PPS) clock signal; Crystal oscillator pulse per second (PPS) clock carries out bit comparison mutually with the pulse per second (PPS) of GPS, produces biased sequence, this deviation comprise gps clock about shake differ cumulative errors with phase place; Adopt mathematical regression that two kinds of errors are estimated, thereby isolate error separately, and the crystal cumulative errors are revised, construct a kind of easy high precision clock generating means thus.Be specially and pass through frequency dividing circuit, the output clock of high precision clock is carried out frequency division, the pps pulse per second signal that obtains pps pulse per second signal digital phase demodulation filter of process and GPS behind the frequency division carries out bit comparison mutually, obtains the phase deviation sequence samples, and the accumulated error of crystal oscillator is provided with the offset correction by CPU.The per second adjustment once, the offset of N during second by the preceding N-1 gps clock sum of errors of second before the historical data of offset of the N-1 second offset that adopts the algorithm of linear regression to obtain estimating.

Advantage of the present invention is to guarantee gps clock output accuracy.

Description of drawings

Fig. 1 is the structural representation of clock synchronization device;

Fig. 2 is digital phase demodulation Filter Structures schematic block diagram;

Fig. 3 is the top layer electrical schematic diagram of digital phase demodulation filter inside;

Fig. 4 is the electrical schematic diagram in " DP_CTRL " module;

Fig. 5 is the clock adjustment algorithm FB(flow block) of LEAST SQUARES MODELS FITTING.

Embodiment

The invention will be further described below in conjunction with drawings and Examples.

Embodiment

As shown in Figure 1, for clock synchronization device is a structural representation, described clock synchronization device is made up of digital phase demodulation filter, GPS receiver, CPU and constant temperature highly stable crystal, numeral phase demodulation filter is connected with the GPS receiver, digital phase demodulation filter and CPU and constant temperature highly stable crystal connect to form the loop simultaneously, CPU:Rabbit2000, performance is equal to 8051 series that adopt the 16M crystal oscillator approximately.

As shown in Figure 2; be digital phase demodulation Filter Structures schematic block diagram; the present invention is directed to the pps pulse per second signal (or equivalent 1pps signal) of the 1pps that this receiver module of GPS cheaply provided; as External Reference comparison signal source; the output equivalent 1pps signal of the voltage-controlled quartz oscillator of this locality that the phase-locked loop that utilizes digital-to-analogue to mix is controlled is as local comparison signal source; by carrying out digital phase demodulation and filtering technique with FPGA; can adjust the characteristic and the precision of output signal flexibly, with the dealing with various requirements occasion.Among the present invention, used two local high-frequency signal sources, 1), the controlled local standard high frequency clock source by the VCXO of 16.384MHZ is formed by frequency division, can produce output clock and the local 1pps signal of 2.048MHZ.2), by 4 frequencys multiplication of 16.384MHZ both 65.536MHZ signal, as digital phase demodulation and filtering work clock.The phase difference of more local pps pulse per second signal of digital phase discriminator and External Reference pps pulse per second signal, pass through digital filtering again, and the Algorithm Analysis of outside software kit, can solve the 1pps output disturbance problem of GPS module, to guarantee the local output signal precision, can produce the multiple signal output suitable thus with the input signal source precision.

A kind of digital phase demodulation filter that the embodiment of the invention provided, and the GPS module that is connected with digital phase demodulation filter respectively, 2M frequency signal source module, CPU and 16.384MHZ voltage controlled frequency unit;

Because it all is to realize among FPGA (programmable logic device) that digital phase demodulation and digital filtering also have some auxiliary units, so here be described in detail with regard to the design realization of FPGA inside.

As shown in Figure 3, the top layer of digital phase demodulation filter inside electricity principle is as follows:

Top layer comprises 3 modules (module 1～module 3), and the left side pin of each module is input, and the right is output.But the pin of mark " BDB Bi-directional Data Bus " is that input and output are two-way.

1) interface module 1: " IO_INTERFACE ", be responsible for carrying out exchanges data with outer CPU, receive configuration-direct, report the phase place relativeness of local second signal and External Reference signal second etc.; The input of interface module 1 connects GPS module and 2M frequency signal source module respectively, connects CPU through data/address bus; According to configuration, select an External Reference source, and transfer it to pulse per second (PPS) output EXT_1PPS, as the External Reference foundation of phase demodulation.For example, CPU is by address wire ADDRES[31..24], / CS, ALE ,/WR cooperate, and are x " 00 " corresponding data lines DB[7..0 with the address] on content write this module, if data content is x " 00 ", show that then choosing " GPS_1PPS " is the External Reference source, interface module can directly output to it module output port " SEL_1PPS ", uses for external module; If data content is x " 01 ", show that then the first via in the choosing " 2MHZ[4..1] " (2MHZ[1]) is the External Reference source, owing to be the frequency input of 2.048MHZ at this moment, so module is done frequency division to it, produce the pulse per second (PPS) of 1pps, and it is outputed to module output port " SEL_1PPS ", use for external module; Other are analogized, and " External Reference " pulse per second (PPS) has just produced like this.

In like manner, CPU is also with the duty cycle parameters of output signal, and the parameter writing module of filter outputs to respectively on interface module " PW[7..0] " and " FILT_D[7..0] " port, uses for external module.

In addition,, offer the CPU visit by this interface module and read also by same mode from " UP ", " DOWN " of outer module, " OVER_DIR " phase place comparison output signal.

Like this, CPU just can be continual by the phase place relativeness between data wire grasp External Reference source and the local source, thereby provenance is adjusted during the controlled local standard high frequency that VCXO is formed, continue carrying out repeatedly like this, special algorithm by CPU, just finally reach the stable state of closed feedback loop, local output signal is the just tracking of the accurate external reference source of maintenance also.

2) local module (LOCAL_CQ) 2, be used to finish frequency division to the local crystal oscillator incoming frequency, the divide ratio that forwards 1hz by 16.384MHZ to carries out frequency division, and extracts other required frequencies out, also will export the duty ratio of pulse per second (PPS) by the pulse width data adjustment of CPU configuration simultaneously; The input of local module 2 is External Reference pulse per second (PPS) output, filter parameter output, reset the position output and the 16.384MHZ frequency signal source module of connection interface module 1 respectively, and local module 2 is respectively equipped with the output of signals such as other required frequencies such as pulse per second (PPS), 2.048MHZ, 200HZ, 8KMHZ; In addition, after the synchronous set command of the overline that receives CPU, divider state be alignd once again with the phase place of External Reference signal second.The pulse per second (PPS) L1PPS that is produced is the local reference frame of phase demodulation.

But the core here is exactly the synchronised clock cover half counter of an asynchronous set, and the mould value is 16.384 * 10 ⁶When counting value returns, both be the initial edge of local pulse per second (PPS), and the width of high level, promptly by the decision of " PW_D[7..0] " port numerical value, when Counter Value smaller or equal to PW_D[7..0] value the time, output keep high level, otherwise be low, if will expand adjusting range, can realize that thus, " this locality " pulse per second (PPS) has just produced by the figure place that increases pulse configuration data " PW_D[7..0] ".In addition, when the RESYN end is received replacement position signal, just produce a burst pulse, and guarantee to make it synchronous with the pulse per second (PPS) rising edge of External Reference, by this burst pulse counter is carried out asynchronous resetting, like this, after the replacement position, the state of local counter just is consistent with the External Reference source, the purpose of Chu Liing like this, be in order to accelerate the tracking lock process of external reference source, but also the digital phase demodulation and the filter circuit of follow-up module are simplified, because after the position of resetting, the phase place of local pulse per second (PPS) is close to consistent with the pulse per second (PPS) phase place in External Reference source, in short time period, between the two differ the drift not too large, so the range of observation of filter circuit just can dwindle.

3) data processing module (DP_CTRL) 3 is used for the phase-detection between inside and outside two pulses, also comprises the tunable integers character filter.The input of data processing module 3 is output, the output of local module 2 and the 4 frequency multiplication outputs of 16.384MHZ frequency signal source module of connection interface module 1 respectively, the input of the output connection interface module 1 of data processing module 3;

The phase-detection of notebook data processing module, detect two phase place relativenesses between the pulse exactly, these two input pulses are exactly " External Reference " pulse per second (PPS) that the external module before described had been handled, " this locality " pulse per second (PPS), identified result can reflect relative position and the variation tendency between " External Reference " pulse per second (PPS) and " this locality " pulse per second (PPS), and identified result is that the per second kind is upgraded once.

The introducing of tunable integers character filter, be the interference of antithesis electricity road to do shielding on the one hand, topmost effect is, when " External Reference " pulse per second (PPS) is that the GPS receiver module is when producing, its intrinsic pulse per second (PPS) " disturbance " is relatively large, system is weighed with high accuracy clock, the saltus step of its phase place is undesirable, also can cause interference simultaneously to the identified result of phase discriminator, especially when local clock source has in fact kept highly consistent with the External Reference source, this phenomenon can be more obvious, for this reason, filter the effect here filters out this phase place " saltus step " exactly as far as possible, in other words, " the big phase difference " with " burst " reports CPU exactly, and CPU can be according to certain algorithm, judge current virtual condition, thereby avoid unnecessary adjustment or " cross and adjust " and the output signal performance index that cause descend.But, the problem that a reality is used needs to consider, because the potential difference between the Individual circuits components and parts, the difference of the electrical property of especially possible GPS receiver module (for example: producer's difference, batch difference of producing or the like), all might allow use preset parameter filter lose usefulness, for this reason, the filter parameter here can be established, and real-time is controlled by CPU, thus, the phase difference width by " filtration " just can change, and has improved the reliability and the practicality of circuit performance greatly.

In addition, because " speed " and " precision " always is a pair of contradiction, filter range diminishes, systematic tracking accuracy uprises, but system enter stable state just take longer, otherwise, it is big that filter range becomes, the systematic tracking accuracy step-down, but that system enters stable state is just faster, for this reason, at different application scenarios, suitably adjust the parameter setting of filter, can change the Whole Response speed of system, increase work efficiency.

As shown in Figure 4, be the electrical schematic diagram in " DP_CTRL " module, be provided with phase discriminator unit 4 and filter cell 5,6 in the described data processing module;

Phase discriminator unit (V_DPD) 4: be the digital phase discriminator that makes up with the VHDL hardware description language, the External Reference pulse per second (PPS) output of the input difference connection interface module 1 of phase discriminator unit 4 and this locality of local module 2 are with reference to the pulse per second (PPS) output, be used to identify the phase relation of two input pulses, utilize the edge of pulse to differentiate, irrelevant with the pulse duration of input, very high resolution is arranged, when a local second signal frequency of input is higher than or during the leading External Reference of phase place signal second, output " DOWNDIR " just becomes ' 1 ', otherwise " UPDIR " just becomes ' 1 '.When being ' 0 ', represent that two input pulses are in full accord, promptly with the frequency homophase." DOWNDIR " is ' 1 ', and indication will lower the frequency of local VCXO, and " UPDIR " when being ' 1 ', and the frequency with local VCXO of indicating raises to be accelerated.Adding of phase discriminator unit 4 indicates, subtracts the frequency indication output end frequently respectively through controlling, subtract control input end frequently with adding frequently of door connection interface module 1.

A) leading filter cell (V_OVER_CTRL) 5, lag filter unit (V_OVER_CTRL) 6, the digital filter for making up with the VHDL hardware description language is used to overflow indication; Exceed FID[7..0 when two input pulses differ] during the value that sets, " OVER_ACT " exports ' 1 ' level, used two such modules here, exactly in order to distinguish two kinds of relative status: a.The leading External Reference of signal signal second overflowed b in local second.Signal lag External Reference signal second overflowed in local second, and unite two into one " OVER_DIR " to export, detect for CPU, FID[7..0] be set by CPU, can dynamically adjust, what its reflected is the periodicity of " clk * 4 " input clock (both 65.536MHZ), changes its value, can change the characterisitic parameter of output clock.

The input of leading filter cell 5 connects indication output end, 4 frequency multiplication outputs of 16.384MHZ frequency signal source module, the filter parameter output of interface module 1 frequently of adding of phase discriminator unit 4 respectively, the input of lag filter unit 6 connects indication output end, 4 frequency multiplication outputs of 16.384MHZ frequency signal source module, the filter parameter output of interface module 1 frequently of subtracting of phase discriminator unit 4 respectively, the control input end of overflowing of overflowing indication output end warp or door connection interface module 1 of leading filter cell 5 and lag filter unit 6.

Adopt mathematical regression that two kinds of errors are estimated, thereby isolate error separately, and the crystal cumulative errors are revised, construct a kind of easy high precision clock generating means thus.Be specially and pass through frequency dividing circuit, the output clock of high precision clock is carried out frequency division, the pps pulse per second signal that obtains pps pulse per second signal digital phase demodulation filter of process and GPS behind the frequency division carries out bit comparison mutually, obtains the phase deviation sequence samples, and the accumulated error of crystal oscillator is provided with the offset correction by CPU.The per second adjustment once, the offset of N during second by the preceding N-1 gps clock sum of errors of second before the historical data of offset of the N-1 second offset that adopts the algorithm of linear regression to obtain estimating.Algorithm is as follows:

The first step. set up the Mathematical Modeling of the synchronous crystal oscillator clock of gps clock

There are certain error e in GPS output clock and universal time, the e Normal Distribution:

ε～N(0，σ ²)。(1)

S time series X:

1，2，3，4，…，x，…，n (2)

The universal time of the s clock sequence correspondence of GPS output can be designated as

1-e ₁，2-e ₂，3-e ₃，4-e ₄，…，x-e _x，…，n-e _n (3)

General formula is expressed as y _x'=x-ε _xX ∈ N ε _x～(0, σ ²) (4)

Y in the formula _x' for GPS exports the universal time of x s clock correspondence, time error is e _x

If the 0th the s clock of s clock sequence that the crystal oscillator frequency division produces and the initial deviation of universal time are a; Time interval error is b; (as precision is 10 because the random error of high accuracy crystal oscillator is much smaller than the random error of the s clock of GPS ^-9The crystal oscillator random error of s＜1ns), therefore do not consider the random error of crystal oscillator s clock, the universal time of the clock sequence correspondence of crystal oscillator frequency division output s clock generating can be designated as

1+a+b，2+a+2b，3+a+3b，4+a+4b，…，x+a+bx，…，n+a+bn (5)

General formula is expressed as y _x"=x+a+bx x ∈ N (6)

Y in the formula _x" export the universal time of x s clock correspondence for the crystal oscillator frequency division, time error is

m(x)＝a+bc (7)

Then crystal oscillator frequency division s clock (being called for short crystal oscillator s clock) with the deviation of the s clock of GPS is

y _x＝y _x″-y _x′＝a+bx+ε _x x∈N (8)

Biased sequence Y can be expressed as

y ₁，y ₂，y ₃，y ₄，y ₅，y ₆，…，y _x，…，y _n (9)

Time series by Y can be to a, and b estimates, thereby calculates crystal oscillator s clocking error m (x); Simultaneously can be to the error e of GPS by the time series of Y _xEstimate, thereby can weigh the precision level of GPS receiver.

Second step. the estimation error of crystal oscillator s clock

The Linear Regression Model in One Unknown of employing formula (8) promptly adopts the regression equation of formula (7), analysis time sequence X and biased sequence Y correlation properties, to a, b carries out least-squares estimation, estimated value is respectively

$\hat{b}=\frac{\underset{x=1}{\overset{n}{\mathrm{\Σ}}}(x-\stackrel{\‾}{x})(y_x-\stackrel{\‾}{y})}{\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{(x-\stackrel{\‾}{x})}^2}---\left(10\right)$

$\hat{a}=\stackrel{\‾}{y}-\hat{b}\stackrel{\‾}{x}---\left(11\right)$

Y in the formula, x are respectively the mean value of biased sequence Y and time sequence X,

$\stackrel{\‾}{x}=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}x=\frac{n+1}{2}---\left(12\right)$

$\stackrel{\‾}{y}=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{y}_x---\left(13\right)$

Then x s clock of crystal oscillator output and the error estimate between the universal time

For

$\widehat{\mathrm{\μ}}\left(x\right)=\hat{a}+\hat{b}x---\left(14\right)$

Obtain

Be a time quantum, unit is second, also needs the controlled quentity controlled variable voltage (unit is V) of itself and highly stable crystal is changed.Control voltage is by the controlled quentity controlled variable decision of D/A chip, and conversion formula is as follows:

$\mathrm{\ΔDA}=\frac{\widehat{\mathrm{\μ}}\left(x\right)*D_{\mathrm{MAX}}}{\frac{f_{\mathrm{Max}}}{f_{\mathrm{MIN}}}-1}---\left(15\right)$

D in the formula _MAXThe figure place that depends on the DA conversion chip is sixteen bit conversion chip, then D as DA _MAX=65536.As DA is eight conversion chips, then D _MAX=256.f _MINBe the minimum frequency that voltage-controlled highly stable crystal is adjusted to, f _MAXThe peak frequency that can be adjusted to for voltage-controlled highly stable crystal.

According to error estimate

The Δ DA that obtains adjusts crystal oscillator s clock, can produce high precision clock output.

The s clocking error of the 3rd step .GPS receiver output is estimated

The estimation of the pulse per second (PPS) error of GPS receiver output is actually σ in the formula (1) ²Estimation because σ ²=D (ε)=E (ε ²) be the second order initial point distance of e, to press apart from the estimation technique, usable samples second order initial point is apart from the estimated value as it

${\widehat{\mathrm{\σ}}}^2=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{\mathrm{\ϵ}}_x^2---\left(16\right)$

And get by formula (8)

ε _x＝y _x-a-bx (17)

With Substitute a respectively, b promptly gets σ ²Estimator

${\widehat{\mathrm{\σ}}}^2=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{(y_x-\hat{a}-\hat{b}x)}^2---\left(18\right)$

The precision of size reflection receiver output pulse per second (PPS).Work as error estimate

The time, think GPS receiver step-out or fault.

As shown in Figure 5, gps clock adjustment algorithm FB(flow block) for LEAST SQUARES MODELS FITTING, the present invention passes through frequency dividing circuit, the output clock of high precision clock is carried out frequency division, the pps pulse per second signal that obtains pps pulse per second signal digital phase demodulation filter of process and GPS behind the frequency division carries out bit comparison mutually, obtain the phase deviation sequence samples, the accumulated error of crystal oscillator is provided with the offset correction by CPU.The per second adjustment once, the offset of N during second by the preceding N-1 gps clock sum of errors of second before the historical data of offset of the N-1 second offset that adopts the algorithm of linear regression to obtain estimating.The highly stable crystal frequency adjusted as revising with this offset, and to be calculated the offset of next second, the steps include: by this identified result

The first step: according to the control initial value DA of the calculation of parameter D/A conversion chip of voltage-controlled crystal (oscillator), with electric control crystal on this initial value.Concrete grammar is as follows:

The frequency-tuning range of this routine high voltage stability control crystal is 16.384M ± 15Hz, and the DA conversion chip is 16, reference voltage 5V, and the DA assignment is that 0 o'clock output voltage is 0, output frequency 16.384M-15Hz.The DA assignment is that 0 o'clock output voltage is 5V, output frequency 16.384M+15Hz.For the frequency initial value that guarantees to power on is roughly 16.384M, DA value 32768 gets final product;

Second step: the pulse per second (PPS) of crystal is alignd with the pulse per second (PPS) of GPS, begin to follow the tracks of;

The 3rd step: according to the crystal voltage change adjustment crystal that phasemeter is got it right and answered, phase lag is accelerated frequency, and phase place reduces frequency in advance, begins to enter the process of quick tracking GPS.The purpose of this process is that the central value for the output frequency that makes crystal can enter a scope more accurately, and in this scope fuctuation within a narrow range.This process continues half an hour, notes last 400 times phase data (being the biased sequence Y of formula 9).Crystal control this moment voltage D/A value is DA, and this routine DA is 32210.Record s time series X (formula 2) value gets 400;

The 4th step: each second estimated the phase difference of this second by linear regression algorithm by the phase data of preceding X-1 second

(establish this example for+5ns) (see formula 14), calculate this control magnitude of voltage offset Δ DA1=-179 (seeing formula 15) according to the calculated relationship of the corresponding relation of phase place and frequency and highly stable crystal frequency and control voltage to crystal.Control Parameter with the voltage of this offset correction crystal is DA+ Δ DA1=32210-179=32031, and adjusting that the back X that finishes progressively increases is 401; The DA value was updated to DA=DA+ Δ DA1=32031 after adjustment finished;

The 5th step: (when using MOTOROLA VP ONCORE is 2 σ units if differ by more than 100ns this second, it is 95.46% that the probability of this second of time identified result (lead-lag) accuracy equals the indignant rate that the GPS pulse per second (PPS) falls within the 2 σ scopes) as this example be+can think that phase difference is excessive during 105ns, must carry out certain phase compensation, the phase place of compensation is the part that exceeds 100ns, calculated relationship according to the corresponding relation of phase place and frequency and highly stable crystal frequency and control voltage is calculated this control magnitude of voltage offset Δ DA2=-179 (seeing formula 15) to crystal, is DA+ Δ DA2=32031-179=31852 with the Control Parameter of this offset correction crystal voltage; The DA value was not upgraded after adjustment finished;

The 6th step: repeated for the 4th step and revise repeatedly, the time is long more, and number of samples is many more, and this moment, the voltage control parameter DA of each second of voltage-controlled crystal (oscillator) will be along certain central value fuctuation within a narrow range up and down, totally levels off to a horizontal linear.Overcome the influence that the pulse per second (PPS) shake brings by linear regression.

Claims (9)

1. the clock adjustment algorithm based on LEAST SQUARES MODELS FITTING is characterized in that, adopts the program of C language establishment, runs in the clock synchronization device, and its method is:

The first step: according to the control initial value DA of the calculation of parameter D/A conversion chip of voltage-controlled crystal (oscillator), with electric control crystal on this initial value;

Second step: the pulse per second (PPS) of constant temperature highly stable crystal is alignd with the pulse per second (PPS) of GPS receiver, begin to follow the tracks of;

The 3rd step: according to the crystal voltage change adjustment crystal that phasemeter is got it right and answered, phase lag is accelerated frequency, and phase place reduces frequency in advance, begin to enter the process of quick tracking GPS, this process continues half an hour, notes last 400 times phase data, i.e. the biased sequence Y of formula 9; Establish crystal control this moment voltage D/A value after half an hour and be DA, record s time series X is that formula 2 values get 400;

The 4th step: each second estimated the phase difference of this second by linear regression algorithm by the phase data of preceding X-1 second

It is formula 14, calculating this control magnitude of voltage offset Δ DA1 to crystal according to the calculated relationship of the corresponding relation of phase place and frequency and highly stable crystal frequency and control voltage is formula 15, Control Parameter with the voltage of this offset correction crystal is DA+ Δ DA1, adjusts the back X that finishes and progressively increases; The DA value was updated to DA=DA+ Δ DA1 after adjustment finished;

The 5th step: if can think that phase difference is excessive when differing by more than 100ns this second, must carry out certain phase compensation, the phase place of compensation is the part that exceeds 100ns, calculating this control magnitude of voltage offset Δ DA2 to crystal according to the calculated relationship of the corresponding relation of phase place and frequency and highly stable crystal frequency and control voltage is formula 15, is DA+ Δ DA2 with the Control Parameter of this offset correction crystal voltage; The DA value was not upgraded after adjustment finished;

The 6th step: repeated for the 4th step and revise repeatedly, time is long more, and number of samples is many more, and the voltage control parameter DA of the each second of voltage-controlled crystal (oscillator) will be along fuctuation within a narrow range about certain central value at this moment, totally level off to a horizontal linear, overcome the influence that GPS pulse per second (PPS) shake brings by linear regression.

2. a kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING according to claim 1 is characterized in that, the computational methods in described step (3)-step (6) are:

The first step: the Mathematical Modeling of setting up the synchronous crystal oscillator clock of gps clock

There are certain error e in GPS output clock and universal time, the e Normal Distribution:

ε～N(0，σ ²)； (1)

S time series X:

1，2，3，4，...，x，...，n (2)

The universal time of the s clock sequence correspondence of GPS output can be designated as

1-e ₁，2-e ₂，3-e ₃，4-e ₄，...，x-e _x，...，n-e _n (3)

General formula is expressed as y _x'=x-ε _xX ∈ N ε _x～(0, σ ²) (4)

Y in the formula _x' for GPS exports the universal time of x s clock correspondence, time error is e _x,

If the 0th the s clock of s clock sequence that the crystal oscillator frequency division produces and the initial deviation of universal time are a; Time interval error is b; Do not consider the random error of crystal oscillator s clock, the universal time of the clock sequence correspondence of crystal oscillator frequency division output s clock generating can be designated as

1+a+b，2+a+2b，3+a+3b，4+a+4b，...，x+a+bx，...，n+a+bn (5)

General formula is expressed as y _x"=x+a+bx x ∈ N (6)

Y in the formula _x" export the universal time of x s clock correspondence for the crystal oscillator frequency division, time error is

m(x)＝a+bx (7)

Then crystal oscillator frequency division s clock (being called for short crystal oscillator s clock) with the deviation of the s clock of GPS is

y _x＝y _x″-y _x′＝a+bx+ε _x x∈N (8)

Biased sequence Y can be expressed as

y ₁，y ₂，y ₃，y ₄，y ₅，y ₆，...，y _x，...，y _n (9)

Time series by Y can be to a, and b estimates, thereby calculates crystal oscillator s clocking error m (x); Simultaneously can be to the error e of GPS by the time series of Y _xEstimate, thereby can weigh the precision level of GPS receiver;

Second step: the estimation error of crystal oscillator s clock

The Linear Regression Model in One Unknown of employing formula (8) promptly adopts the regression equation of formula (7), analysis time sequence X and biased sequence Y correlation properties, to a, b carries out least-squares estimation, estimated value is respectively

$\hat{b}=\frac{\underset{x=1}{\overset{n}{\mathrm{\Σ}}}(x-\stackrel{\‾}{x})(y_x-\stackrel{\‾}{y})}{\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{(x-\stackrel{\‾}{x})}^2}---\left(10\right)$

$\hat{a}=\stackrel{\‾}{y}-\hat{b}\stackrel{\‾}{x}---\left(11\right)$

Y in the formula, x are respectively the mean value of biased sequence Y and time sequence X, $\stackrel{\‾}{x}=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}x=\frac{n+1}{2}---\left(12\right)$

$\stackrel{\‾}{y}=\frac{1}{n}\stackrel{n}{\underset{x=1}{\mathrm{\Σ}}}{y}_x---\left(13\right)$

Then x s clock of crystal oscillator output and the error estimate between the universal time For

$\widehat{\mathrm{\μ}}\left(x\right)=\hat{a}+\hat{b}x---\left(14\right)$

Obtain

Be a time quantum, unit is second, also needs the controlled quentity controlled variable voltage (unit is V) of itself and highly stable crystal is changed, and control voltage is by the controlled quentity controlled variable decision of D/A chip, and conversion formula is as follows:

$\mathrm{\ΔDA}=\frac{\widehat{\mathrm{\μ}}\left(x\right)*D_{\mathrm{MAX}}}{\frac{f_{\mathrm{Max}}}{f_{\mathrm{MIN}}}-1}---\left(15\right)$

According to error estimate

The Δ DA that obtains adjusts crystal oscillator s clock, can produce high precision clock output;

The 3rd step: the s clocking error of GPS receiver output is estimated

The estimation of the pulse per second (PPS) error of GPS receiver output is actually σ in the formula (1) ²Estimation because σ ²=D (ε)=E (ε ²) be the second order initial point distance of e, to press apart from the estimation technique, usable samples second order initial point is apart from the estimated value as it

${\widehat{\mathrm{\σ}}}^2=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{\mathrm{\ϵ}}_x^2---\left(16\right)$

And get by formula (8)

ε _x＝y _x-a-bx (17)

With

Substitute a respectively, b promptly gets σ ²Estimator

${\widehat{\mathrm{\σ}}}^2=\frac{1}{n}\underset{x=1}{\overset{n}{\mathrm{\Σ}}}{(y_x-\hat{a}-\hat{b}x)}^2---\left(18\right)$

The precision of size reflection receiver output pulse per second (PPS), work as error estimate

The time, think GPS receiver step-out or fault.

3. a kind of clock adjustment algorithm according to claim 1 based on LEAST SQUARES MODELS FITTING, it is characterized in that, described clock synchronization device is made up of digital phase demodulation filter, GPS receiver, CPU and constant temperature highly stable crystal, numeral phase demodulation filter is connected with the GPS receiver, and digital phase demodulation filter and CPU and constant temperature highly stable crystal connect to form the loop simultaneously.

4. a kind of clock adjustment algorithm according to claim 3 based on LEAST SQUARES MODELS FITTING, it is characterized in that, described digital phase demodulation filter is realized in FPGA (programmable logic device), what be connected with digital phase demodulation filter respectively has GPS module, standard signal source module, CPU and a controlled local standard voltage controlled frequency unit, constitute a high accuracy clock device, it is characterized in that described digital phase demodulation filter comprises:

One interface module, be used for and comprise that the external module of the FPGA of CPU carries out information exchange, the phase detection information that is about between inside and outside two pulses is exported to CPU, and input signals such as the duty cycle parameters of CPU, filter parameter, replacement position are transferred to corresponding module in the FPGA; Its input connects described GPS module and described standard signal source module respectively, connects described CPU through data/address bus;

One local module is used to finish the frequency division to the local crystal oscillator incoming frequency, and the replacement position of local pulse per second (PPS), and exports other required frequencies; Its input connects External Reference pulse per second (PPS) output, the filter parameter output of described interface module, reset position output and controlled local standard voltage controlled frequency unit module respectively, and described local module is respectively equipped with the output of other required frequencies;

One data processing module comprises that adjustment by the tunable integers character filter that CPU is provided with filter parameter, is used for the phase-detection between inside and outside two pulses; Its input connects the output of the output of described interface module, described local module and the frequency multiplication output of controlled local standard voltage controlled frequency unit module respectively, and its output connects the input of described interface module;

Described CPU controls the replacement position of local module, the parameter of filter, the duty ratio of output signal according to the phase detection information between inside and outside two pulses.

5. a kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING according to claim 4 is characterized in that, is provided with in the described data processing module:

One phase discriminator unit, be used to identify the phase relation of two input pulses, the External Reference pulse per second (PPS) output of its input difference connection interface module and this locality of local module are with reference to the pulse per second (PPS) output, and it adds indicates, subtracts the frequency indication output end frequently respectively through controlling, subtract the frequency control input end frequently with adding of door connection interface module;

An one leading filter cell and a lag filter unit is used to overflow indication; The input of leading filter cell connects indication output end, the frequency multiplication output of controlled local standard voltage controlled frequency unit module, the filter parameter output of interface module frequently of adding of phase discriminator unit respectively; The input of lag filter unit connects indication output end, the frequency multiplication output of controlled local standard voltage controlled frequency unit module, the filter parameter output of interface module frequently of subtracting of phase discriminator unit respectively, the control input end of overflowing of overflowing indication output end warp or door connection interface module of leading filter cell and lag filter unit.

6. a kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING according to claim 4 is characterized in that described standard signal source module is a 2M frequency signal source module.

7. a kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING according to claim 4 is characterized in that, described controlled local standard voltage controlled frequency unit is the voltage controlled frequency unit of 16.384MHZ.

8. a kind of clock adjustment algorithm based on LEAST SQUARES MODELS FITTING according to claim 4 is characterized in that the required frequency of other of described local module output is pulse per second (PPS), 2.048MHZ, 200HZ, 8KMHZ.

9. digital phase demodulation filter according to claim 4 is characterized in that, the frequency multiplication output of described controlled local standard voltage controlled frequency unit module is 4 frequency multiplication outputs of 16.384MHZ voltage controlled frequency unit module.

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