CN105187149B - Clock synchronization system based on satellite orbit self-learning algorithm is fitted output system and method certainly - Google Patents
Clock synchronization system based on satellite orbit self-learning algorithm is fitted output system and method certainly Download PDFInfo
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Abstract
The invention discloses the clock synchronization system based on satellite orbit self-learning algorithm, with reference to pulse per second (PPS) receiving module, with reference to pulse per second (PPS) correcting module, output module is fitted certainly from output system, including satellite message processing module (MPM), satellite orbit self-learning module is fitted；By satellite orbit self-learning algorithm, the problem of solving the SPA sudden phase anomalies that external reference pulse per second (PPS) phase is caused due to the reduction of satellites in view number；Meanwhile, external reference pulse per second (PPS) is filtered using wave filter, external discrete shake is eliminated；External reference pulse per second (PPS) is after amendment, and the present invention uses least square fitting OCXO aging curves, it is ensured that the stability of pulse per second (PPS) output, improves the timekeeping performance of clock synchronization system.
Description
Technical field
The present invention provides the clock synchronization system based on satellite orbit self-learning algorithm from output intent is fitted, and belongs to electric power
Technical field of automation.
Background technology
In power system, using the pulse per second (PPS) phase accuracy of Time-Dependent synchronization system during synchronous pair of secondary device.Close
And the secondary device such as unit, PMU (phasor measurement unit) is very high for the requirement of pulse per second (PPS) phase accuracy and stability, remaining two
Secondary device, also can more and more higher to phase accuracy requirement in order to improve sampling precision and facilitate crash analysis.Therefore high accuracy is right
When become a basic function of secondary equipment in power system.
The pulse per second (PPS) phase of satellite modules output is by the other interpolation algorithms of Doppler measurement location algorithm mating part
Draw, satellites in view is more, the pulse per second (PPS) phase of satellite modules output is more accurate.When satellites in view is less than or equal to four
(the satellite number for meeting basic fixed position time service), is limited by algorithm, and mutation occurs in the pulse per second (PPS) phase of satellite modules output.
On the other hand, by earth atmosphere and climatic effect, inherently there is discrete shake in satellite-signal, and the shake meets Gauss point
There is the larger shake of only a few within submicrosecond in the shake in cloth, 90% confidential interval.The above external cause is equal
Pulse per second (PPS) phase can be influenceed.
Clock synchronization system relies on constant-temperature crystal oscillator OCXO and provides clock signal, but the physical characteristic of crystal oscillator determines that crystal oscillator exists
During use, frequency always changes over time, that is, crystal oscillator aging phenomenon.The aging direction of crystal oscillator
Ununified rule, and aging curve is logarithmic curve.Because clock synchronization system run time is most more than 10 years,
1us/H need to be reached plus the punctual precision of Industry code requirements clock synchronization system, so processing crystal oscillator aging phenomenon is particularly significant.
Therefore, it is necessary to a kind of new technical scheme is to solve the above problems.
The content of the invention
To solve above-mentioned irresistible factor, the present invention provides the clock synchronization system based on satellite orbit self-learning algorithm
From fitting output intent, solve due to system local environment change the discrete shake of the SPA sudden phase anomalies, the external clock reference that cause with
And device inside crystal oscillator aging and cause the problem of time signal stability of local clock is reduced.
In order to realize above-mentioned target, the present invention is adopted the following technical scheme that：
Clock synchronization system based on satellite orbit self-learning algorithm is fitted output system, including satellite Message processing mould certainly
Block, satellite orbit self-learning module, with reference to pulse per second (PPS) receiving module, with reference to pulse per second (PPS) correcting module, from fitting output module；
The satellite message receives to processing module, arranges the message data from satellite, and is transferred to the satellite
Track self-learning module；The satellite orbit self-learning module to count the orbital data of satellites in view and carry out self study,
And self study result is transferred to the reference pulse per second (PPS) correcting module；The reference pulse per second (PPS) receiving module comes to receive
Outside reference pps pulse per second signal, by being transferred to the reference pulse per second (PPS) correcting module after filtering process；The pulse per second (PPS) is repaiied
Positive module refers to pps pulse per second signal to correct, and is transferred to described from fitting output module；It is described to be used to from fitting output module
By least square fitting aging curve, and export local pps pulse per second signal.
Also include CPU, FPGA, constant-temperature crystal oscillator OCXO, satellite reception module；The CPU is to realize above-mentioned satellite message
Processing module, certainly satellite orbit self-learning module, fitting output module；The FPGA is to realize that above-mentioned reference pulse per second (PPS) is received
Module, with reference to pulse per second (PPS) correcting module；The OCXO for FPGA to provide clock signal；The satellite reception module is received and defended
Star message signals, and by Serial Port Transmission to CPU.
The OCXO frequencies are 20MHz.
The CPU is using the POWERPC frameworks for being not less than 266MHz dominant frequency or the CPU of ARM frameworks.
The FPGA logic cell quantity is no less than 24000.
The clock synchronization system based on satellite orbit self-learning algorithm can use following technical side from output intent is fitted
Case：
Including step：
1) satellite Message processing：Satellite reception module receives the message from big-dipper satellite and gps satellite, and passes through serial ports
It is transferred to CPU；CPU is by analyzing the satellites in view orbit information message inside message, by the orbital data of each satellites in view
It is transferred to satellite orbit self-learning module；
2) satellite orbit self study：CPU is to step 1) orbital data that transmits sets up database, visually defended all
Star enters visual range and recorded with the time for leaving visual range；By multiple data collection, every can be gone out with self study
The visible cycle of satellites in view, line period of going forward side by side covering；When the satellites in view coverage rate for calculating the following visible cycle is less than 4
During satellite, warning information is transferred to FPGA pulse per second (PPS) correcting module；
3) receive and filtering external refers to pulse per second (PPS)：FPGA is received after external reference pulse per second (PPS), by bandpass filter
Processing, the pulse per second (PPS) that phase offset is more than default threshold is filtered, to eliminate the discrete shake of external clock reference.After filtering
Pulse per second (PPS) correcting module is transferred to reference to pulse per second (PPS)；
4) pulse per second (PPS) amendment：FPGA receives step 3) reference pulse per second (PPS) after, according to step 2) obtained warning information
Carry out step-by-step processing：It is poor that reference pulse per second (PPS) phase under reference pulse per second (PPS) phase and non-alert status under alert status is carried out
Value compares, and long-term record arithmetic mean of instantaneous value；Reference pulse per second (PPS) phase under alert status is modified, correction value is above-mentioned
Arithmetic mean of instantaneous value；To the reference pulse per second (PPS) under non-alert status without amendment；Final result is transferred to from fitting output module；
5) from fitting output：FPGA receives step 4) amendment pulse per second (PPS) after, use the pulse per second (PPS) calculate OCXO frequency
Rate, CPU is transmitted to by the frequency counting of each second；CPU is and bent according to aging by least square fitting OCXO aging curve
The frequency counting in next pulse per second (PPS) cycle is fed back to FPGA by line again；FPGA exports the final local second according to the frequency counting
Pulse
Compared with background technology, the present invention has the following advantages：
The present invention solves external reference pulse per second (PPS) phase due to satellites in view number by satellite orbit self-learning method
The problem of SPA sudden phase anomalies for reducing and causing；Meanwhile, external reference pulse per second (PPS) is filtered using wave filter, eliminate it is outside from
Dissipate shake；External reference pulse per second (PPS) is after amendment, and the present invention uses least square fitting OCXO aging curves, it is ensured that second arteries and veins
The stability of output is rushed, the timekeeping performance of clock synchronization system is improved.It the composite can be widely applied to clock synchronization system.
Brief description of the drawings
Fig. 1 is that the clock synchronization system based on satellite orbit self-learning algorithm is fitted output system structure chart certainly；
Fig. 2 is the visual periodic cover schematic diagram of Satellite track self-learning algorithm of the present invention；
Fig. 3 is that the clock synchronization system based on satellite orbit self-learning algorithm is fitted output intent flow chart certainly.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
As shown in figure 1, the clock synchronization system based on satellite orbit self-learning algorithm is fitted output system, including satellite certainly
Message processing module (MPM), satellite orbit self-learning module, with reference to pulse per second (PPS) receiving module, with reference to pulse per second (PPS) correcting module, from fitting
Output module；The satellite message processing module (MPM) receives, arranges the message data from satellite, and is transferred to the satellite orbit
Self-learning module；The satellite orbit self-learning module counts the orbital data of all satellites in view and carries out self study, and will
Self study result is transferred to the reference pulse per second (PPS) correcting module；The reference pulse per second (PPS) receiving module is received from outside ginseng
Pps pulse per second signal is examined, by being transferred to the reference pulse per second (PPS) correcting module after filtering process；The pulse per second (PPS) correcting module is repaiied
Pps pulse per second signal is just referred to, is transferred to described from fitting output module；It is described to be intended from fitting output module by least square method
Aging curve is closed, and exports local pps pulse per second signal.
Clock synchronization system based on satellite orbit self-learning algorithm is based on CPU, FPGA from fitting output system hardware,
Constant-temperature crystal oscillator OCXO, satellite reception module；The CPU realizes above-mentioned satellite message processing module (MPM), satellite orbit self-learning module,
From fitting output module；The FPGA realizes above-mentioned reference pulse per second (PPS) receiving module, with reference to pulse per second (PPS) correcting module, defeated from being fitted
Go out module；The OCXO provides clock signal for FPGA；The satellite reception module receives satellite message signals, and passes through serial ports
It is transferred to CPU.
Outside constant-temperature crystal oscillator OCXO frequencies are 20MHz, to meet clock synchronization system time service and punctual precision.
CPU is using the POWERPC frameworks for being not less than 266MHz dominant frequency or the CPU of ARM frameworks, to ensure quick carry out most
Small square law is calculated.
FPGA logic cell quantity is no less than 24000, to meet clock synchronization system basic function demand.
As shown in figure 3, the above-mentioned clock synchronization system based on satellite orbit self-learning algorithm is fitted output intent, step certainly
Including：
1) satellite Message processing：Satellite reception module receives the message from big-dipper satellite and gps satellite, the message one second
One group of clock, content includes temporal information, latitude and longitude information, satellites in view satellite mark, satellites in view orbital position etc..These reports
Text by Serial Port Transmission to CPU, satellites in view satellite mark and satellites in view track position that CPU is read the newspaper by analytic solution inside text
Put, the orbital data of each satellites in view is transferred to satellite orbit self-learning module；
2) satellite orbit self study：CPU is to step 1) orbital data that transmits sets up database, visually defended all
Star enters visual range and recorded with the time for leaving visual range.As shown in Fig. 2 by multiple data collection, can be certainly
Learn the visible cycle of every satellites in view, line period of going forward side by side covering.When the satellites in view for calculating the following visible cycle is covered
When lid rate is less than 4 satellites, the pulse per second (PPS) correcting module by alert status information transfer to FPGA.When coverage rate is more than or equal to 4
During satellite, any alert status information is not transmitted；
3) receive and filtering external refers to pulse per second (PPS)：By earth atmosphere and climatic effect, satellite-signal is inherently present
Discrete shake, the shake meets shake in Gaussian Profile, 90% confidential interval within submicrosecond, but exist only a few compared with
Big shake.FPGA is received after external reference pulse per second (PPS), is handled by bandpass filter, and phase offset is more than into default threshold
Pulse per second (PPS) is filtered, to eliminate the discrete shake that external clock reference is larger.Reference pulse per second (PPS) after filtering is transferred to pulse per second (PPS)
Correcting module；
4) pulse per second (PPS) amendment：FPGA receives step 3) reference pulse per second (PPS) after, regardless of whether in alert status, all will
Get off with reference to pulse per second (PPS) phase recording.Then according to step 2) obtained warning information carries out step-by-step processing：When being in early warning
During state, the reference pulse per second (PPS) phase under the reference pulse per second (PPS) phase and non-alert status under alert status is subjected to difference ratio
Compared with, and long-term record arithmetic mean of instantaneous value.The average value is signed integer, can correctly reflect the direction of phase difference；It is then right
Reference pulse per second (PPS) phase under alert status is modified, and correction value is above-mentioned arithmetic mean of instantaneous value；To the ginseng under non-alert status
Pulse per second (PPS) is examined without amendment；Final result is transferred to from fitting output module；
5) from fitting output：FPGA receives step 4) amendment pulse per second (PPS) after, use the pulse per second (PPS) calculate OCXO frequency
Rate, CPU is transmitted to by the frequency counting of each second；CPU is and bent according to aging by least square fitting OCXO aging curve
The frequency counting in next pulse per second (PPS) cycle is fed back to FPGA by line again；FPGA exports the final local second according to the frequency counting
Pulse.Because aging curve is full curve, rather than the relatively independent point of frequency counting originally, so can have from fitting output
Effect evades the discrete shake with reference to pulse per second (PPS) submicrosecond level.Meanwhile, when clock synchronization system step-out, along OCXO aging curves
Output, can greatly improve timekeeping performance, and precision of keeping time is better than 1us/H.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and deformed
Also it should be regarded as protection scope of the present invention.
Claims (5)
1. the clock synchronization system based on satellite orbit self-learning algorithm is fitted output system certainly, it is characterised in that including satellite
Message processing module (MPM), satellite orbit self-learning module, with reference to pulse per second (PPS) receiving module, with reference to pulse per second (PPS) correcting module, from fitting
Output module；Also include CPU, FPGA, constant-temperature crystal oscillator OCXO, satellite reception module；
The satellite message processing module (MPM) receives to processing module, arranges the message data from satellite, and is transferred to described
Satellite orbit self-learning module；
The satellite orbit self-learning module is to count the orbital data of satellites in view and carry out self study, and by self study knot
Fruit is transferred to the reference pulse per second (PPS) correcting module；
The reference pulse per second (PPS) receiving module is to receive from outside reference pps pulse per second signal, by being transmitted after filtering process
To the reference pulse per second (PPS) correcting module；
The pulse per second (PPS) correcting module refers to pps pulse per second signal to correct, and is transferred to described from fitting output module；
It is described from fitting output module to by least square fitting aging curve, and export local pps pulse per second signal；
The CPU is to realize above-mentioned satellite message processing module (MPM), certainly satellite orbit self-learning module, fitting output module；
The FPGA to realize above-mentioned reference pulse per second (PPS) receiving module, with reference to pulse per second (PPS) correcting module, from fitting output module；
The OCXO for FPGA to provide clock signal；The satellite reception module receives satellite message signals, and passes through string
CPU is defeated by oral instructions.
2. the clock synchronization system according to claim 1 based on satellite orbit self-learning algorithm is fitted output system certainly,
It is characterized in that：The OCXO frequencies are 20MHz.
3. the clock synchronization system according to claim 1 based on satellite orbit self-learning algorithm is fitted output system certainly,
It is characterized in that：The CPU is using the POWERPC frameworks for being not less than 266MHz dominant frequency or the CPU of ARM frameworks.
4. the clock synchronization system according to claim 1 based on satellite orbit self-learning algorithm is fitted output system certainly,
It is characterized in that：The FPGA logic cell quantity is no less than 24000.
5. a kind of clock synchronization system based on satellite orbit self-learning algorithm according to any of the above-described claim is intended certainly
Close the output intent of output system, it is characterised in that：Including step：
1）Satellite Message processing：Satellite reception module receives the message from big-dipper satellite and gps satellite, and passes through Serial Port Transmission
To CPU；CPU is transmitted the orbital data of each satellites in view by analyzing the satellites in view orbit information message inside message
Give satellite orbit self-learning module；
2）Satellite orbit self study：CPU is to step 1）The orbital data transmitted sets up database, and all satellites in view are entered
Enter visual range and recorded with the time for leaving visual range；By multiple data collection, every can be gone out with self study visually
The visible cycle of satellite, line period of going forward side by side covering；When the satellites in view coverage rate for calculating the following visible cycle is less than 4 satellites
When, warning information is transferred to FPGA pulse per second (PPS) correcting module；
3）Receive and filtering external refers to pulse per second (PPS)：FPGA is received after external reference pulse per second (PPS), is handled by bandpass filter,
The pulse per second (PPS) that phase offset is more than default threshold is filtered, to eliminate the discrete shake of external clock reference；Reference after filtering
Pulse per second (PPS) is transferred to pulse per second (PPS) correcting module；
4）Pulse per second (PPS) amendment：FPGA receives step 3）Reference pulse per second (PPS) after, according to step 2）Obtained warning information is carried out
Step-by-step processing：Reference pulse per second (PPS) phase under reference pulse per second (PPS) phase and non-alert status under alert status is subjected to difference ratio
Compared with, and long-term record arithmetic mean of instantaneous value；Reference pulse per second (PPS) phase under alert status is modified, correction value is above-mentioned arithmetic
Average value；To the reference pulse per second (PPS) under non-alert status without amendment；Final result is transferred to from fitting output module；
5）From fitting output：FPGA receives step 4）Amendment pulse per second (PPS) after, use the pulse per second (PPS) calculate OCXO frequency, will
The frequency counting of each second is transmitted to CPU；CPU, and will according to aging curve by least square fitting OCXO aging curve
The frequency counting in next pulse per second (PPS) cycle feeds back to FPGA again；FPGA exports final local second arteries and veins according to the frequency counting
Punching.
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| JP2013017104A (en) * | 2011-07-06 | 2013-01-24 | Fujitsu Ltd | Communication system |
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| WO2005117311A1 (en) * | 2004-05-28 | 2005-12-08 | Thales | Distributed synchronization method and system |
| CN101079687A (en) * | 2006-05-25 | 2007-11-28 | 上海欣泰通信技术有限公司 | A clock adjustment algorithm based on minimum two multiplexing model |
| CN102427413A (en) * | 2011-08-30 | 2012-04-25 | 广东电网公司电力科学研究院 | Method and system for testing error of correction field of peer-to-peer transparent clock, and clock tester |
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