CN1819499B - Synchronous circuit processing method by master spare low-order pointer - Google Patents
Synchronous circuit processing method by master spare low-order pointer Download PDFInfo
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Abstract
The method includes: the low order pointer processing module working at main state makes module multi-frame count; when the multi-frame count value accords with the desired multi-frame count value, the indication of multi-frame count is sent out; the low order pointer processing module at standby state uses the received signal of multi-frame count indication to synchronize the its internal multi-frame count, and then to synchronize the low order read-write address of low order pointer processing module at main state. The invention solves the problem that is there are error codes generated when switch is made between the main low order pointer processing circuit and the standby low order pointer processing circuit.
Description
Technical field
The present invention relates to method synchronous to the master spare low-order pointer treatment circuit in synchronous digital hierarchy (SDH) system, this method relates to equally and has the synchronous other system of active and standby identical function module needs.
Background technology
In synchronous digital hierarchy (SDH) system (SDH), be the redundancy backup of 1+1 to the function module design of key, for example high-order cross-connect module, low-order pointer processing module, low order interlace algorithm link block etc.Wherein, standby high-order cross-connect module, low-order pointer processing module, low order interlace algorithm link block are in the Hot Spare state all the time.In principle, in case the master is broken down with a certain module in high-order cross-connect module, low-order pointer processing module, the low order interlace algorithm link block, system should be able to not switch on the spare module with having error code automatically.
For growing business demand in the synchronous digital hierarchy (SDH) system (SDH), require no error code generation under the situation that active and standby high-order cross-connect module, low-order pointer processing module, low order interlace algorithm link block are switched.Under existing technical conditions, giving clock, data and the frame alignment signal of active and standby high-order cross-connect module in full accord is not have error code in the time of can realizing the active and standby switching of active and standby high-order cross-connect module to take place, but can not realize that the active and standby switching of low-order pointer processing module do not have error code and take place.Therefore in actual engineering maintenance, present design is taking place might to have the generation of low order error code when the master spare low-order pointer processing module is switched.
Occur on the protection mechanism that the problems referred to above main cause is the low-order pointer processing module not well established.The master spare low-order pointer treatment circuit is distributed on the active and standby single-deck in the present synchronous digital hierarchy (SDH) system (SDH), relatively independent, the low-order pointer processing module is externally under the situation of conditionally complete unanimity, because the order that active and standby single-deck powers in application of practical project is at random, can be under out of order situation, to change or active and standby switching, also can be under the situation of function upgrading, to re-power etc., the time that causes the Pointer Justification Event in the low-order pointer processing circuit module in the active and standby single-deck to take place is inconsistent, thereby causes the pointer value of low order portion not necessarily identical; When synchronous digital hierarchy (SDH) system (SDH) need switch the low-order pointer processing module owing to fault,, therefore may have the low order error code and produce because the pointer value that the master spare low-order pointer processing module is sent is not necessarily identical.
The control information that does not transmit low-order pointer adjustment incident between the master spare low-order pointer processing module mutually is to cause switching the master spare low-order pointer processing module can not guarantee not have the reason that error code produces.Therefore present design is to have no idea to guarantee that the no error code of low-order pointer processing module switching produces.
Summary of the invention
The object of the present invention is to provide the synchronous method of master spare low-order pointer treatment circuit in a kind of synchronous digital hierarchy (SDH) system.
The synchronous method of master spare low-order pointer treatment circuit comprises step in a kind of synchronous digital hierarchy (SDH) system provided by the invention: be operated in and main will send into the payload buffer through the data that the low-order pointer explanation module is sent with the low-order pointer processing module of operating state and carry out buffer memory, the pointer generation module takes out data from the payload buffer simultaneously, and to carry out simultaneously in mould 4 multi-frames countings and the multi-frame be mould 4 frame counts of starting point with the multi-frame, sends multi-frame and count and indicate when multi-frame count value and expectation multi-frame count value are consistent; The low-order pointer processing module of standby operating state is come its interior multi-frame counting synchronously with the multi-frame counting index signal of sending here; Make during for high level the write address of corresponding payload buffer and main write address with operating state low-order pointer processing module correspondence TU12 tributary unit or TU3 tributary unit payload time slot consistent when time multiplexing signal in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot in odd-numbered frame, wherein time multiplexing signal is multi-frame to be counted index signal, payload buffer write address location index signal, payload buffer read the signal after the index signal time division multiplexing of address location; In even frame in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot when time multiplexing signal make during for high level corresponding payload buffer read the address and main with operating state low-order pointer processing module correspondence TU12 tributary unit or TU3 tributary unit payload time slot to read the address consistent.
The invention solves in the prior art, the master spare low-order pointer treatment circuit switches the problem that can not guarantee not have the error code generation.
Description of drawings
Fig. 1 is the realization flow schematic diagram of masterslave state index signal level identification;
Fig. 2 is main with state multi-frame counting synchronous working flow chart;
Fig. 3 is a stand-by state multi-frame counting synchronous working flow chart;
Fig. 4 is main with the synchronous flow chart of state low-order pointer processing payload buffer;
Fig. 5 handles the synchronous flow chart of payload buffer for the stand-by state low-order pointer.
Embodiment
The master spare low-order pointer processing module is separate in the existing synchronous digital hierarchy (SDH) system (SDH), externally under the situation of conditionally complete unanimity, because master spare low-order pointer processing module power-on time can not guarantee in full accord, there is not to transmit mutually the control information that low-order pointer is adjusted incident between the master spare low-order pointer processing module, the Pointer Justification Event that can not guarantee the output of master spare low-order pointer processing module is in full accord, when the low-order pointer processing module need be switched owing to fault in system, because the pointer value that the master spare low-order pointer processing module is sent is not necessarily identical, may has the low order error code and produce.
This method does not produce the low order error code in the time of can allowing the master spare low-order pointer processing module need switch the low-order pointer processing module in system owing to fault, allows synchronous digital hierarchy (SDH) system (SDH) really accomplish the no any error code of low-order pointer processing module switching.
The module such as stable operation clock, intersection that is related to system in the synchronous digital hierarchy (SDH) system (SDH) generally all adopts active and standby working method, have only module work such as a clock, intersection in that system is in service, modules such as another one clock, intersection are in Status of Backups.Active and standby intersection, clock module are all sent a corresponding indicating signals and are given and intersection, other modules that clock module is relevant, as line interface, master spare low-order pointer processing modules etc., indication intersects, clock module is operated in main with state or be operated in stand-by state.When active clock, Cross module need switch to standby clock, Cross module owing to the system failure, standby clock, Cross module enter the main operating state of using, the clock of main usefulness, Cross module enter standby operating state simultaneously, and the operating state index signal of active and standby intersection, clock module is overturn.
It is in full accord that active and standby intersection, clock module are given the data and the clock of master spare low-order pointer processing module, the operating state index signal that active and standby intersection, clock module are sent has been given the master spare low-order pointer processing module respectively simultaneously, and the master spare low-order pointer processing module is according to the operating state of the operating state index line decision master spare low-order pointer processing module of active and standby intersection, clock module.The operating state index signal that the activestandby state of while master spare low-order pointer processing module is sent according to active and standby intersection, clock module is carried out the switching of activestandby state.The operating state index signal that primary and backup intersection, clock module are given correlation module is mutual exclusion, being operated in main generally speaking is low level with the intersection of state, the operating state index signal that clock module is sent, and is operated in the intersection of stand-by state, the operating state index signal that clock module is sent is a high level.The operating state index signal of its corresponding active and standby intersection, clock module is overturn when upset takes place the operating state of active and standby intersection, clock module, promptly original master has become standby intersection, clock module with intersection, clock module, the masterslave state index signal of sending simultaneously becomes high level by low level, originally standby intersection, clock module have become intersection, the clock module of main usefulness, and the masterslave state index signal of sending simultaneously becomes low level by high level.
The operating state index signal of sending by active and standby intersection, clock module is controlled the operating state of master spare low-order pointer processing module or is controlled the operating state of low-order pointer processing module by relevant software processing mode.The master spare low-order pointer processing module can be configured to independent working mode and active and standby interrelated pattern by the relevant register configuration.It is high level or low level that active and standby interrelated pattern can be selected the level of masterslave state index signal by register configuration.
Be operated in and main will send into the payload buffer through the data that the low-order pointer explanation module is sent with the low-order pointer processing module of operating state and carry out buffer memory, the pointer generation module takes out data from the payload buffer simultaneously, at the state that carries out detecting when the payload buffer writes and reads the payload buffer, write and read address difference and carry out corresponding pointer adjustment within certain scope the time when detecting, carry out mould 4 multi-frames counting, frame count simultaneously, when the multi-frame count value is consistent with expectation multi-frame count value, send the indication of multi-frame counting; In odd-numbered frame, when being the design desired value, write address sends payload buffer write address location index signal in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot; In even frame, when reading the address, send the payload buffer in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot and read the address location index signal for the design desired value; By time division multiplexing the indication of multi-frame counting, payload buffer write address location index signal, payload buffer are read the address location index signal and send the low-order pointer processing module after multiplexing.
The low-order pointer processing module that is operated in standby operating state will be sent into the payload buffer through the data that the low-order pointer explanation module is sent and carry out buffer memory, the pointer generation module takes out data from the payload buffer simultaneously, at the state that carries out detecting when the payload buffer writes and reads the payload buffer, write and read address difference and carry out corresponding pointer adjustment within certain scope the time when detecting, receive simultaneously to be operated in and mainly pass through time-multiplexed signal with what the low-order pointer processing module of operating state was sent here, at first the counting of the multi-frame on time multiplexing signal index signal demultiplexing is come out, come multi-frame counting in the low-order pointer processing module of synchronized reserve operating state with multi-frame counting index signal simultaneously, make that the multi-frame counting of the multi-frame counting of low-order pointer processing module of standby operating state and main low-order pointer processing module with operating state is in full accord; Frame count is counted according to the multiframe alignment signal position indication separately of master spare low-order pointer processing module just can realize that mould 4 frame counts are in full accord.Multi-frame counting, frame count and main with the low-order pointer processing module in full accord after, in odd-numbered frame, make during for high level the write address value of corresponding payload buffer and the main write address value of operating state low-order pointer processing module correspondence TU12 tributary unit or TU3 tributary unit payload time slot of using consistent when time multiplexing signal in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot; In even frame in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot when time multiplexing signal make during for high level corresponding payload buffer read address value and main with operating state low-order pointer processing module correspondence TU12 tributary unit or TU3 tributary unit payload time slot to read address value consistent; Under the on all four situation of read/write address value of multi-frame counting, frame count, corresponding TU12 tributary unit or TU3 tributary unit payload time slot payload buffer, because it is in full accord to give clock, the data of master spare low-order pointer processing module after system powers on and stablizes, so the Pointer Justification Event of master spare low-order pointer processing module is in full accord.
When synchronous digital hierarchy (SDH) system need switch the low-order pointer processing module owing to fault, the low-order pointer processing module that is operated in main usefulness switches to standby operating state, mode according to standby low-order pointer processing module part is worked, be operated in standby low-order pointer processing module simultaneously and switch to the main operating state of using, work according to main mode with low-order pointer processing module part.Every generation is once switched, and the operating state of low-order pointer processing module takes place once to change.Utilize method of the present invention, can when breaking down, realize switching low order and not have any error code, and can increase the stability of equipment and the reliability of switching.
Below in conjunction with accompanying drawing, explain the embodiment of the inventive method in detail.
The reason of master spare low-order pointer processing module generation error code when switching is that the payload buffer action of master spare low-order pointer processing module is inconsistent, after making that the pointer processing module is read TU payload and framing from the payload buffer, the data flow of master spare low-order pointer processing module is inconsistent.Implementation of the present invention is to export read-write enable signal and the read/write address value that synchronous control signal is controlled the payload buffer in the standby low-order pointer processing module by main with the low-order pointer processing module, makes that the read-write enable signal and the read/write address value of the payload buffer in the master spare low-order pointer processing module are in full accord; Standby low-order pointer processing module receives only main synchronically controlling information with the low-order pointer processing module.
Low-order pointer processing module acquiescence after system powers on is low level according to the master with intersection, clock module operating state index signal, and standby intersection, clock module operating state index signal are the operating state that the mode of high level is discerned the low-order pointer processing module.It is high level with intersection, clock module operating state index signal that the low-order pointer processing module provides main simultaneously, and standby intersection, clock module operating state index signal are low level mode, discern the operating state of low-order pointer processing module in this way.Concrete processing mode as shown in Figure 1.The operating state that provides register directly to dispose the master spare low-order pointer processing module simultaneously can directly be configured to the low-order pointer processing module main with operating state, standby operating state or mutually independent (control signal of master spare low-order pointer processing module is invalid).
Because the power-on time of master spare low-order pointer processing module is at random, at first need the multiframe alignment signal of the system of master spare low-order pointer processing module is carried out mould 4 countings synchronously.System's multiframe alignment signal adopts 2 bit counter synchronously, a multiframe alignment signal counting of output indication when main multi-frame counting with the low-order pointer processing module is zero, indication comes preset system multiframe alignment signal 2 bit counter to standby low-order pointer processing module according to the multiframe alignment signal counting, thereby makes that master spare low-order pointer processing module mould 4 multi-frames counting is in full accord.Frame count is counted according to the multiframe alignment signal position indication separately of master spare low-order pointer processing module just can realize that mould 4 frame counts are in full accord.Idiographic flow is shown in Fig. 2,3.
The signal of payload buffer comprises and writes enable signal, write address, TU payload, reads enable signal and read the address in the low-order pointer processing module, wherein write address and read the address and adopt time-multiplexed mode to produce.For the TU12 payload, read/write address is totally 12 bits, and high 8 bits are represented the sequence number of 252 TU12 tributary units, and low 4 bits are represented the degree of depth of every road TU12 payload buffer.For the TU3 payload, read/write address is totally 11 bits, and high 4 bits are represented the sequence number of 12 TU3 tributary units, and low 7 bits are represented the degree of depth of every road TU3 payload buffer.The writing of TU payload buffer enable with the TU sequence number all be that framing signal according to high-order pointer processing module produces, irrelevant with the system power-on time; The high position of reading the address of same payload buffer produces according to system's framing signal, and is also irrelevant with the system power-on time.And the low level of payload buffer read/write address is to be produced by the counter in the internal circuit.In addition, the TU payload is that variation has taken place phase place when delivering to the payload buffer through the TU pointer interpreter, and same and system's power-on time has nothing to do.And TU payload buffer read effective id signal that enable signal is a payload, it has comprised the positive and negative adjustment information that is produced by the payload buffer.A circuit of judging read/write address is arranged in the payload buffer, when the difference of read-write low order address meets some requirements, will produce positive negative justification signal.Describe from above, the source of the high position of the read-write enable signal of payload buffer, read/write address and TU payload all is synchronous in the master spare low-order pointer processing module, the state of payload buffer that only need carry out just can realizing synchronously the master spare low-order pointer processing module to the low level of the read/write address of master spare low-order pointer processing module is in full accord, thereby makes the Pointer Justification Event unanimity of master spare low-order pointer processing module.
Under the control of multi-frame coincidence counter and frame synchronization counter, respectively the low-order pointer processing module of four transfer rates Synchronous Transport Module level-N that is 622.080Mbit/s is carried out synchronously, thereby realize to transfer rate being that the low-order pointer processing module of the Synchronous Transport Module level-N of 2488.320Mbit/s is carried out synchronously.The payload that the low-order pointer processing module is handled comprises two kinds of TU12 and TU3, in each transfer rate is in the low-order pointer processing module of Synchronous Transport Module level-N of 622.080Mbit/s in four frame times in a multi-frame, the write address low level of 252 TU12 tributary units of first frame synchronization payload buffer, 252 TU12 tributary units of second frame synchronization payload buffer read the address low level, the write address low level of 12 TU3 tributary units of the 3rd frame synchronization payload buffer, the reading the address low level and just can realize master spare low-order pointer processing module Pointer Justification Event unanimity of 12 TU3 tributary units of the 4th frame synchronization payload buffer.
For the TU12 tributary unit payload buffer of low-order pointer processing module, the scope that read/write address is low four is 0～15, and appointing certain two difference of getting in these 16 values is 8 two value W1, W2 (W2=W1+8).First frame in a multi-frame, when main with low-order pointer processing module TU12 tributary unit payload buffer in certain road TU12 write address hang down four when reaching the W1 value, the synchronous enabled control information of a pulse duration of output that is to say that the payload buffer is synchronous enabled to put 1.When next clock arrived, the corresponding road of standby low-order pointer processing module TU12 tributary unit payload buffer received this synchronous enabled control, was low four positions of the write address of corresponding road TU12 tributary unit payload buffer W1.Second frame in a multi-frame, when main with low-order pointer processing module TU12 tributary unit payload buffer in certain road TU12 read the address hang down four when reaching the W2 value, the synchronous enabled control information of a pulse duration of output that is to say that the payload buffer is synchronous enabled to put 1.When next clock arrived, the corresponding road of standby low-order pointer processing module TU12 tributary unit payload buffer received this synchronous enabled control, was low four positions of reading the address of corresponding road TU12 tributary unit payload buffer W2.For the TU3 payload buffer of low-order pointer processing module, the scope that read/write address is low seven is 0～127, appoints and gets two value W3, the W4 (W4=W3+64) of certain two difference 64 in these 128 values.The 3rd frame in a multi-frame, when main with low-order pointer processing module TU3 tributary unit payload buffer in certain road TU3 write address hang down seven when reaching the W3 value, the synchronous enabled control information of a pulse duration of output that is to say that the payload buffer is synchronous enabled to put 1.When next clock arrived, the corresponding road of standby low-order pointer processing module TU3 tributary unit payload buffer received this synchronous enabled control, was low seven positions of the write address of corresponding road TU3 tributary unit payload buffer W3.The 4th frame in a multi-frame, when main with low-order pointer processing module TU3 tributary unit payload buffer in certain road TU3 read the address hang down seven when reaching the W4 value, the synchronous enabled control information of a pulse duration of output that is to say that the payload buffer is synchronous enabled to put 1.When next clock arrived, the corresponding road of standby low-order pointer processing module TU3 tributary unit payload buffer received this synchronous enabled control, was low seven positions of reading the address of corresponding road TU3 tributary unit payload buffer W4.Idiographic flow is shown in Fig. 4,5.
Synchronous enabled control signal above-mentioned produces according to system-frame framing signal and multiframe alignment signal, and the time control signal effective length of read/write address all is the time of a frame synchronously.Because the payload of each frame is made up of 35 payloads of every road TU12 tributary unit or 765 payloads of every road TU3 tributary unit, and the degree of depth 16 of each TU12 tributary unit payload buffer, the degree of depth of each TU3 tributary unit payload buffer is 128.So produce any one value sure appearance in the time of a frame in the counter 0～15 of low four of TU12 tributary unit payload buffer, produce any one value also sure appearance in a frame time in the counter 0～127 of low 7 of TU3 tributary unit payload buffer equally.Therefore select the time of a frame can guarantee that every road TU12 and TU3 can both finish synchronously.
In order to reduce the number of signals that connects between the master spare low-order pointer processing module; The buffer control information of TU12 tributary unit payload and the control information of TU3 tributary unit payload buffer of low-order pointer processing module that to transfer rate is the Synchronous Transport Module level-N of 2488.320Mbit/s adopt time-multiplexed mode, and namely a synchronous control signal of primary low-order pointer processing module output has comprised TU12 tributary unit payload buffers all in the low-order pointer processing module of the Synchronous Transport Module level-N that four transfer rates are 622.080Mbit/s and synchronizing information and system's multi-frame counter synchronisation information of TU3 tributary unit payload buffer.
For fear of clashing, the time that the time control signal of the counter of synchronous payload buffer becomes a frame by time of a frame deducts 6 continuous clock pulse.These 6 burst lengths are used for transmitting the 2 bit counter control informations that realize synchronous 4 multi-frames counting.
When active and standby intersection, when upset takes place clock module operating state index signal, active and standby upset takes place in the operating state of corresponding low-order pointer processing module simultaneously, the operating state of the synchronous circuit in the corresponding low-order pointer treatment circuit is also overturn, promptly being operated in the main operating state upset of sending the low-order pointer processing module of synchronizing information with state originally is stand-by state, and reception simultaneously was operated in stand-by state originally and is now operating in the main synchronizing information of sending with the low-order pointer processing module of state; Originally the low-order pointer processing module that was operated in stand-by state is now operating in the master and sends synchronically controlling information with state.
Describing of above-mentioned embodiment only to explain that operation principle of the present invention is a purpose, does not constitute limiting the scope of the invention.Protection scope of the present invention is limited by incidental claims.
Claims (9)
1. the synchronous method of master spare low-order pointer treatment circuit in the synchronous digital hierarchy (SDH) system comprises step:
1) is operated in and main will send into the payload buffer through the data that the low-order pointer explanation module is sent with the low-order pointer processing module of operating state and carry out buffer memory, the pointer generation module takes out data from the payload buffer simultaneously, and carry out mould 4 multi-frames counting simultaneously, when the multi-frame count value is consistent with expectation multi-frame count value, send the indication of multi-frame counting;
2) the low-order pointer processing module of standby operating state uses the multi-frame counting indication of sending here to come its interior multi-frame counting synchronously; 3) in odd-numbered frame, make during for high level the write address value of corresponding payload buffer and main write address value consistent when time multiplexing signal in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot with operating state low-order pointer processing module correspondence TU12 tributary unit or TU3 tributary unit payload buffer, wherein time multiplexing signal is that multi-frame is counted index signal, payload buffer write address location index signal, the payload buffer is read the signal after the index signal time division multiplexing of address location, and payload buffer write address location index signal is sent during for the design desired value when write address in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot in odd-numbered frame; The payload buffer is read the address location index signal and is sent when reading the address for the design desired value in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot in even frame;
4) in even frame in corresponding TU12 tributary unit or the TU3 tributary unit payload time slot when time multiplexing signal make during for high level corresponding payload buffer read address value and main with operating state low-order pointer processing module correspondence TU12 tributary unit or TU3 tributary unit payload buffer to read address value consistent.
2. the method for claim 1, it is characterized in that: consistent of the read/write address of corresponding TU12 tributary unit or TU3 tributary unit payload buffer is needed under the control of multi-frame coincidence counter and frame synchronization counter, payload buffer read/write address low level to the low-order pointer processing module of four transfer rates Synchronous Transport Module level-N that is 622.080Mbit/s carries out synchronously the degree of depth of described low bit representation payload buffer respectively.
3. method according to claim 2, it is characterized in that: in each transfer rate is in the low-order pointer processing module of Synchronous Transport Module level-N of 622.080Mbit/s, in four frame times in a multi-frame, the write address low level of 252 TU12 tributary units of first frame synchronization payload buffer, 252 TU12 tributary units of second frame synchronization payload buffer read the address low level, the write address low level of 12 TU3 tributary units of the 3rd frame synchronization payload buffer, 12 TU3 tributary units of the 4th frame synchronization payload buffer read the address low level.
4. method as claimed in claim 3, it is characterized in that: appoint that to get difference in low four scopes 0～15 of read/write address be two value W1 of 8, W2, W2=W1+8, the write address low level of 252 TU12 tributary units of wherein said first frame synchronization payload buffer specifically comprises step: for the TU12 tributary unit payload buffer of low-order pointer processing module, first frame in a multi-frame, when main with low-order pointer processing module TU12 payload buffer in certain road TU12 payload buffer write address hang down four when reaching the W1 value, the synchronous enabled control information of a pulse duration of output, when next clock arrives, the corresponding road of standby low-order pointer processing module TU12 payload buffer receives this synchronous enabled control information, is low four positions of the write address of corresponding road TU12 payload buffer W1, the address low level of reading of 252 TU12 tributary units of wherein said second frame synchronization payload buffer specifically comprises step: second frame in a multi-frame, when main with low-order pointer processing module TU12 payload buffer in the payload buffer of certain road TU12 read the address hang down four when reaching the W2 value, the synchronous enabled control information of a pulse duration of output, when next clock arrives, the corresponding road of standby low-order pointer processing module TU12 payload buffer receives this synchronous enabled control information, is low four positions of reading the address of corresponding road TU12 payload buffer W2.
5. method as claimed in claim 3, it is characterized in that: appoint that to get difference in low seven scopes 0～127 of read/write address be two value W3 of 64, W4, W4=W3+64, the write address low level of 12 TU3 tributary units of wherein said the 3rd frame synchronization payload buffer specifically comprises step: for the TU3 tributary unit payload buffer of low-order pointer processing module, the 3rd frame in a multi-frame, when main with low-order pointer processing module TU3 payload buffer in certain road TU3 payload buffer write address hang down seven when reaching the W3 value, the synchronous enabled control information of a pulse duration of output, when next clock arrives, the corresponding road of standby low-order pointer processing module TU3 payload buffer receives this synchronous enabled control information, is low seven positions of the write address of corresponding road TU3 payload buffer W3, the address low level of reading of 12 TU3 tributary units of wherein said the 4th frame synchronization payload buffer specifically comprises step: the 4th frame in a multi-frame, when main with low-order pointer processing module TU3 payload buffer in certain road TU3 payload buffer read the address hang down seven when reaching the W4 value, the synchronous enabled control information of a pulse duration of output, when next clock arrives, the corresponding road of standby low-order pointer processing module TU3 payload buffer receives this synchronous enabled control information, is low seven positions of reading the address of corresponding road TU3 payload buffer W4.
6. the method for claim 1, it is characterized in that step 1), 2) multi-frame counting specifically comprises step synchronously: system's multiframe alignment signal adopts 2 bit counter synchronously, a multi-frame counting of output indication when main multi-frame counting with the low-order pointer processing module is zero, indication comes preset system multiframe alignment signal 2 bit counter to standby low-order pointer processing module according to the multi-frame counting, thereby makes that master spare low-order pointer processing module mould 4 multi-frames counting is in full accord.
7. the method for claim 1 is characterized in that: frame count is counted according to the multiframe alignment signal position indication separately of master spare low-order pointer processing module just can realize that mould 4 frame counts are in full accord.
8. the method for claim 1, it is characterized in that: the time that the time control signal of the counter of synchronous payload buffer becomes a frame by time of a frame deducts 6 continuous clock pulse, and these 6 burst lengths are used for transmitting the 2 bit counter control informations that realize synchronous mould 4 multi-frames counting.
9. the method for claim 1, it is characterized in that: in order to reduce the number of signals that connects between the master spare low-order pointer processing module, the buffer control information of TU12 tributary unit payload and the control information of TU3 tributary unit payload buffer of low-order pointer processing module that to transfer rate is the Synchronous Transport Module level-N of 2488.320Mbit/s adopt time-multiplexed mode, and a promptly main synchronous control signal of exporting with the low-order pointer processing module has comprised the TU12 tributary unit payload buffers all in the low-order pointer processing module of the Synchronous Transport Module level-N that four transfer rates are 622.080Mbit/s and synchronizing information and system's multi-frame counter synchronisation information of TU3 tributary unit payload buffer.
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| CN (1) | CN1819499B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000074283A1 (en) * | 1999-05-28 | 2000-12-07 | Fujitsu Limited | Sdh transmitter and method for switching frame timing in sdh transmitter |
| CN1555168A (en) * | 2003-12-24 | 2004-12-15 | 烽火通信科技股份有限公司 | Damage-free switching method for main and spare synchronous digital series device timing source |
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2006
- 2006-01-06 CN CN 200610000174 patent/CN1819499B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000074283A1 (en) * | 1999-05-28 | 2000-12-07 | Fujitsu Limited | Sdh transmitter and method for switching frame timing in sdh transmitter |
| CN1555168A (en) * | 2003-12-24 | 2004-12-15 | 烽火通信科技股份有限公司 | Damage-free switching method for main and spare synchronous digital series device timing source |
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| Publication number | Publication date |
|---|---|
| CN1819499A (en) | 2006-08-16 |
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