KR0171765B1 - Board switching method of lsmb - Google Patents

Abstract

The present invention relates to a board switching method of a low-speed multiplexer in a synchronous transmission device. When a forced board transfer command is input, it is determined whether the high-speed multiplexing board (HSMB) is all hernias. ; Determining whether the transfer target board is the same type as the spare board if all of the hernias are not hernia, and stopping the transfer if the types are not the same; If the type is the same, it is determined whether the forced transfer is already performed and if it is already done, stopping the transfer (202); If it is not forced transfer, determining whether manual transfer or hernia transfer is performed (203); If the transfer is made, returning the transfer (204); Performing forced transfer if no transfer is made (205); And setting 206 a lockout variable to improve the reliability of the circuit.

Description

Board Switching Method of Low Speed Multiplexer in Synchronous Transmission System

1 shows a general synchronous multiplexing structure.

2 is an STM-n frame format of a general synchronous digital hierarchy.

(A) of FIG. 3 shows the section overhead (SOH) of the frame format shown in FIG.

(B) of FIG. 3 shows the path overhead (POH) of the frame format shown in FIG.

4 is an example of a ring photology of an optical synchronous transmission apparatus to which the present invention is applied.

5 is an example of a synchronous transmission apparatus to which the present invention is applied.

6 is a board mounting diagram of a synchronous multiplexing self according to the present invention.

7 is a flowchart illustrating a board transfer method according to the present invention.

8 is a detailed flowchart of the board transfer shown in FIG.

9 is a detailed flowchart of the board transfer recovery shown in FIG.

10 is a detailed flowchart of circuit transfer recovery shown in FIGS. 8 and 9.

* Explanation of symbols for main parts of the drawings

10,20,30,40: Node S: Service Line

P: Reserve Line T: Optical Transmitter

R: Optical receiver 11,21,31,41: Multiplexing device

111: low speed multiplexer switching unit 112: low speed multiplexer

113: high speed multiplexer 114: network node matcher

115: clock supply 116: multiplexing control unit

117: system control unit 118: network control unit

119: mating line matching unit 120: mating board

121: Alarm

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous optical transmission device. In particular, up to 84 or 2.048 Mbps signals (hereinafter referred to as DS1E), which are conventional asynchronous signals, are referred to as a maximum of 84 or 2.048 Mbps signals (hereinafter referred to as DS1E), and 44.736 Mbps signals (hereinafter referred to as DS3). The present invention relates to a board switching method of low-speed multiplexing in an optical transmission device that accommodates up to three signals, multiplexes the STM-1 signal as the basis in a synchronous digital network, and then performs optical transmission.

In general, a synchronous optical transmission device converts an asynchronous multiplexed signal (for example, DS1, DS1E) into an optical signal in an optical transmitter, transmits the optical signal to an opposite station through an optical cable, and transmits the optical signal received from the other station to an optical receiver. After converting the signal to a synchronous demultiplexing to output an asynchronous demultiplexed signal, a process of forming a STM-n frame by synchronous multiplexing the asynchronous multiplexed signal is illustrated in FIG. 1. In FIG. 1, AM denotes an asynchronous multiplexing process, SM denotes a synchronous multiplexing process, and multiplexes in the direction of the arrow to form an STM-n frame. For example, a DS-1 frame is mapped to a box (C: Container) to be C-11, and when a path overhead (POH: Path OverHead) is added, the DS-1 frame is a virtual box (VC) VC-11, and a pointer thereon. If PTR is added, it becomes TU-11. In addition, 'TU-11 is grouped into four groups and multiplexed into VC-3 and VC-4 in the form of a hierarchical signal unit group (TUG-2), and VC-3 is multiplexed through the management unit (AU) AU-3. It becomes Management Unit Group (AUG) and finally STM-1. At this time, the European DS1E is mapped to C-12, and then a path overhead (POH) is added to form the virtual box VC-12.

Here, the box (C) is a basic unit constituting the synchronous multiplexing structure, and the existing asynchronous digital hierarchical signals are synchronously multiplexed by being mapped into the corresponding box, and correspond to C-1, C-2, C-3, There is C-4, and C-1 is again divided into C-11 to map North American DS1 and C-12 to map European DS1E. The virtual box VC is a signal unit for supporting a connection between path layers in synchronous transmission, and the level signal unit TU is a lower path layer VC-1, VC-2 and an upper path layer VC-. Pointer is used to adapt 3, VC-4), and the hierarchy signal unit group (TUG) combines one or more hierarchy unit signals (TU) and aligns them at a predetermined position in the upper VC payload space. The management unit (AU) is used as an AU pointer as a signal unit to provide the adaptive function between the upper path layer and the multiplexer section layer, and the management unit group (AUG) combines one or more signals of the management unit (AU) to pay STM. It is aligned at a fixed position in space.

Figure 2 illustrates the STM-1 frame format of a general synchronous digital hierarchy, which occupies 9 rows and 270 columns of bytes for 125 [mu] sec and has a transmission rate of 9 x 270 x 8 x 8 Kbps = 155.550 Mbps. Here, 9x9 bytes are the section overhead (SOH) and AU pointer space, and 9x261 bytes are the payload space. In the 9x9 byte, 3x9 (a) is the player section overhead, 1x9 (b) is the AU pointer, and 5x9 (c) is the multiplexer section overhead. The payload space may be loaded with one VC-4 or three VC-3s. The VC-3 includes 9 × 1 path overhead (d: POH).

(A) of FIG. 3 is a section overhead (SOH) of the frame format shown in FIG. 2, with rows 1 to 3 being the player section overhead, row 4 to the AU pointer, row 5 to 9 the multiplexer section. Is overhead. In (a) of FIG. 3, the player section overhead is the section overhead checked for each player, and 'A1' and 'A2' are frame alignment codes for identifying the boundary of the STM frame, and 'A1' = 11110110, ' A2 '= 00101000,' B1 'is Bit Interleaved Parity (BIP) byte for player interval error monitoring, and' D1, D2, D3 'are data communication channels that can be used in the player interval. (DCC: Data Communication Channel), the capacity of each channel is 64 Kbps, so the total capacity of the player section data communication channel is 192 Kbps. 'E1' is an orderwire that can be used for voice communication in the player section, 'F1' is a user channel for users such as network operators, and 'X' is assigned to be defined and used in each country. Space.

The multiplexer section overhead is the section overhead identified for each multiplexer and is transparently passed in the players, and consists of B2, D4 to D12, E2, K1, K2, Z1, and Z2. 'B2' is the bit-changing even-check byte for the error detection function of the multiplexing section, and 'D4 to D12' is the data communication channel (DCC) for the multiplexer section, and the total capacity is 576 Kbps. 'E2' is a short circuit that can be used for voice communication in the multiplexer section, and 'K1, K2' are assigned for APS as APS (Automatic Protection Switching) channels, and 'K2' is an alarm display signal ( It is used for displaying interval maintenance signal such as AIS (Alarm Indication Signal) and FERF, and 'Z1 and Z2' are reserved bytes for future use.

The path overhead (POH) has a high path overhead and a low path overhead. FIG. 3 (b) is a high path overhead (POH) of the frame format shown in FIG. Path overhead attached to the high-level virtual box, VC-3 and VC-4, located in the first column of VC-3 or VC-4, consisting of J1, B3, C2, G1, F2, H4, Z3 to Z5. 'B3' is the bit shift even check byte for path error monitoring function, 'C2' is the signal label to indicate the configuration of VC-3 / VC-4, and 'F2' is for communication between path devices. 'G1' is a channel for informing the VC-3 / VC-4 sender of the path status and performance at the VC-3 / VC-4 receiver, and 'H4' is used for multi-frame display of component payloads. Used. The lower path overhead is a path overhead (POH) attached to the lower virtual box, VC-1, VC-2, and is denoted as 'V5' as the first byte of VC-11, VC-12, and VC-2. It consists of BIP-2, FEBE, PT, L1-L3, and FERF.

The general description of such a synchronous transmission method is described in detail in pages 101 to 234 of the book Broadband Information Communication, co-authored by Lee Byung-ki and two others.

However, in order to improve the reliability of the service in the synchronous optical transmission apparatus using the synchronous transmission scheme, it is necessary to design a redundant circuit or a redundant board.

Accordingly, an object of the present invention is to provide a low speed multiplexer board switching method for switching over to a spare board when an error occurs in a DS1 or DS1E low speed multiplexing board.

In order to achieve the above object, the present invention is provided with a low-speed multiplexing board and a high-speed multiplexing board provided with at least one or more spare boards to form a synchronous transmission module (STM) by synchronously multiplexing predetermined asynchronous multiplexed signals. A synchronous multiplexing device comprising: determining whether a high speed multiplexing board (HSMB) is all hernias when a forced board transfer command is input, and stopping the transfer if all are hernias; If all are not hernias, determining whether the transfer target board is the same type as the spare board, and if the type is not the same, stopping the transfer; If the type is the same, determining whether a forced transfer is already made and if so, stopping the transfer; Determining whether manual transfer or hernia transfer is performed if forced transfer is not performed; If the transfer is made, returning the transfer; Performing forced transfer if there is no transfer; And setting a lockout variable.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

First, an example of configuring a ring network having four nodes using a synchronous optical transmission apparatus to which the present invention is applied is as shown in FIG. 4, as shown in FIG. It consists of the station D (40), and each station is provided with two optical transmitters and multiplexers / demultiplexers and a ring is formed by two lines. In FIG. 2, S denotes a service line currently in use, P denotes a reserve line, and a signal transmission direction is in the opposite direction to the service line.

That is, the station A 10 multiplexes its own station signal with the relay signal received from the station D 40 through the receiver 13 or from the station B 20 through the receiver 14, and then the transmitter 12. Converts the optical signal to the station B 20 through the service line S, and converts the optical signal from the transmitter 15 to the station D 40 through the preliminary line P, respectively. 20) multiplexes the relay signal received from the station A 10 through the receiver 23 or the station signal received from the station C 30 through the receiver 24 and its own station signal, and then converts the transmitter 22 into an optical signal. By converting the optical signal from the transmitter 25 to the station C through the service line (S), and transmits to the station A (10) via the preliminary line (P), respectively. The signal transmission in the station C and the D is the same as the signal transmission in the A and B stations.

In this ring structure, each node is composed of one master station and the other slave stations, and all nodes can be equally master stations, and the master stations receive and reserve service lines (S). (P) The sending side should be cut off (called S-cut) or service line (S) transmission, and the reserve line (P) receiving side should be cut off (called P-cut). Both transmission and reception of line P must be connected.

As shown in FIG. 5, a synchronous multiplexer to which the present invention is applied (hereinafter, since multiplexing of a transmission process in the present invention includes demultiplexing in a reception process, multiplexing and demultiplexing are simply referred to as multiplexing). Low Speed Multiplexer Switching Unit (LPSB: 111), Low Speed Multiplexer (LSMB: 112), High Speed Multiplexer (HSMB: 113), Network Node Matcher (NNIB: 114), Clock Supplyer (STGB: 115), Multiplexing Control Unit ( CPCB: 116, System Control Unit (SPCB: 117), Network Control Unit (DCCB: 118), Matching Line Matching Unit (OWIB: 119), Matching Board (TEL: 120), Alarm (ALU: 121). The signal DS1 or DS1E is converted and inversely converted into the STM-1 signal which is a synchronous multiplexed signal.

In FIG. 5, a clock supplier (STGB) 115 generates and supplies a clock and timing necessary for a system, and a system controller (SPCB) 117 is in charge of controlling and monitoring the entire system, and a network controller (DCCB: 118) accesses the OAM data by the TMN protocol to the parameters of the large or remote station and provides communication over the DCC channel. The low speed multiplexer (LSMB: 112) consists of six operation boards and one spare board, so that the synchronous multiplexing / demultiplexing of the DS1 signal to the TUG2 signal is connected, and the high speed multiplexer (HSMB: 113) connects up to 21 TUG signals. Synchronous synchronization / demultiplexing with VC-3 and AUG signals. In addition, the low speed multiplexer switching unit (LPSB) 111 is composed of relays for switching a 7: 1 circuit and a 6: 1 board (or unit) to improve the availability and reliability of a service channel. The switch is performed according to the transfer command of: 116, and the network node matching device (NNIB: 114) connects the AUG signal to generate and insert a section overhead (SOH) to form an STM-1 signal to connect to the optical device and restore the clock. It also performs a scramble function to make it smooth. And the other line matching unit (OWIB: 119) performs the function of connecting the other line to the network through the system control unit 117, two-wire interface function, multi-party call configuration function, call setup internal function, E1 / E2 selection Function and the like, and the alarm 121 processes the alarm according to the control of the system control unit 117. On the other hand, the system control unit 117 and the network control unit 118 is connected to the terminal equipped with the GU1 function, the matching line matching unit 119 is connected to the matching board (TEL), the network node matching unit 114 is STM -1 Send and receive signals to the service line and the reserve line, respectively.

FIG. 6 is a board mounting diagram of a multiplexing shelf to which the present invention is applied, and one low-speed multiplexing switching board (LPSB-1, LPSB-2, and LPSB-3) and seven low-speed multiplexing boards (LSMB-S) are included in one multiplexing shelf. LSMB-6, two high speed multiplexing boards (HSMB-1, HSMB-2), multiplexing control boards (CPCBs), two network node matching boards (NNIB-1, NNIB-2), system control boards (SPCB) ), And a network control board (DCCB) is mounted.

In FIG. 6, one low speed multiplexer switching board (LPSB) is responsible for two low speed multiplexing boards (LSMB), for example, the first switching board (LPSB-1) is the first and second low speed multiplexing board ( LSMB-1, LSMB-2), the second switching board LPSB-2 includes the third and fourth low speed multiplexing boards LSMB-3 and LSMB-4, and the third switching board LPSB-3 includes the third switching board LPSB-3. It handles the 5th and 6th low speed multiplexing boards (LSMB-5, LSMB-6) respectively and processes the circuit switching and board switching according to the transfer command of the multiplexing control board (CPCB).

In this circuit switching process, one low-speed multiplexing board (LSMB) handles four DS1 level channels, so a pair of low-speed multiplexing boards enables 7: 1 circuit switching, and the board switching is the first of seven low-speed multiplexing boards (LSMB). -S) is a spare board, so 6: 1 board switching is possible.

There are forced board transfer, manual board transfer, automatic board transfer, etc. The priority is board transfer. Manual board transfer is automatic board transfer.

7 is a flowchart illustrating a board switching method according to the present invention, when a forced board transfer command is input, determining whether all HSMB boards are hernias and stopping the transfers if all are hernias (200); Determining whether the transfer target board is the same type as the spare board if all of the hernias are not hernia, and stopping the transfer if the types are not the same; If the type is the same, it is determined whether the forced transfer is already performed and if it is already done, stopping the transfer (202); If it is not forced transfer, determining whether manual transfer or hernia transfer is performed (203); If the transfer is made, returning the transfer (204); Performing forced transfer if no transfer is made (205); And setting 206 a lockout variable.

That is, according to the present invention, if all of the high speed multiplexing boards are mounted, and the spare board of the low speed multiplexing board is the same type as the operation board to be transferred (for example, for DS1 or DS1E), if the forced transfer is not performed by checking whether forced transfer is performed, Perform forced board changeover according to 8 degree flow. At this time, if the transfer by manual or hernia is already made, the board transfer is returned according to the flow of FIG.

FIG. 8 is a detailed flowchart of the forced board transfer step 205 shown in FIG. 7, which determines whether the spare board is normal and stops the transfer if it is not normal; Checking whether the circuit is switched if it is normal (301); If circuit switching has occurred, returning the circuit switching (302); Disabling the CPU interrupt (303) to prevent interruption during board transfer after a circuit return or when no circuit transfer occurs; Copying the board operation information 304; Giving a transfer command to a low speed transfer processing (LPSP) chip (305); Confirming the success of the transfer operation (306); When the transfer is completed, a step 307 of releasing the CPU interrupt is configured.

That is, according to the invention, if the spare board is normal and the circuit is not switched, the operation board is copied after the operation information is copied. At this time, in the case of circuit switching, forced switching is performed after the circuit switching is restored in accordance with the flow of FIG.

FIG. 9 is a detailed flowchart of the board transfer recovery shown in FIG. 7, which includes determining whether a board to be returned is normal and stopping transfer if it is not normal; Checking whether the circuit is switched if the board to be returned is normal (401); If circuit switching has occurred, returning the circuit switching (402); Disabling the CPU interrupt (403) to prevent interruption during board transfer recovery if circuit transfer is returned or if circuit transfer is not performed; Copying the board operation information (404); Giving a return command to the low speed transfer processing (LPSP) chip (405); Confirming the success of the transferover (406); Enabling the CPU interrupt when the transfer is complete or the transfer is stopped, step 407.

That is, according to the present invention, if the board to be returned is normal and the circuit is not switched, the transfer operation is performed after copying the board operation information. At this time, if the circuit is switched, the board transfer is restored after performing the circuit transfer recovery in accordance with the flow of FIG.

FIG. 10 is a detailed flowchart of circuit switching recovery shown in FIGS. 8 and 9, comprising: disabling a CPU interrupt (500) to prevent interruption during circuit switching recovery; Determining whether the board with the returned circuit is normal and stopping transfer if it is not normal (501); Determining if the circuit to be returned is switched if the circuit to be returned is normal (502); Determining whether the HSMB is all hernias if the transfer is stopped, and if the hernias are stopped, stopping the transfer (503; determining whether the lockout is engaged if not all hernias) and stopping the transfer recovery if the lockout is engaged. (504): if a lockout is not engaged, giving a return command to a low speed transfer processing (LPSP) chip (505); copying circuit operation information (506); confirming the success of the transfer recovery (507); Enabling 508 to interrupt the CPU when the transfer is complete or the transfer is stopped.

That is, in the circuit transfer return step according to the present invention, if the board to which the circuit to be returned belongs is normal and the HSMB is not all mounted, the circuit transfer is returned and the circuit operation information is copied if the lockout is not engaged.

As described above, if an abnormality occurs in the low speed multiplexing board in operation according to the present invention and the board forced replacement is performed, the reliability of the important channel may be improved by performing the board switching after reverting the low priority board transfer that is already being transferred. It can be effective.

Claims (4)

In a synchronous multiplexing device including a low speed multiplexing board having at least one spare board and a high speed multiplexing board to synchronously multiplex predetermined asynchronous multiplexed signals to form a synchronous transmission module (STM), a forced board transfer command is input. Determining whether the high speed multiplexing board (HSMB) is all hernias; Determining whether the transfer target board is the same type as the spare board if all of the hernias are not hernia, and stopping the transfer if the types are not the same; If the type is the same, it is determined whether the forced transfer is already performed and if it is already done, stopping the transfer (202); If it is not forced transfer, determining whether manual transfer or hernia transfer is performed (203); If the transfer is made, returning the transfer (204); Performing forced transfer if no transfer is made (205); And setting a lockout variable (206). A method of board switching of a low speed multiplexer in a synchronous transmission device. In FIG. 1, the forced board transfer step 205 includes determining whether the spare board is normal and stopping the transfer if it is not normal (300); Checking whether the circuit is switched if it is normal (301); If circuit switching has occurred, returning the circuit switching (302); Disabling the CPU interrupt (303) to prevent interruption during board transfer after a circuit return or when no circuit transfer occurs; Copying the board operation information 304; Giving a transfer command to a low speed transfer processing (LPSP) chip (305); Confirming the success of the transfer operation (306); And a step (307) of releasing the CPU interrupt when the switching is completed. The method of claim 1, wherein the board transfer recovery step (204) comprises: determining whether the board to be returned is normal and stopping the transfer transfer if it is not normal (400); Checking whether the circuit is switched if the board to be returned is normal (401); If circuit switching has occurred, returning the circuit switching (402); Disabling the CPU interrupt (403) to prevent interruption during board transfer recovery if circuit transfer is returned or if circuit transfer is not performed; Copying the board operation information (404); Giving a return command to the low speed transfer processing (LPSP) chip (405); Confirming the success of the transferover (406); And (407) enabling CPU interrupts when transfer is complete or when transfer is stopped. 4. The method of claim 2, wherein the circuit transfer recovery step comprises: disabling a CPU interrupt (500) to prevent interruption during circuit transfer recovery; Determining whether the board with the returned circuit is normal and stopping transfer if it is not normal (501); Determining if the circuit to be returned is switched if the circuit to be returned is normal (502); Determining whether the HSMB is all hernias if the transfer is stopped, and if the hernias are stopped, stopping the transfer (503; determining whether the lockout is engaged if not all hernias) and stopping the transfer recovery if the lockout is engaged. (504): if a lockout is not engaged, giving a return command to a low speed transfer processing (LPSP) chip (505); copying circuit operation information (506); confirming the success of the transfer recovery (507); And (508) enabling CPU interrupts when transfer is complete or when transfer is stopped.