CN115963891A - Method, apparatus, storage medium, and device for synchronous serial communication delay compensation - Google Patents
Method, apparatus, storage medium, and device for synchronous serial communication delay compensation Download PDFInfo
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- CN115963891A CN115963891A CN202211728429.3A CN202211728429A CN115963891A CN 115963891 A CN115963891 A CN 115963891A CN 202211728429 A CN202211728429 A CN 202211728429A CN 115963891 A CN115963891 A CN 115963891A
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Abstract
The invention relates to the technical field of communication, in particular to a synchronous serial communication delay compensation method.A compensation clock after line delay compensation is generated in a host, the compensation clock is clk _ compensation, and the starting time of the clk _ compensation is the same as the edge time of the starting bit of received data, so that the compensated clock clk _ compensation is used for receiving the data sent by a slave, and the data sent by the slave can be accurately received without calculating the specific time of line delay; and because each communication is real-time compensation, even if the same host product uses different baud rates at different moments, the data can be correctly read. The invention is generally used for different synchronous serial communication products, has strong compatibility and can greatly improve the speed and the physical line length of the synchronous serial communication.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method for compensating synchronous serial communication delay.
Background
The synchronous serial communication has the characteristics that the wiring is simple (a clock line and a data line), each bit of data is transmitted according to the clock frequency strictly during communication, and errors are not easy to occur, so that the synchronous serial communication has very wide application, and for example, encoders with communication protocols of SSI and BISS-C are developed based on the synchronous serial communication.
With the development of the technology, more and more data are communicated, the communication speed is higher and higher, and the physical line of communication is longer and longer. Since the master and the slave of the synchronous serial communication both receive and transmit data strictly according to the clock transmitted by the master, the longer the physical line is, the larger the line delay of the communication line is, and when the time of the line delay exceeds the transmission time of one bit, the master receives erroneous communication data. This phenomenon becomes more remarkable as the communication speed increases (the transmission time per bit becomes shorter).
Disclosure of Invention
The invention provides a method for compensating synchronous serial communication delay aiming at the problems in the prior art, which can generate a compensation clock of line delay in real time according to received data, sample the received data through the compensation clock, is not influenced by the line delay and can ensure the accuracy of the received data.
In order to solve the technical problem, the first aspect of the present invention discloses the following technical solutions: a method of synchronous serial communication delay compensation, comprising the steps of:
the master sends a communication request to the slave, the sending clock of the communication is CLK1, the slave sends DATA according to the received master communication request and is set as DATA DATA1, wherein the clock used by the slave to receive the master communication request is CLK2, and the period of the clock CLK1 and the clock CLK2 is t;
the method comprises the steps that a host receives sending DATA from a slave, the received DATA is set as DATA DATA2, the edge time of a start bit of the DATA DATA2 is T0, and the DATA DATA2 comprises a start bit, a DATA bit and a stop bit;
the host generates a compensated clock clk _ compensation of the line delay, wherein the clock cycle of the compensated clock clk _ compensation is T, and the starting edge time is T0;
after the host receives the start bit of the DATA DATA2, the host continues to send a communication request according to the sending clock CLK1 for the slave to send DATA, and simultaneously receives the sampling DATA DATA2 according to the generated compensation clock CLK _ compensation;
when the stop bit of the DATA2 is received, the master stops transmission of the communication request to the slave.
Preferably, the generation of the compensation clock clk _ compensation is stopped after the host receives the stop bit of the DATA 2.
Preferably, the DATA1 includes a 1-bit start bit, a Nbit DATA bit and a 1-bit stop bit, and the DATA2 includes a 1-bit start bit, a Nbit DATA bit and a 1-bit stop bit, wherein an edge of the start bit of the DATA1 is t1, and an edge of the start bit of the DATA2 is t2.
Preferably, the number of the compensated clock clk _ compensation of the line delay generated by the host is (1 + N + 1) bit.
Preferably, when the start edge time of the transmission clock CLK1 is T0, T0= T0+ T1+ T2.
The second aspect of the invention discloses a communication device, which comprises a host and a slave connected with the host by signals;
the host is used for sending a communication request clock to the slave, receiving data from the slave by the host after the slave receives the communication request clock and sends data to the host, generating a compensation clock according to the initial time of the received data, and sampling the received data by the host by using the compensation clock.
A third aspect of the present invention discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method for synchronous serial communication delay compensation described above.
The fourth aspect of the present invention discloses an electronic device, wherein the electronic device includes:
a processor; and (c) a second step of,
a memory arranged to store computer executable instructions that, when executed, cause the processor to perform a method of synchronous serial communication delay compensation as described above. The invention has the beneficial effects that:
the invention provides a synchronous serial communication delay compensation method, which is characterized in that a compensation clock clk _ compensation after line delay compensation is generated in a host, the starting time of the compensation clock clk _ compensation is the same as the edge time of the starting bit of received data, so that the compensated clock clk _ compensation is used for receiving the data sent by a slave, and the data sent by the slave can be accurately received without calculating the specific time of line delay; and because each communication is real-time compensation, even if the same host product uses different baud rates at different moments, the data can be correctly read. The invention is universal for different synchronous serial communication products, has strong compatibility and can greatly improve the speed and the physical wire length of the synchronous serial communication.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a schematic diagram of synchronous serial communication ignoring line delay;
FIG. 3 is a schematic diagram of synchronous serial communication with line delay;
FIG. 4 is a schematic diagram of synchronous serial communication after line delay compensation according to the present invention.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present invention is further described below with reference to the following examples and the accompanying drawings, which are not intended to limit the present invention. The present invention is described in detail below with reference to the attached drawings.
The first embodiment is as follows:
the method for compensating synchronous serial communication delay provided by the embodiment, as shown in fig. 1 and 4, includes the following steps:
s1, the master sends a communication request to the slave, a sending clock of communication is CLK1, the slave sends DATA according to the received master communication request and is set as DATA DATA1, wherein a clock used by the slave to receive the master communication request is CLK2, and the period of the clock CLK1 and the clock CLK2 is t; wherein, the DATA DATA1 comprises a 1-bit start bit, an Nbit DATA bit and a 1-bit stop bit; since the master transmits the clock CLK1 to the slave, this process takes a certain time, and thus a first line delay has been generated in this process, the clock CLK2 actually received from the slave is delayed from the transmission clock CLK1 of the master as shown in fig. 4.
S2, the host receives the sending DATA from the slave, the received DATA is set as DATA DATA2, the edge time of the start bit of the DATA DATA2 is T0, and the DATA DATA2 comprises a start bit, a DATA bit and a stop bit; wherein, since the DATA2 is DATA transmitted from the slave, it is the same as the DATA1, i.e. the DATA2 includes a 1-bit start bit, a Nbit DATA bit and a 1-bit stop bit, except that, in the process from the slave transmitting the DATA1 to the host receiving, a second line delay is generated so that the DATA2 is delayed from the DATA1, and thus the present embodiment is represented by the DATA1 and the DATA2, both of which are shown in fig. 4.
S3, generating a compensation clock clk _ compensation of line delay by the host, wherein the clock cycle of the compensation clock clk _ compensation is T, and the starting edge time is T0; when the compensation clock clk _ compensation is a virtual clock generated in real time when the host receives DATA, the host generates a compensation clock clk _ compensation having the same edge timing as the start bit of the DATA2 at the same time when the host receives the DATA2 (although there is a delay, the host does not sample the DATA yet), and the DATA2 is sampled by the compensation clock clk _ compensation, for example, the DATA is sampled at the rising edge of the compensation clock clk _ compensation, as shown in fig. 4, since a clock signal generated after the compensation clock compensates the first line delay and the second line delay can keep consistency with the DATA2, the DATA can be read according to the compensation clock clk _ compensation without calculating the line delay time, without being affected by the line delay, and the accuracy of the read DATA can be ensured.
S4, after the host receives the start bit of the DATA DATA2, the host continues to send a communication request according to the sending clock CLK1 for the slave to send DATA, and simultaneously receives the sampling DATA DATA2 according to the generated compensation clock CLK _ compensation;
and S5, after the stop bit of the DATA DATA2 is received, the host stops sending a communication request to the slave and also stops generating the compensation clock clk _ compensation, so that the waste of resources of the host is avoided, in the embodiment, as long as the compensation clock clk _ compensation is continuously generated between the start bit and the stop bit of the DATA DATA2, that is, the number of the compensation clocks is consistent with the number of bits of the DATA DATA2, for example, the number of the compensation clocks clk _ compensation in the embodiment is (1 + N + 1) bit.
Optionally, the method steps of this embodiment are all implemented in an FPGA.
Specifically, in the present embodiment, a compensated clock CLK _ compensation after line delay compensation is generated inside the host, and the start time of the compensated clock CLK _ compensation is the same as the edge time of the start bit of the received DATA, so that the DATA transmitted from the slave can be received by the compensated clock CLK _ compensation, and the DATA transmitted from the slave can be accurately received without calculating the specific time of the line delay, for example, when the start edge time of the transmission clock CLK1 is T0, the edge time of the start bit of the DATA1 is T1, and the edge time of the start bit of the DATA2 is T2, the start time T0= T0+ T1+ T2 of the clock CLK _ compensation after line delay compensation. Because the communication of each time is real-time compensation, even if the same host product uses different baud rates at different moments, the data can be correctly read, and because the theoretical line delay is eliminated, the communication speed and the communication physical line length can be set and used at will by users as long as the method is supported by a hardware circuit.
As shown in fig. 2, the synchronous serial communication in which the line delay is ignored is schematically illustrated, and under this condition, the start edge timing of the transmission clock CLK1 is t0, the edge timing of the start bit of the DATA1 is t1, and the edge timing of the start bit of the DATA2 is t2, which are the same, that is, at the same timing.
Further, when the schematic diagram of the synchronous serial-parallel line after the actual line delay is taken into account is shown in fig. 3, at this time, the host receives the DATA2 through two line delays, and when the line delay increases, the transmission clock CLK1 of the host samples the DATA2, which may exceed one bit, and the situation may occur that the start bit is not read or the DATA bit at the rear is directly read.
Therefore, the present embodiment compensates the line delay generated in the above two transmission and reception processes to generate a real-time compensated clock clk _ compensation, as shown in fig. 4, which is a schematic diagram of the clock and signal for DATA transmission and reception in the present embodiment, the compensated clock clk _ compensation is synchronized with the received DATA2, and the DATA2 is read according to the compensated clock clk _ compensation, so that the accuracy of the DATA can be ensured without considering whether there is more than one bit in the two previous line delays. Therefore, the embodiment is generally applied to different synchronous serial communication products, has strong compatibility, and can greatly improve the speed and the physical line length of the synchronous serial communication.
Example two:
the communication device for synchronous serial communication delay compensation provided by the embodiment comprises a host and a slave connected with the host through signals; the host is used for sending a communication request clock to the slave, receiving data from the slave by the host after the slave receives the communication request clock and sends data to the host, generating a compensation clock according to the initial time of the received data, and sampling the received data by the host by using the compensation clock.
Specifically, the host can realize a product of synchronous serial communication, and the host has two clock signals, one is a transmission clock CLK1 for requesting data, and the other is a real-time compensation clock CLK _ compensation generated after receiving data of the slave, wherein the transmission clock CLK1 is used for transmitting a communication request to the slave, the compensation clock CLK _ compensation is used for reading data received from the slave, and the compensation clock CLK _ compensation is consistent with the received data, so that the host can accurately read data fed back by the slave without being influenced by delay of a physical line.
Example three:
the present embodiment discloses a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform the steps of the method for synchronous serial communication delay compensation described in the first embodiment.
Example four:
the present embodiment discloses a computer program product comprising a non-transitory computer readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform some or all of the steps of the method for synchronous serial communication delay compensation described in the first embodiment.
Example five:
the electronic device disclosed in this embodiment, wherein the electronic device includes:
a processor; and a memory arranged to store computer executable instructions (program code), which may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. The memory has a memory space for storing program code for performing any of the method steps in the embodiments. For example, the memory space for the program code may comprise respective program codes for implementing the respective steps in the above method, respectively. The program code can be read from or written to one or more computer program products. These computer program products comprise a program code carrier such as a hard disk, a Compact Disc (CD), a memory card or a floppy disk. Such a computer program product is typically the computer-readable storage medium of embodiment four. The computer-readable storage medium may have storage sections, storage spaces, and the like similarly arranged as the memory in the electronic device of the present embodiment. The program code may be compressed, for example, in a suitable form. In general, the memory unit stores program code for performing the steps of the method according to the invention, i.e. program code readable by a processor such as the like, which, when run by an electronic device, causes the electronic device to perform the individual steps of the method described above.
Although the present invention has been described with reference to the above preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A method of synchronous serial communication delay compensation, comprising the steps of:
the master machine sends a communication request to the slave machine, the sending clock for communication is CLK1, the slave machine sends DATA according to the received master machine communication request and is set as DATA DATA1, the clock used by the slave machine for receiving the master machine communication request is CLK2, and the period of the clock CLK1 and the clock CLK2 is t;
the method comprises the steps that a host receives sending DATA from a slave, the received DATA is set as DATA DATA2, the edge time of a start bit of the DATA DATA2 is T0, and the DATA DATA2 comprises a start bit, a DATA bit and a stop bit;
the host generates a compensated clock clk _ compensation of the line delay, wherein the clock cycle of the compensated clock clk _ compensation is T, and the starting edge time is T0;
after the host receives the start bit of the DATA DATA2, the host continues to send a communication request according to the sending clock CLK1 for the slave to send DATA, and simultaneously receives the sampling DATA DATA2 according to the generated compensation clock CLK _ compensation;
when the stop bit of the DATA2 is received, the master stops transmission of the communication request to the slave.
2. The method of claim 1, wherein the method further comprises: after the host receives the stop bit of the DATA2, the generation of the compensation clock clk _ compensation is stopped.
3. The method of claim 1, wherein the method further comprises: the DATA1 includes a 1-bit start bit, a Nbit DATA bit, and a 1-bit stop bit, and the DATA2 includes a 1-bit start bit, a Nbit DATA bit, and a 1-bit stop bit, where an edge time of the start bit of the DATA1 is t1, and an edge time of the start bit of the DATA2 is t2.
4. A method for synchronous serial communication delay compensation according to claim 3, wherein: the number of compensated clocks clk _ compensation for the line delay generated by the host is (1 + N + 1) bit.
5. A method for synchronous serial communication delay compensation according to claim 3, wherein: when the start edge of the transmission clock CLK1 is T0, T0= T0+ T1+ T2.
6. A communication device according to claim 1, characterized in that: the system comprises a host and a slave connected with the host through signals;
the host is used for sending a communication request clock to the slave, receiving data from the slave by the host after the slave receives the communication request clock and sends data to the host, generating a compensation clock according to the initial time of the received data, and sampling the received data by the host by using the compensation clock.
7. A computer-readable storage medium, characterized in that: the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the method of synchronous serial communication delay compensation of any of claims 1-5.
8. An electronic device, wherein the electronic device comprises:
a processor; and the number of the first and second groups,
a memory arranged to store computer executable instructions that when executed cause the processor to perform a method of synchronous serial communication delay compensation as claimed in any of claims 1-5.
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| CN116996156A (en) * | 2023-09-28 | 2023-11-03 | 成都天锐星通科技有限公司 | Sampling clock signal compensation method and device and phased array panel antenna |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116996156A (en) * | 2023-09-28 | 2023-11-03 | 成都天锐星通科技有限公司 | Sampling clock signal compensation method and device and phased array panel antenna |
| CN116996156B (en) * | 2023-09-28 | 2023-12-29 | 成都天锐星通科技有限公司 | Sampling clock signal compensation method and device and phased array panel antenna |
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