JP5804930B2 - Serial communication method, communication apparatus, and serial communication system - Google Patents

Description

  The present invention relates to a serial communication method, a communication device, and a serial communication system for reading and writing data between a master side and a slave side.

  When serial communication is performed between semiconductor devices such as microcomputers (hereinafter referred to as microcomputers) for embedded devices, the serial communication unit (frame) is often performed in a relatively small communication unit of 8 bits or 16 bits. In many cases, the number of bits in the communication unit matches the number of data bits handled by the microcomputer. For example, in the case of an 8-bit microcomputer, one frame is usually 8 bits.

In the case of reading out 8-bit data in such a semiconductor device that performs full-duplex synchronous communication composed of 8 bits per frame, conventionally, the procedure is as follows.
In the first frame, address data is transmitted from the master side device to the slave side device, and in the second frame, read data of the received address is transmitted from the slave side to the master side.
The address data is assumed to be composed of a maximum 7-bit address and 1-bit R / W control information for controlling read (R) or write (W). In the case of a number of addresses, a frame is added.

  In addition to this, when performing error detection / correction processing in order to improve communication quality, the master side requires errors such as parity and CRC (Cyclic Redundancy Check) necessary for error detection / correction processing of read data. It is necessary to obtain detection / correction information. However, since 1 frame ≤ number of data bits, error detection / correction information cannot be mixed in the second frame, so error detection / correction is performed from the slave side to the master side in the newly added third frame. Information will be sent separately.

  As described above, when performing error detection / correction processing, an extra communication for one frame is required to transmit error detection / correction information, and the time from the read request to the completion of communication is increased up to 1.5 times. There was a problem that would become. In order to solve this problem, a method for shortening the communication time when performing error checking / correction processing has been trial and error. For example, in Patent Document 1, a parity signal for request in full-duplex asynchronous communication and The data signal was superimposed and transmitted. However, since the communication system of Patent Document 1 is an asynchronous system and multi-value processing by superposition is necessary, in order to realize a conventional synchronous communication system with a low-cost (binary) digital dedicated circuit. It cannot be applied as it is.

JP 2006-246394 A

  As described above, the conventional full-duplex synchronous communication system has a problem that the communication time is increased by the number of frames added for communicating error detection / correction information. In particular, when the communication speed is slow, the addition of useless frames increases the communication time in milliseconds, so it is desired that the communication be completed with as few frames as possible.

  The present invention has been made to solve the above-described problems. By completing communication including error detection information in a communication time of 2 frames, the conventional 3 frames can be reduced to 2 frames. An object of the present invention is to provide a serial communication method, a communication apparatus, and a serial communication system with high communication reliability capable of shortening communication latency for a frame and increasing a communication band.

  The serial communication method according to the present invention is a serial communication method of a communication device connected by serial data lines for transmitting and receiving data signals and performing full-duplex communication, wherein the number of bits of a frame as a communication unit is the master side and If the number of data bits of each communication device on the slave side matches or is smaller than the number of data bits, a frame including the address information of the read data is transmitted from the master side to the slave side, and the address on the slave side At the time when the information is received, the read data is read to obtain information for error detection or correction and returned to the master side in the same frame, and read from the slave side to the master side in the first phase And a second phase for transmitting a frame including the read data.

  A serial communication method according to the present invention is a serial communication method of a communication device connected by a serial data line for transmitting and receiving data signals to perform serial communication, wherein the number of bits of a frame as a communication unit is set on the master side and the slave side When the number of data bits of each communication device is equal to or smaller than the number of data bits, write data address information from the master side to the slave side and information for error detection or correction of the write data are displayed. The first phase for transmitting the included frame and the second phase for transmitting the frame including the write data from the master side to the slave side are provided.

  The communication device according to the present invention is a communication device that is connected by a serial data line that transmits and receives data signals and performs full-duplex communication, and the number of bits of a frame as a communication unit is different between each communication on the master side and the slave side. When the number of data bits matches the number of data bits of the device, or when the number of data bits is smaller than the number of data bits, the master side communication device transmits a frame including address information of read data to the slave side in the first phase, and A frame including information for error detection or correction of the read data is received from the slave side, and a frame including the read data is received from the slave side in the second phase.

  The communication device according to the present invention is a communication device that performs serial communication by being connected by a serial data line that transmits and receives data signals, and the number of bits of a frame that is a communication unit of each of the communication devices on the master side and the slave side If the number of data bits matches or is less than the number of data bits, the master side communication device, in the first phase, writes the address information of the write data and information for error detection or correction of the write data. Is transmitted to the slave side, and in the second phase, the frame including the write data is transmitted to the slave side.

  The communication device according to the present invention is a communication device that is connected by a serial data line that transmits and receives data signals and performs full-duplex communication, and the number of bits of a frame as a communication unit is different between each communication on the master side and the slave side. When the number of data bits matches the number of data bits of the device, or when the number of data bits is smaller than the number of data bits, the communication device on the slave side receives a frame including address information of read data from the master side in the first phase, and When the address information is received, the read data is read and information for error detection or correction is obtained and transmitted to the master side in the same frame. In the second phase, the read data read in the first phase is included. The transmitted frame is transmitted to the master side.

  The communication device according to the present invention is a communication device that performs serial communication by being connected by a serial data line that transmits and receives data signals, and the number of bits of a frame that is a communication unit of each of the communication devices on the master side and the slave side If the number of data bits matches or is less than the number of data bits, the slave side communication device detects the address information of the write data and the error detection or correction of the write data from the master side in the first phase. In the second phase, a frame including the write data is received from the master side.

  The serial communication system according to the present invention performs serial communication between the communication device on the master side and the communication device on the slave side.

  According to the present invention, at the time of a read operation, the address information is transmitted from the master side, and the slave side performs read processing from the address up to the last bit of this frame and obtains information for error detection or correction. Because full-duplex communication was used, data was returned to the master during the same frame, and the data read earlier in the next frame was sent to the master. Communication including detection / correction information can be completed. Accordingly, there are provided a serial communication method, a communication apparatus, and a serial communication system with high communication reliability that can reduce the communication latency for one frame and increase the communication band by reducing the conventional three frames to two frames. be able to.

  Also, according to the present invention, during the write operation, the master side sends the write data address and information for error detection or correction first, and sends the write data in the next frame. Then, when write data is received, error detection processing can be performed using the received error detection or correction information, and the result can be returned to the master side in the same frame. The communication including the error detection / correction information of the write data can be completed. Accordingly, there are provided a serial communication method, a communication apparatus, and a serial communication system with high communication reliability that can reduce the communication latency for one frame and increase the communication band by reducing the conventional three frames to two frames. be able to.

It is a block diagram which shows the structure of the serial communication system which concerns on Embodiment 1 of this invention. 3 is a diagram illustrating a communication frame configuration of the serial communication system according to Embodiment 1. FIG. 4 is a timing chart of the slave device according to the first embodiment and shows a write operation. 4 is a timing chart of the slave device according to the first embodiment and shows a read operation. 3 is a flowchart showing an operation of the slave device according to the first embodiment.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of the serial communication system according to the first embodiment. The serial communication system of the illustrated example includes a master device 100 and a slave device 200. Between the master device 100 and the slave device 200, a serial clock line (SCLK terminal) for inputting a serial clock and two serial data lines ( The SDI terminal for data input and the SDO terminal for data output are connected by a total of three lines, and full-duplex communication using SPI (Serial Preferential Interface) is performed.

In the following, an 8-bit microcomputer is used for the master device 100, and the communication unit (frame) is 8 bits in accordance with this specification. The slave device 200 is a peripheral device such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array).
In addition, the following three phases, which are configured by one communication unit (one frame), are defined. Details of each phase will be described later.
(1) Address set phase (AS phase)
(2) Write data phase (WD phase)
(3) Read data phase (RD phase)
The read / write operation from the master device 100 to the register (not shown) of the slave device 200 is realized by a two-phase operation of AS phase + RD phase or a two-phase operation of AS phase + WD phase. Therefore, the two-phase operation requires a communication time of two 8-bit communications (that is, two frames).

  The master device 100 generates a clock signal for synchronizing communication between the serial communication unit 110 that performs serial communication with the slave device 200, the master device main processing unit 120 that is a microcomputer core, and the slave device 200. And a clock generation unit 130 for generation. The serial communication unit 110 on the master side is a communication circuit that performs SPI full-duplex communication, and includes a shift register 111 that operates at a timing synchronized with a clock signal output from the clock generation unit 130. Note that data exchange between the serial communication unit 110 and the master device main processing unit 120 may be performed via an internal bus interface (not shown).

The shift register 111 stores parallel data (address, R / W control information, write data, etc.) input from the master device main processing unit 120 side, converts it into serial data, and outputs it from the SDO terminal bit by bit. . The shift register 111 stores serial data (such as read data) input from the SDI terminal, converts it into parallel data, and outputs the parallel data to the master device main processing unit 120.
The master device main processing unit 120 calculates the parity of the data to be transmitted to the slave device 200 and outputs it to the shift register 111, and acquires the parity included in the data received from the slave device 200 and performs a parity check.

  The slave device 200 includes a serial communication unit 210 that performs serial communication with the master device 100 and a slave device main processing unit 220 that is a microcomputer core. The slave-side serial communication unit 210 is a communication circuit that performs SPI full-duplex communication, and includes a reception shift register 211 that operates at a timing synchronized with a clock signal input from the master-side serial communication unit 110, and a transmission data selector. 212 and a state transition control unit 213. Note that data exchange between the serial communication unit 210 and the slave device main processing unit 220 may be performed via an internal bus interface (not shown).

The reception shift register 211 stores serial data (address, R / W control information, write data, parity, etc.) input from the SDI terminal, converts it into parallel data, and outputs it to the slave device main processing unit 220. The transmission data selector 212 is selected from among parallel data (such as read data) input from the slave device main processing unit 220, data stored in the reception shift register 211, and parity check results input from the slave device main processing unit 220. The data according to the selection signal of the state transition control unit 213 is selectively acquired, converted into serial data, and output bit by bit from the SDO terminal.
The slave device main processing unit 220 calculates the parity of the data to be transmitted to the master device 100 and outputs it to the transmission data selector 212, and obtains the parity included in the data received from the master device 100 and performs a parity check.
The state transition control unit 213 determines the read / write operation and the phase type based on the data of each bit input from the SDI terminal, and receives a selection signal (address information or write information) predetermined for each bit. The data is output to the transmission data selector 212 and the slave device main processing unit 220.

(1) AS Phase FIG. 2A is a diagram illustrating the frame configuration of the AS phase. 3 and 4 are timing charts of the slave device 200. FIG. 3 shows the AS phase and WD phase during the write operation, and FIG. 4 shows the AS phase and RD phase during the read operation. As shown in FIG. 3, the slave device 200 detects the signal at the SDI terminal at the falling edge of the clock signal in synchronization with the clock signal input from the SCLK terminal, and the SDO terminal at the falling edge of the clock signal. Output from. On the other hand, master device 100 detects the signal at the SDI terminal at the timing indicated by the broken line in FIGS.

  In the AS phase, data is transmitted in the order of bits 0 to 7 from the SDO terminal on the master side to the SDI terminal on the slave side. Bit 0 is a start bit (value is 0). Bits 1 to 4 are an address (4 bits) of a read / write operation target register. Bit 5 is R / W control information for designating either a read / write operation, and is 1 for a read operation and 0 for a write operation. Bit 6 is an AS parity (in this case, odd) of the upper 5 bits of the AS phase (address 4 bits and R / W control information 1 bit). In order to check on the slave side whether the address request is correct or not. Information to be used. Bit 7 is a WD parity (in this case, odd) of write data (8 bits) transmitted in the WD phase during a write operation, and is information used to check whether the write data received on the slave side is correct. is there. In the first embodiment, the parity for WD is transmitted in advance in the AS phase preceding the WD phase. On the other hand, transmission of parity is not necessary in the AS phase during the read operation.

  Simultaneously with the transmission from the master side to the slave side, data is transmitted in the order of bits 0 to 7 from the SDO terminal on the slave side to the SDI terminal on the master side. Bits 0 to 5 may be any value, for example, the upper 6 bits received by the slave side in the previous phase as dummy data are returned as they are. Bit 6 is RD parity of read data (8 bits) transmitted in the RD phase during the read operation, and is obtained by reading the read data in the cycle of bit 5 in the AS phase. In the first embodiment, RD parity is transmitted in advance in the AS phase preceding the RD phase. On the other hand, transmission of parity is not necessary in the AS phase during the write operation. Bit 7 is information indicating the parity check result of the address received on the slave side. The address and R / W control information received in the AS phase are also used as the AS parity received in the AS phase. This is a parity check (5 if there is no error) in 5 cycles.

  In the AS phase, an address etc. is transmitted from the master side to the slave side, and a parity check of this address etc. is performed on the slave side and returned, but the address etc. is packed on the first bit side of the frame, On the slave side, when reception of the address is completed, the data at that address is read from the slave device main processing unit 220 in advance (timing indicated by the solid arrow in FIG. 4), parity check is performed, and the result is returned in the same phase. It becomes possible to do. Details will be described later.

(2) WD Phase FIG. 2B is a diagram for explaining a frame configuration of the WD phase.
In the WD phase following the AS phase, data is transmitted in the order of bits 0 to 7 from the SDO terminal on the master side to the SDI terminal on the slave side. Bits 0 to 7 are write data (8 bits) for writing to the address specified in the previous AS phase.
Simultaneously with the transmission from the master side to the slave side, data is transmitted in the order of bits 0 to 7 from the SDO terminal on the slave side to the SDI terminal on the master side. However, bits 0 to 5 may be any value, for example, the upper 7 bits received by the slave side in the previous phase as dummy data are returned as they are. Bit 7 is information indicating the parity check result of the write data received on the slave side, and the write data received in the WD phase is used in the cycle of bit 7 by using the WD parity received in the previous AS phase. Parity check (1 if there is no error).

(3) RD Phase FIG. 2C is a diagram for explaining the frame configuration of the RD phase.
In the RD phase following the AS phase, data is transmitted in the order of bits 0 to 7 from the SDO terminal on the master side to the SDI terminal on the slave side. However, the bits 0 to 7 may be any value.
Simultaneously with the transmission from the master side to the slave side, data is transmitted in the order of bits 0 to 7 from the SDO terminal on the slave side to the SDI terminal on the master side. Bits 0 to 7 are read data (8 bits) read from the register at the address specified in the previous AS phase.

  In the master device 100 shown in FIG. 1, the serial communication unit 110 may have the same hardware configuration as that required for conventional SPI communication. However, software processing is different from conventional SPI communication. In the conventional SPI communication, the address and the R / W control information are transmitted in the first frame as described above. In the first embodiment, the first frame is obtained by obtaining the parity for AS and the parity for WD. In the (AS phase), in addition to the address and R / W control information, an AS parity and a WD parity are also transmitted.

In the other slave device 200, the serial communication unit 210 is newly provided with a transmission data selector 212 and a state transition control unit 213 in addition to the hardware configuration necessary for conventional SPI communication.
Hereinafter, the operation of the entire serial communication system including the master device 100 will be described focusing on the operation of the slave device 200 including the transmission data selector 212 and the state transition control unit 213.

First, the write operation will be described, and then the read operation will be described.
In the AS phase during the write operation, in the master device 100, the master device main processing unit 120 calculates the AS parity from the write data address and the R / W control information, and outputs it to the shift register 111. The WD parity is calculated from the data and output to the shift register 111.
The shift register 111 stores the address and R / W control information output from the master device main processing unit 120, the parity for AS, and the parity for WD in bits 1 to 7. Bit 0 is a start bit.
The serial communication unit 110 outputs the clock signal generated by the clock generation unit 130 from the SCLK terminal, and outputs the 8-bit data stored in the shift register 111 from the SDO terminal in synchronization with the clock signal (AS phase). ).

  FIG. 5 is a flowchart showing the operation of the slave device 200. Steps ST1 to ST8 are processing on the reception side, and steps ST11 to ST18 are processing on the transmission side. Transmission / reception between the master device 100 and the slave device 200 is performed in synchronization with the clock signal at the SCLK terminal. Further, the processes in steps ST21 to ST24 are various internal processes, and are performed according to an instruction from the state transition control unit 213.

In the serial communication unit 210 of the slave device 200, the state transition control unit 213 detects the start bit of bit 0 input from the SDI terminal (step ST1 “YES”), and determines the start of the AS phase. The received data of bit 0 is stored in the reception shift register 211.
On the other hand, the state transition control unit 213 that has detected the start bit outputs a selection signal to the transmission data selector 212, and the transmission data selector 212 selects the upper 1 bit of the previous reception data stored in the reception shift register 211. Then, it is transmitted as dummy data from the SDO terminal to the master device 100 (step ST11).

The serial communication unit 210 receives the address of bits 1 to 4 and the R / W control information of bit 5 from the master device 100 and stores them in the reception shift register 211 (steps ST2 and ST3).
On the other hand, the state transition control unit 213 continues to output a selection signal to the transmission data selector 212, and the transmission data selector 212 selects bits 1 to 5 of the previous reception data stored in the reception shift register 211 to obtain dummy data. Transmission is performed from the SDO terminal to the master device 100 (step ST12).
Further, the state transition control unit 213 notifies the slave device main processing unit 220 of the address of bits 1 to 4 stored in the reception shift register 211 in advance, and the slave device main processing unit 220 reads during the AS phase. Data is read and RD parity is calculated (steps TT21 and ST22).

The serial communication unit 210 receives the AS parity of bit 6 from the master device 100 and stores it in the reception shift register 211 (step ST4).
On the other hand, the state transition control unit 213 determines whether to write or read according to the R / W control information. In the case of writing, the state transition control unit 213 continues to output a selection signal to the transmission data selector 212, and the transmission data selector 212 is stored in the reception shift register 211. Bit 6 of the previously received data that has been received is selected and transmitted as dummy data from the SDO terminal to master device 100 (step ST13). Processing in the case of reading will be described later. In the case of writing, the RD parity obtained in step ST22 is not necessary.
Further, the slave device main processing unit 220 acquires data from the reception shift register 211, and performs parity check of the address and the R / W control information using the AS parity (step ST23).

The serial communication unit 210 receives the WD parity of bit 7 from the master device 100 and stores it in the reception shift register 211 (step ST5).
On the other hand, the state transition control unit 213 outputs a selection signal to the transmission data selector 212 so as to acquire the parity check result of the address from the slave device main processing unit 220. The transmission data selector 212 acquires the parity check result of the address calculated by the slave device main processing unit 220 in step ST23, and transmits the result as bit 7 from the SDO terminal to the master device 100 (step ST14).

On the other hand, the master device 100 transmits data such as an address from the shift register 111 to the SDO terminal, and also receives upper 7-bit dummy data and an address parity check result from the SDI terminal, and sends them to the shift register 111. Store (AS phase). The stored 8-bit data is output to master device main processing unit 120.
Subsequently, 8-bit write data is output from the master device main processing unit 120 to the shift register 111, and the shift register 111 outputs from the SDO terminal (WD phase).

In the RD phase, in the slave device 200, the state transition control unit 213 determines whether to read or write according to the R / W control information stored in the reception shift register 211, and outputs the determination result to the master device main processing unit 120 ( Step ST6). This time for writing (step ST6 “Write”), write data is received from the SDI terminal, stored in the reception shift register 211, and 8-bit write data is output to the slave device main processing unit 220. The slave device main processing unit 220 writes the write data to the address specified in the AS phase (step ST7).
Also, the slave device main processing unit 220 acquires the write data of 7 bits already stored in the reception shift register 211 and 1 bit received by this clock for a total of 8 bits in step ST5 of the AS phase. A parity check is performed using the stored WD parity (step ST24).

  The serial communication unit 210 can receive correct write data when it is determined that the parity check result at step ST23 is an error and the correct address request cannot be received, and when the parity check result at step ST24 is an error. In either one or both of the cases where it is determined that there is no data, the write request to the slave device main processing unit 220 may be stopped to protect the register data.

  Further, the state transition control unit 213 determines that the transition from the AS phase to the WD phase has been made (step ST15 “Write”), and outputs a selection signal to the transmission data selector 212. The transmission data selector 212 then transfers to the reception shift register 211. The upper 7 bits of the previously received data stored are selected and transmitted as dummy data from the SDO terminal to the master device 100 (step ST16). Further, the state transition control unit 213 outputs a selection signal to the transmission data selector 212 so as to acquire the parity check result of the write data from the slave device main processing unit 220. The transmission data selector 212 acquires the parity check result of the write data calculated by the slave device main processing unit 220 in step ST24, and transmits it as bit 7 from the SDO terminal to the master device 100 (step ST17).

  On the other hand, the master device 100 transmits write data from the shift register 111 to the SDO terminal, and also receives the upper 7-bit dummy data and the parity check result of the write data from the SDI terminal and stores them in the shift register 111. (WD phase). The master device 100 performs a predetermined response such as repeating the write operation according to the parity check result.

Next, the read operation will be described.
In the AS phase during the read operation, in the master device 100, the master device main processing unit 120 calculates the AS parity from the read data address and the R / W control information in the same manner as in the AS phase of the write operation. To 111.
The shift register 111 stores the address and R / W control information output from the master device main processing unit 120 and the parity for AS in bits 1 to 6. Bit 0 is a start bit and bit 7 is not required.
The serial communication unit 110 outputs the AS phase frame stored in the shift register 111 in synchronization with the clock signal.

The serial communication unit 210 of the slave device 200 performs steps ST1 to ST5, ST11, ST12, and ST23 as described above. Here, the description will focus on steps that are different from those in the write operation.
In the AS phase during the read operation, when the address of bits 1 to 4 is received in step ST2, the slave device receives the notification from the state transition control unit 213 while receiving the following R / W control information and AS parity. The processing unit 220 acquires the read data at this address (step ST21) and calculates the parity (step ST22).

  In subsequent step ST13, since the R / W control information is read, the state transition control unit 213 outputs a selection signal to the transmission data selector 212 so as to obtain the RD parity from the slave device main processing unit 220 in the case of reading. . Then, the transmission data selector 212 acquires the RD parity calculated by the slave device main processing unit 220 in step ST22 and transmits it as the bit 6 from the SDO terminal to the master device 100.

On the other hand, in the master device 100, data such as an address is transmitted from the shift register 111 to the SDO terminal, and upper 6-bit dummy data, RD parity, and address parity check result are transmitted from the SDI terminal to the shift register 111. Are received and stored. The stored 8-bit data is output to master device main processing unit 120.
Subsequently, the shift register 111 outputs dummy data from the SDO terminal in synchronization with the clock signal (RD phase).

In the RD phase, in the slave device 200, the state transition control unit 213 determines whether to read or write according to the R / W control information stored in the reception shift register 211 (step ST6). This time for reading (step ST6 “Read”), dummy data is received from the SDI terminal and stored in the reception shift register 211 (step ST8).
Further, the state transition control unit 213 determines that the transition from the AS phase to the RD phase has been made (step ST15 “Read”), and outputs a selection signal to the transmission data selector 212. The transmission data selector 212 performs the slave device main processing unit. Read data output from 220 is transmitted from the SDO terminal to master device 100 (step ST18).

  On the other hand, the master device main processing unit 120 of the master device 100 uses the RD parity acquired in advance in the previous AS phase, and is input from the SDI terminal in the current RD phase and stored in the shift register 111. Parity check is performed on the read data (RD phase). The master device 100 performs a predetermined response such as repeating a read operation according to the parity check result.

As described above, according to the first embodiment, during the read operation of the serial communication system that performs the synchronous full-duplex serial communication, the frame including the read data address from the master device 100 to the slave device 200 in the AS phase. When the address is received, the slave device 200 reads the read data, obtains the parity for RD, returns it to the master device 100 in the same frame, and in the subsequent RD phase, from the slave device 200 to the master device 100. A frame including read data read in the AS phase is transmitted to the frame. For this reason, the communication including the parity for RD (information for error detection) is completed in the communication time of 2 frames of the AS phase and the RD phase by transmitting the parity for RD before the RD phase. it can. Therefore, the parity check can be started immediately on the master side without separately communicating a frame with only parity. In addition, communication reliability can be improved. Therefore, it is possible to shorten the communication latency for one frame (up to about 30% reduction) and increase the communication band by reducing the conventional 3 frames to 2 frames, and further, it is required for applications where real-time processing is important. Response time can be shortened.
That is, assuming that the communication speed is 9600 bps and the operation frequency of the microcomputer core is 4 MHz, the communication pulse width of 1 bit is 1 sec / 9600 = about 104 μsec, and the operation cycle of the microcomputer core is 1 sec / 4,000,000 = 250 nsec (0.25 μsec).
When transmitting / receiving a data frame of 1 byte = 8 bits, according to the conventional method, the communication time can be obtained as 104 μsec × 8 bits × 3 frames = 2696 μsec, but the communication time in the present invention is 104 μsec × 8 bits. Since × 2 frames = 1664 μsec, it is possible to reduce the communication latency by subtracting 2496-1664 = 832 μsec.
In a microcomputer core with an operating frequency of 4 MHz, this difference corresponds to 832 μsec / 250 nsec = 3328 cycles.
In other words, according to the present invention, processing of up to 3328 instructions to be executed after completion of communication can be executed in advance by reducing communication latency as compared with the conventional method.

  Further, according to the first embodiment, in the AS phase that is transmitted from the master device 100 to the slave device 200, the frame in which the address is packed ahead of the parity is transmitted. When the device 200 receives the address, the slave device main processing unit 220 can read the read data in advance and obtain and return the parity for RD.

  Further, according to the first embodiment, during the write operation of the serial communication system that performs synchronous full-duplex serial communication, in the AS phase, the address of the write data from the master device 100 to the slave device 200, and the parity for WD The frame including the write data is transmitted from the master device 100 to the slave device 200 in the subsequent WD phase. For this reason, in the write operation, the WD parity (information for error detection) is sent from the master side in the AS phase before the WD phase, the write data is sent in the subsequent WD phase, and the parity check result in the same frame Thus, the communication including the parity check result of the parity for WD can be completed in the communication time of two frames of the AS phase and the WD phase. Therefore, communication reliability can be improved. In addition, it is possible to reduce the communication latency for one frame and increase the communication band by reducing the number of frames from the conventional 3 frames to 2 frames, and further, it is possible to reduce the response time required for applications where real-time processing is important. .

Note that the number of bits of a frame, which is a communication unit, is the same as the number of data bits of the master device 100 and the slave device 200 or less than the number of data bits in both the read operation and the write operation.
Here, the number of data bits of the master device 100 and the slave device 200 represents the width of data that can be processed at one time in each device in terms of the number of bits. For example, only 8 bits can be calculated at a time. Those having 8 bits of data bits and those capable of performing operations of 32 bits have 32 data bits.
There are products such as 32-bit microcomputers with an external data bus width of 16 bits, such as a 32-bit microcomputer with fewer input / output bits than the internal data bus width. The details of explanation are omitted.

  Further, during the write operation, it is not necessary to read the read data in advance as in the read operation, so that the transmission data selector 212 and the state transition control unit 213 can be omitted. In this case, the reception shift register 211 is used in the same manner as the shift register 111, and the received data is serial / parallel converted and output to the slave device main processing unit 220, and the data output from the slave device main processing unit 220 is also output. May be parallel / serial converted and transmitted to the master device 100.

Note that the write operation is not limited to full-duplex serial communication, but may be half-duplex or unidirectional serial communication.
Further, the order of the AS phase and the WD phase may be reversed. That is, the master device 100 during the write operation first receives write data for writing to the slave device 200 from the master device main processing unit 120 in the WD phase and transmits it from the shift register 111 to the slave device 200, and in the subsequent AS phase. The frame including the address of the write data and the WD parity obtained by the master device main processing unit 120 is transmitted from the shift register 111 to the slave device 200. The other slave device 200 first receives a frame including write data to be written to the slave device main processing unit 220 from the master device 100 in the WD phase. In the subsequent AS phase, the address and WD of the write data from the master device 100 are received. The slave device main processing unit 220 received the WD parity received in the AS phase using the WD parity received in the WD phase and included the parity check result. The frame is configured to be transmitted to the master device 100. Even in this case, highly reliable communication including WD parity can be completed in a communication time of 2 frames.
It is assumed that the number of bits of a frame that is a communication unit matches the number of data bits of master device 100 and slave device 200 or is smaller than the number of data bits.

  Further, according to the first embodiment, in the AS phase transmitted from the master device 100 to the slave device 200, the master device 100 generates a frame including the address, the R / W control information, and the AS parity. In particular, the address is arranged so as to be packed on the first bit side of the shift register 111. Therefore, in this AS phrase, the slave device 200 can perform the parity check of the address using the AS parity, and return the check result. Therefore, in the communication time of 2 frames, communication including not only the parity of the read data or the write data but also the parity of the address can be completed. Thereby, in addition to shortening the communication time, the communication reliability can be further improved.

  Also, according to the first embodiment, the slave device 200 detects an error in the error detection process of the address and R / W control information using the AS parity, and writes the write data using the WD parity. The writing of the write data is stopped in one or both of cases where an error is detected in the error detection process. For this reason, by preventing writing of the write data value received in error on the slave device 200 side, it is possible to prevent the occurrence of malfunction due to erroneous setting / control.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to the configuration of the above-described embodiment, and the design does not depart from the gist of the present invention. Needless to say, changes and the like are included in the present invention.
For example, in the first embodiment, one master device 100 and one slave device 200 are used, but a plurality of slave devices 200 may be used.
For example, although a general-purpose microcomputer is used as the master device 100, the invention is not limited to this, and the slave device 200 may be used as the master device 100. In the case of this configuration, a plurality of slave devices 200 each including the clock generation unit 130 may be prepared, and one of the clock generation units 130 may be activated to transmit a clock signal to another slave device 200.
Further, for example, the error detection process for each of the address, read data, and write data is performed. However, the present invention is not limited to this, and an error correction may be performed in addition to error detection.

In the first embodiment, a serial clock line that transmits a physically existing clock signal and a serial data line that transmits and receives a data signal synchronized with the clock signal are used. There is no need to synchronize the clock, and the data may be encoded in synchronization with the clock on the transmission side, and the clock may be regenerated from the data signal on the reception side by a clock recovery circuit or the like, thereby internally synchronizing. Absent.
Further, the serial data line has been described as two data input SDI terminal and data output SDO terminal, but for the purpose of speeding up communication, for example, the same technology can be used even if two or more data lines are used. Needless to say, the present invention can be applied according to a specific idea.

DESCRIPTION OF SYMBOLS 100 Master apparatus 110,210 Serial communication part 111 Shift register 120 Master apparatus main process part 130 Clock generation part 200 Slave apparatus 211 Reception shift register 212 Transmission data selector 213 State transition control part 220 Slave apparatus main process part

Claims (13)

In a serial communication method of a communication device connected by a serial data line for transmitting and receiving data signals and performing full duplex communication,
When the number of bits of a frame that is a communication unit matches the number of data bits of each communication device on the master side and the slave side, or less than the number of data bits,
Sending a frame including address information of read data from the master side to the slave side, and reading the read data at the time of receiving the address information on the slave side, information for error detection or correction A first phase for seeking and returning to the master in the same frame;
A serial communication method comprising: a second phase for transmitting a frame including the read data read in the first phase from the slave side to the master side. In a serial communication method of a communication device that performs serial communication connected by a serial data line that transmits and receives data signals,
When the number of bits of a frame that is a communication unit matches the number of data bits of each communication device on the master side and the slave side, or less than the number of data bits,
A first phase for transmitting a frame including address information of write data from the master side to the slave side and information for error detection or correction of the write data;
And a second phase for transmitting a frame including the write data from the master side to the slave side.   3. The serial communication according to claim 1, wherein in the first phase, a frame in which address information is packed is transmitted from the master side to the slave side from the information for error detection or correction. Method.   In the first phase, a frame including address information from the master side to the slave side, control information instructing whether to perform a read operation or a write operation, and the address information and information for error detection or correction of the control information The serial communication method according to claim 1, wherein the serial communication method is transmitted.   On the slave side, a frame including address information from the master side in the first phase, control information for instructing a read operation or a write operation, the address information and information for error detection or correction of the control information And performing error detection or correction processing on the address information and control information using information for error detection or correction, and returning the processing result to the master side in the same frame. Item 5. The serial communication method according to Item 4.   6. The serial communication method according to claim 5, wherein when an error is detected in error detection or correction processing for address information and control information of write data, writing of the write data can be stopped on the slave side.   On the slave side, error detection or correction processing is performed on the write data in the second phase, the processing result is returned to the master side in the same frame, and if an error is detected in the error detection or correction processing, 3. The serial communication method according to claim 2, wherein writing of write data can be stopped.   A frame including write data in the first phase is transmitted from the master side to the slave side, and a frame including address information of the write data and information for error detection or correction is transmitted in the second phase. The serial communication method according to claim 2, wherein: In a communication device that is connected by a serial data line that transmits and receives data signals and performs full-duplex communication,
When the number of bits of a frame that is a communication unit matches the number of data bits of each communication device on the master side and the slave side, or less than the number of data bits,
The communication device on the master side
In the first phase, a frame including address information of read data is transmitted to the slave side, and a frame including information for error detection or correction of the read data is received from the slave side,
In the second phase, the communication apparatus receives a frame including the read data from the slave side. In a communication device that performs serial communication connected by a serial data line that transmits and receives data signals,
When the number of bits of a frame that is a communication unit matches the number of data bits of each communication device on the master side and the slave side, or less than the number of data bits,
The master side communication device is:
In the first phase, a frame including address information of write data and information for error detection or correction of the write data is transmitted to the slave side,
In the second phase, the communication apparatus transmits a frame including the write data to the slave side. In a communication device that is connected by a serial data line that transmits and receives data signals and performs full-duplex communication,
When the number of bits of a frame that is a communication unit matches the number of data bits of each communication device on the master side and the slave side, or less than the number of data bits,
The communication device on the slave side
In the first phase, a frame including read data address information is received from the master side, and when the address information is received, the read data is read to obtain information for error detection or correction. To the master side during
In the second phase, a frame including the read data read in the first phase is transmitted to the master side. In a communication device that performs serial communication connected by a serial data line that transmits and receives data signals,
When the number of bits of a frame that is a communication unit matches the number of data bits of each communication device on the master side and the slave side, or less than the number of data bits,
The slave side communication device is:
In the first phase, a frame including address information of write data and information for error detection or correction of the write data is received from the master side,
In the second phase, the communication apparatus receives a frame including the write data from the master side.   A serial communication system that uses the communication device according to claim 9 or 10 as a master side and uses the communication device according to claim 11 or claim 12 as a slave side to perform serial communication between both communication devices.

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