JPH04120929A - Digital data transmission synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent taking a long time for recovering synchronism even when a data train is shifted in a synchronous state by transmitting a reset signal from a first or second synchronizing part turned to the synchronous state first to the correspondent second or first synchronizing part so that the counter side can be asynchronous. CONSTITUTION:A synchronizing bit detection circuit 2 is provided to detect the synchronizing bit of an input signal, and first and second synchronizing parts 10 and 11 are provided to detect coincidence/non-coincidence between the synchronizing bit and a generated frame synchronizing pulse and to change the frame synchronizing pulse while counting the front and rear protection of the detected signal. The first or second synchronizing part 10 or 11 turned to the synchronous state first transmits the reset signal to the correspondent second or first synchronizing part 11 or 11 so that the counter side can be asynchronous. Thus, even when one coincidence/non-coincidence detection circuit, 4b detects coincidence while another coincidence/non-coincidence detection circuit 4a executes front protection, rear protection is started, by which time from out-of-synchronism to the recovery of synchronism can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital transmission, and particularly to a synchronous circuit in digital disk transmission.

[Conventional technology]

The conventional synchronous circuit, as shown in FIG. 2, consists of a 1υ1 pit 1-detection circuit 21, a match/unmatch/number configuration circuit 23, a protection circuit 24, and a pulse generation circuit 25. The synchronous bit position in the data string of the input signal input from the input terminal 1 is detected by the synchronous bit detection circuit 21. Then, the coincidence/mismatch detection circuit 23 detects timing coincidence/mismatch between the output signal from the synchronization pin 1 detection circuit 21 and the frame synchronization pulse 28 from the pulse generation circuit 25 formed in a pinary count format. be exposed. If these signals continue to have discrepancies equal to the number of protective films in front, an out-of-synchronization state occurs. Further, when the synchronization bit detection circuit 2 detects a synchronization bit, the pulse generation circuit 25 is reset by the cent signal 29 from the protection circuit 24. The match/mismatch detection circuit 23 matches the synchronization hint position in the input data string with the Frame 1 and synchronization pulse positions of the signal from the pulse generation circuit 24. When the frame synchronization pulse 28 and the synchronization bit continue to match for the number of backward protective films, a synchronization state is established.

[Problem to be solved by the invention]

In this conventional synchronization circuit, when a discrepancy equal to the number of protective films in front of the signal is detected, the synchronization becomes out of synchronization. Further, when a synchronization error 1- is detected, the pulse generation circuit is reset, and a match corresponding to the number of protective films behind the signal B is detected, and a synchronization state is established. For this reason, in a synchronous state, when the phase of a data string is shifted, there is a drawback that it takes time to restore synchronization.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital data transmission synchronization circuit which eliminates such drawbacks and does not take much time to restore synchronization even if a data string deviates in a synchronized state.

[Means to solve the problem]

The digital data transmission synchronization circuit of the present invention includes a synchronization pin 1 to detection circuit that detects a synchronization bit of an input signal, and a detection circuit that detects coincidence or mismatch between the synchronization bit and a generated frame synchronization pulse, and and first and second counting backward protection and varying the frame sync pulse.
The first or second synchronization unit that has become synchronized first sends a reset signal to the corresponding second or first synchronization unit to make the other side out of synchronization.

Further, the digital data transmission synchronization circuit of the present invention includes a synchronization bit detection circuit that detects a synchronization bit of an input signal, and a signal in which a match or mismatch between the synchronization pin 1- and the generated frame 31J] pulse is detected. first and second synchronizers each having a protection circuit that receives the signal, counts forward and backward protection of this signal, and changes the frame synchronization pulse, and the first or second The synchronization unit protection circuit sends a reset signal to the protection circuit of the corresponding second or first synchronization unit to make the other side asynchronous.

Furthermore, the digital data transmission synchronization circuit of the present invention includes a synchronization bit detection circuit that detects a synchronization bit of an input signal, first and second pulse generation circuits that generate frame synchronization pulses, and a first coincidence/mismatch circuit that detects coincidence/mismatch with the frame synchronization pulse of the pulse generation circuit; and a second coincidence/mismatch circuit that detects coincidence/mismatch between the synchronization bit and the frame synchronization pulse of the second pulse generation circuit. counting the forward and backward protection of the signal detected by the match/mismatch circuit and the first match/mismatch circuit;
A first protection circuit that changes the frame synchronization pulse of the first pulse generation circuit, and counting forward and backward protection of the signal detected by the second coincidence/mismatch detection circuit, and generates the second pulse. and a second protection circuit that changes the frame synchronization pulse of the circuit, and the first or second protection circuit that has entered the synchronization state first is reset to the corresponding second or first protection circuit. Each time a signal is sent, the other side is brought into an asynchronous state.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

This digital data transmission circuit Jυ1 consists of a synchronization bit detection circuit 2, a first synchronization section 10, and a second synchronization section 11. The first synchronization section 10 has a pulse generation circuit 3a, a coincidence/mismatch detection circuit 4a, and a protection circuit 5a, and the second synchronization section 11 has a pulse generation circuit 3b, a coincidence/mismatch detection circuit 4b, It has a protection circuit 5b.

The synchronization bit detection circuit 2 detects a synchronization bit I in the data string of the input signal input from the input terminal 1, and sends it to the coincidence/mismatch detection circuits 4a and 4b.

The coincidence/mismatch detection circuits 4a and 4b respectively receive the synchronization bit from the synchronization focus detection circuit 2 and the pulse generation circuits 3a and 3.
Matching/mismatching with the frame synchronization pulse from b is detected.

The protection circuits 5a and 5b each correspond to the match/mismatch detection circuit 4.
Count the forward and backward protection for the output signals from a, 4b. In addition, in the asynchronous state, the pulse generation circuit 3a,
Change the phase of 3b.

In addition, in the synchronized state, the protection circuit on the side that is in the synchronized state sends the reset I/signal 12 to the protection circuit on the other side. Then, the protection circuit of the other party is brought into an asynchronous state.

The pulse generation circuits 3a and 3b are connected to the protection circuits 5, a, and 3b, respectively.
5b, and sends a frame synchronization pulse in the form of a binary counter to the coincidence/mismatch detection circuits 4a and 4b.

Next, the operation of this embodiment will be explained. In the out-of-synchronization state, the synchronization bit in the data string of the input signal input from the input terminal 1 is detected by the detection circuit 2 into the synchronization bin 1. The synchronization bit detected by the synchronization bit detection circuit 2 is detected by each coincidence/mismatch detection circuit 4a, 4b as to whether it matches or mismatches with the frame synchronization pulse from each pulse generation circuit 3a, 3b. Each of the protection circuits 5a and 5b includes a match/mismatch detection circuit 4a,
The protection circuit 5a or 5b that first detects the coincidence of the output signal of the output signal 4b for the number of protective films behind the protection circuit 5a or 5b enters the same 1υ1 state.

For example, one of the protection circuits 5a that has entered the synchronized state first sends out a reset signal 12 to the other protection circuit 5b. As a result, the other protection circuit 5b is fixed in an out-of-synchronization state and constantly changes the phase of the pulse generation circuit 3b.
A state is entered in which frame synchronization -, match, and mismatch are detected.

Next, in the synchronized state, if the phase of the data string of the input signal input from the input terminal 1 is shifted, the coincidence/mismatch detection circuit 4a of which the synchronized state is established causes the output from the pulse generation circuit 3a to be output from the pulse generation circuit 3a. A mismatch with the frame synchronization pulse is detected.

Then, the protection circuit 5a enters a forward protection state, and if a mismatch exceeding the number of protection stages is detected, the protection circuit 5a enters an out-of-synchronization state. Also, at this time, the reset signal for the other protection circuit 5b is released. In this state, if the coincidence/mismatch detection circuit 4b, which is not in the synchronized state, detects coincidence with the frame synchronization pulse from the pulse generation circuit 3b at a different phase from the pulse generation circuit 3a, The rear protection state is entered, and the protection circuit 5b detects coincidence for the number of rear protection films, and a synchronization state is entered. Then, a reset signal is sent to the other protection circuit 5a.

As explained above, the digital data transmission synchronization circuit of the present invention has a synchronization pin 1-1 for detecting the synchronization bit of an input signal.
A detection circuit, two systems of pulse generation circuits that are formed in the form of a binary counter and output frame pulses, and a coincidence/mismatch detection that detects coincidence/mismatch between the output of each of these pulse generation circuits and the output of the synchronization bit detection circuit. 2 circuits
It has two protection circuits that count forward and backward protection for the output signals of the system and each matching/mismatching circuit, and one protection circuit that is synchronized first will protect the other protection circuit. By resetting the circuit, it becomes out of synchronization.

〔Effect of the invention〕

As explained above, in the present invention, even if this coincidence/mismatch detection circuit detects a coincidence while the other coincidence/mismatch detection circuit detects a coincidence, backward protection is started. This has the effect of shortening the time required.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit block diagram showing an example of a conventional technique. 2...Synchronization bit detection circuit 3a, 3b...Pulse generation circuit 4a, 4b...Coincidence/mismatch detection circuit 5a, 5'b...
...Protection circuit 12...Reset signal agent Patent attorney Yoshiyuki Iwasa■

Claims (3)

[Claims] (1) A synchronization bit detection circuit detects a synchronization bit of an input signal, detects a match/mismatch between the synchronization bit and the generated frame synchronization pulse, counts forward and backward protection of the detected signal, and calculates the It has first and second synchronization sections that change synchronization pulses, and the first or second synchronization section that has entered the synchronization state first sends a reset signal to the corresponding second or first synchronization section. A digital data transmission synchronous circuit that makes the other side asynchronous. (2) A synchronization bit detection circuit detects a synchronization bit of an input signal, receives a signal in which a match/mismatch between the synchronization bit and a generated frame synchronization pulse is detected, and counts forward and backward protection of this signal. first and second synchronizers each including a protection circuit that changes the frame synchronization pulse, and the first or second synchronizer protection circuit that has entered the synchronization state first changes the corresponding second or second synchronization A digital data transmission synchronization circuit that sends a reset signal to the protection circuit of the first synchronization section to make the other side asynchronous. (3) A synchronization bit detection circuit that detects a synchronization bit of an input signal, first and second pulse generation circuits that generate a frame synchronization pulse, and a synchronization bit and a frame synchronization pulse of the first pulse generation circuit. a first coincidence/mismatch circuit that detects coincidence/mismatch between the synchronization bit and the frame synchronization pulse of the second pulse generation circuit;
a second match/mismatch circuit for detecting mismatch;
a first protection circuit that counts forward and backward protection of the signal detected by the coincidence/mismatch circuit and changes a frame synchronization pulse of the first pulse generation circuit; and a second coincidence/mismatch detection circuit. a second protection circuit that counts forward and backward protection of the detected signal and changes the frame synchronization pulse of the second pulse generation circuit, A digital data transmission synchronous circuit in which a protection circuit sends a reset signal to the corresponding second or first protection circuit to bring the other party into an asynchronous state.