JPH1051435A - Sampling synchronization system of pcm relay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold data concurrence by regarding an intermediate point between the transmission and reception of a sampling address in a common frame as the reference point of a sampling clock. SOLUTION: A master station generates information frames successively and sends them to a down route. The information frames reach a return station through respective remote stations and returns to the master station through an incoming route. A remote station gathers data for itself through the outgoing route and stores its information in an information frame through the outgoing route. A transmission delay measurement counter 10 generates superframe cycles for sampling one cycle of a system frequency as 12 divisions. Counters 13 and 15 latches the timing between the reception and transmission of sampling addresses in the incoming. A correction value calculation part 16 calculates the intermediate point of timing between the reception and transmission as the reference point of the sampling clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PC based on a network system comprising one master station, a plurality of remote stations and a serial transmission line connecting them.
The present invention relates to a sampling synchronization system in an M current operated relay.

[0002]

2. Description of the Related Art FIG. 11 shows an example of a transmission line configuration of a PCM current operated relay. In the figure, MS indicates a master station, and RS0 to RS4 indicate remote stations (slave stations). The master station (master station) MS
An information frame for exchanging data between all stations is continuously generated. The frame propagates the down route in the figure,
It reaches the return station RS4, from which it returns to the parent station MS via the up route.

[0003] When each frame is generated, the master station MS adds an ID to the frame. This ID is called a frame address and is stored in an information field. Each station recognizes a frame address to be accessed by itself and to store data. The station that has received a certain frame extracts the frame address from the information field and checks whether the frame should be accessed by the own station. If so, the information of the own station is stored in the frame.
Otherwise, transmit to the next station as it is.

The operation in which each station recognizes a frame address and stores data in each corresponding frame is called a data multiplexing method. Each station multiplexes data one after another in the frame sequence generated by the master station MS, and arrives at the return station RS4. Here, the data for all stations is in a state of being prepared.
The route so far is the down route.

[0005] The route from the return station RS4 to the return to the master station MS is the up route, and each station collects data for all stations. Uplink data that has reached the master station is discarded after data collection at the master station.

In this transmission system, information of each station is written in a prescribed format called a frame, and the other stations take in the information by reading the frame transmitted via the transmission path. FIG. 12 shows the frame format.

Referring to FIG. 12, a frame is a bit string according to HDLC or the like. The frame receiving unit recognizes the flag pattern at the head of the frame and sets this as the start of the frame. The flag pattern defines a unique bit string that does not appear in other parts. When the pattern appears in an information field or the like, a bit of "1" or "0" is inserted to ensure the uniqueness of the flag.

[0008] Information defined by specifications is assigned to the information field. The frame address FA is stored therein as the frame ID. As the frame address, a cyclic numerical value within a certain range is defined. The range depends on the logical meaning of the set of frames. The FCS is a redundant part for ensuring the reliability of the frame. A CRC code or the like is used.

FIG. 13 shows the basic configuration of each station. One station is an up and down route, and blocks (21 to 28) 2 in FIG.
Consists of a set. In the figure, reference numeral 21 denotes a serial data receiving unit which receives received data and a received clock. Reference numeral 22 denotes a data separation unit that creates timing based on the flag portion of the received clock frame and extracts an information field, FCS, and the like. Reference numeral 23 denotes an FA detection unit which compares the detected frame address FA with its own registration. Just down route. A reception buffer 24 stores data in the separated information field. Reference numeral 25 denotes a frame generation unit that continuously generates frames only for the master station downlink route.
Reference numeral 26 denotes a data multiplexing unit, which configures transmission data into a frame in HDLC format. Other station frames also pass.
A transmission buffer 27 stores transmission data to be stored in the own station multiplex frame. However, only the down route. Reference numeral 28 denotes a serial data transmitting unit for transmitting transmission data and a transmission clock.

FIG. 14 shows the flow of data multiplexing between stations. Data is collected on the down route and distributed on the up route. The determination is made at all terminals (stations) based on the distributed data. Transmission data format is HD
LC frame format. The multiplex system of this system uses a frame as a minimum unit.

[0011] The multiplexed _IX in FIG. 14 corresponds to one or more frames. (In some cases, two or more frames are multiplexed by one station.) The process of multiplexing, distribution, and determination for each route will be described below.

(1) Downlink route A route in which each station multiplexes data into frames.

The master station MS constantly generates frames based on the frame timing generated by itself, and transmits the frames to the downstream route.

As a result, multiplex timing (time slot in frame units) in the remote station is secured. Here, the master station itself may multiplex data.

The ID of the generated frame is a frame address in a frame unit.

After receiving these frames and establishing synchronization, the remote station RS detects a frame to be multiplexed by itself from a preset frame address, and multiplexes its own data.

In the flow of the frame that has reached the return station, data is multiplexed in the same manner as in the other stations and transmitted to the upstream route.

(2) Up route Each station distributes / determines multiplexed data for all stations.

The frame from the return station returns to the master station via each remote station. In each station, the received data is stored in a buffer and processed (determined) by the host computer in the terminal. Data that has reached the master station is discarded after being checked.

[0020]

In the above-mentioned conventional data transmission system, as a recovery at the time of transmission line failure,
The master station function is switched and information transparency is ensured by reconfiguring the transmission path. However, when the master station is switched, the upstream and downstream transmission paths are determined based on the temporary master station. The continuity of the transmission frame is lost. As a result, the sampling synchronization by the master station and the sampling synchronization time by the temporary master station are started from different phases.

That is, since there is no mechanism for synchronizing the clock source for sampling synchronization between the master station and the temporary master station, sampling synchronization is re-established. During this re-establishment, depending on how the time distortion of the sampling cycle occurs (a period that is not a fixed cycle exists), the processing performed in this sampling cycle is delayed, and a normal protection operation cannot be performed. There is fear.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a sampling period method in a PCM relay capable of performing a normal protection operation with a small time distortion of the sampling period. Is to provide.

[0023]

SUMMARY OF THE INVENTION The present invention provides a data multiplexing type PC based on a network system comprising a master station, a plurality of slave stations, and a serial transmission line connecting them.
In the sampling synchronization method in the PCM relay, which synchronizes the data sampling clock of the M current relay, the transmission delay time is measured for each station based on the transmission and reception of the sampling address in each common frame, and the intermediate point is set as the sampling clock. And a means for synchronizing the sampling clock with the reference clock by DPLL control of the base clock of the transmission rate and a means for subordinate synchronization.

The reference clock generating means is provided in a transmission delay measurement counter having a period of one superframe time for counting a base clock and a multiplexing unit for downlink data, and includes a sampling address in a common frame. Means for latching the sampling address value and the counter value at that time at the timing of transmitting the data, means for providing the sampling address value at the timing of separating the sampling address in the common frame provided in the uplink data separation unit, A means having a buffer corresponding to the sampling address value, a means for storing an average value of the count value at the time of occurrence of the interrupt as a correction value in a buffer pointed to by the sampling address corresponding to each interrupt, and the value of the buffer is set; Counter count value To match the set value may be configured by a comparator means for generating a reference clock.

In addition, a UL flag defined in the common frame is used in a handshake for starting multiplexing of valid terminal data to the master station, the UL flag is set to a ready state at the time of transmission, and the sampling address delay time is invalidated. Means to send a common frame by setting to
Using the UL flag defined in the common frame,
Among the sampling synchronization rules, it is preferable to provide a means for sending the UL flag in an unready state and sending the UL flag in a ready state when the sampling synchronization is completed.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

1. Basic method In the data and transmission system of the PCM current operation relay shown in FIG. 11, terminal data collected and distributed at each station is as follows:
Data concurrency is required. Simultaneity is the following 2
Is a point.

(1) Synchronize data sampling timing among all stations. (Synchronization up to sampling clock) (2) All terminals must multiplex terminal data collected at the same sampling clock edge into the same multiframe. (Data Synchronization) The above-described (1) is a reference clock that operates with a value calculated from the transmission delay time, and achieves inter-station synchronization by applying dependent synchronization to the sampling clock of the own station.

In order to realize the above (2), a numbering signal synchronized with the sampling signal is generated. When the data collection module of the own station receives this, both the sampling timing and the numbering can be recognized.

FIG. 2 shows the transmission time of the round trip from the master station to the return station. The frame transmitted from the master station at time t1 returns to the master station at time t2 via the loopback station. According to the transmission specifications, this intermediate point is the same for all stations. This point is defined as a sampling synchronization point, and is used as a reference for a sampling clock.

The transmission delay times t1 to t2 are measured based on the transmission and reception of the sampling address (SA) in each common frame. Since the transmission interval of the common frame is equal to the sampling interval (has a different phase), a sampling (SP) synchronization point for all SAs can be determined to generate a sampling clock reference signal synchronized between all stations.

Each station has a sampling clock oscillator. By subjecting this to subordinate synchronization with a reference clock, a data sampling signal at the same timing at each station can be obtained.

This signal is a sampling synchronizing signal (SY
NC1). Since one cycle of the system frequency is sampled 12 times, numbers 0 to 11 are assigned to these.
Therefore, it is asserted in synchronization with every twelfth SYNC1. The SYNC4 signal (sampling synchronization numbering signal) is defined.

The relay module of each station uses SYNC1 as a sampling trigger and uses SYNC4 to determine the order. S
A tag of sampling number # 0 is attached to the sampling data at SYNC1 when YNC4 is asserted. Thereafter, if the timing at which the tag # 0 for adding the sequential tags up to 11 to the sampling data is first added is adjusted in all the stations, data synchronization can be ensured.

FIG. 1 shows a main circuit block of the sampling synchronous system. In FIG. 1, reference numeral 1 denotes a reference clock generator that generates a reference clock for phase comparison, 2 denotes a clock source that generates a base clock (1.544 MHz) to be subjected to slave synchronization, and 3 denotes a phase comparison with the reference clock. A slave synchronization unit 4 that divides the clock and outputs a slave synchronization signal is a SYNC signal generation unit that generates an SP synchronization signal from the divided output and the SYNC4 forced synchronization signal.

2. Generation of Reference Clock FIG. 3 shows a circuit block of the reference clock generation unit. FIG.
, 10 is a transmission delay measurement counter, 11 is an SA latch unit, 12 and 14 are reception SA holding registers of a downlink multiplexing unit and an uplink demultiplexing unit, 13 and 15 are transmission delay measurement count latching counters, and 16 is a generation counter. Correction value (delay time) calculation unit, 17 is an SA-correction value table,
Reference numeral 8 denotes a comparator that outputs a reference clock.

The transmission delay measurement counter 10 is a free-running counter having a period of one superframe time and returning to zero at full count as shown in FIG. Since one superframe has 25704 bits, the period is calculated to be about 16.6 mS from the transmission rate. The counter increment (correction value accuracy) is about 640 ns. The counter width is 15 bits. The counter period is equal to the superframe period, but the phase relationship is undefined.

The counters 13 and 15 latch the output of the counter 10 at the SA transmission / reception timing, and the correction value calculation unit 16 obtains the SP synchronization counter value from this counter value. This value is a value on the counter corresponding to the midpoint of the transmission delay time. This is called a correction value. The correction value for each SA is stored in Table 1 in which the SA is referred to by the index.
7 to manage.

The correction value and the counter value are stored in a comparator 1
If it is set to 8, it will match the correction value after the counter 10 has made one round. Here is a certain sampling address (S
An SP synchronization point corresponding to An). At this timing, the comparator 18 generates a reference clock / correction value match interrupt. When the correction value on the table is updated every time a coincidence interrupt occurs, a reference clock is generated at a sampling cycle.

FIG. 4 shows the relationship between the transmission delay time and the counter value. The upper part of the figure shows the time-distance path and SP of the frame.
This is the relationship with the synchronization point. This shows a state in which the SA part of the frame located only in the common frame transmitted at t1 and located in the next field of the FA is received at t2, and the intermediate point is set as the SP synchronization point. The slash is a miracle. The lower side of the figure is the value of the corresponding counter. When the horizontal axis indicates time and the counter axis indicates counter values, and the counter values for each time are plotted, the hatched lines in the figure are obtained.

The sampling synchronization point is SPn · SPn +
1 ... If there is no abnormality in the transmission path, these points coincide with all stations. Here, assuming that the sampling address of the n-th multi-frame in an arbitrary superframe is SAn, the SP synchronization point is SPn. SP
At the synchronization point, a reference clock SPCLKn is generated.
SPCLKn of SPn is generated by the comparison count value CPn-1 which is a correction value obtained by SAn one cycle before.

Referring to FIG. 3, the reference clock generator 1
After a transmission error or the like is not detected for a certain period of time and the reliability of the received data is confirmed, the F / W processing is performed in the next procedure.
(See 101 to 105 in FIG. 10) (1) The downlink multiplexing unit (12, 13)
At the timing of transmitting A, the SA value and the transmission delay measurement counter value at that time are latched, and an interrupt is generated. (Downlink SA transmission interrupt) (2) The uplink separation unit (14, 15)
At the timing when A is separated, the SA value and the counter value are latched in the same manner as described above, and an interrupt is generated. (Uplink SA reception interrupt) (3) The SA-correction value table 17 indicates that the SA value (0... 1)
It has 12 buffers corresponding to (1), and has the above (1),
The correction value (delay time) _CSP is stored in the buffer pointed to by the SA corresponding to the interrupt of (2). Correction value calculation unit 16
The method for calculating the correction value in will be described later.

Wait until the error of the correction value at this time is within ± 20 μS. If it is within the accuracy, proceed to (4).

(4) The correction value on the buffer is set in the comparator 18, and the comparator is enabled.

(5) The counter 10 enters the next cycle,
When the value matches the set value of the comparator 18, a count match interrupt is generated.

At the same time, one reference clock is generated.

(6) At this interrupt, the F / W sets the next value in the correction value buffer to the comparator.

(7) Thereafter, the above (5) and (6) are repeated while monitoring the accuracy of the correction value.

[0048] 2.1 calculated correction value calculating unit 16 of the correction value, and downlink SA transmission interrupt, the count value of the counter 13 when generated by t1 and C _1,
The count value of the counter 15 when the uplink SA receive interrupt of the same SA value has occurred at t2 as C _2, the correction value C
Calculate _SP . Basically, it is determined by equation (1) or equation (2). (Actually, tuning is required.) (See FIG. 5) When C ₁ <C ₂ (within the same count), C _SP = (C ₁ + C ₂ ) / 2 (1) C ₁ > C ₂ At the time (once full count → zero), C _SP = (C ₁ + C ₂ −T) / 2 (2) (T is a full count value) 2.2 Countermeasures at the time of transmission error detection The value becomes a pointer when setting the correction value. If this SA value is incorrect,
There is a possibility that the correction value of another SA is destroyed. Therefore, when storing the correction value in the table 17, it is necessary to check the reception error status and check the validity of the SA.

However, the validity of the delay value itself is that the multiframe to which the delay value belongs is not normal.

During normal operation, extreme fluctuations in transmission delay cannot occur. However, if the current value cannot be used due to the above-mentioned reasons, the previous correction value is used as it is.

3. Dependent Synchronization of Sampling Clock The slave synchronizer 3 synchronizes all the stations based on the reference clock generated by the reference clock generator 1 with the slave clock of the own station.

FIG. 6 shows a block diagram of the subordinate synchronization unit 3. In the figure, 31 is a frequency divider, 32 is a phase comparator, and the phase comparator determines the frequency division ratio from the phase difference between the reference clock and the F / B signal from the frequency divider. The PLL circuit is configured to divide the clock by the division ratio set by the section.

3.1 Frequency of Base Clock The PCM relay system (FIG. 11) performs terminal data sampling of a system of 60 Hz. According to the specifications, data sampling is performed 12 times per one cycle of the system, so that the sampling frequency is 720 Hz. In contrast, the transmission rate is 1.544 MHz. On the basis of this, a small error occurs with the system frequency. When this error accumulates, the sampling data timing misalignment occurs. For this reason, the basic clock of the sampling timing is used as the transmission rate.

When the base clock is 1.544 MHz,
When the basic frequency division ratio is set to 2142, 1.544 × 10
^6/2142 = about 720.821662Hz.

With respect to this value, the synchronization determination of the slave synchronization unit 3 is set within a range of ± 32 counts. This value is specified (±
20 μS).

When the frequency division ratio is different by one, the period difference is 1 /
Since it is 1.544 × 10 ⁶ , it is about 640 ns. 32 counts of this is (1 / 1.544 × 10 ⁶ ) × 3
2 = about 20.73 μS.

This principle can be applied to a system of 50 Hz without any problem.

3.2 Determination of Synchronization Establishment Sampling synchronization is determined to be synchronization establishment when the DPLL status from the slave synchronization circuit 3 indicates that synchronization has been completed.

The conditions to be satisfied are (accuracy of the correction value within ± 20 μS) and (DPLL is dependent synchronization completed). The out-of-synchronization condition is (the correction value is shifted by ± 20 μS or more) or (DPLL is dependent synchronization) ).

4. Generation of SYNC 1.2 Signals The output of the slave synchronization unit 3 is output by the SP synchronization signal generation unit 4
SYNC 1 and 2 signals. SYNC4 is asserted once for every 12 assertions of SYNC1 as shown in FIG. These are output irrespective of whether subordinate synchronization is established or not. After the dependent synchronization is established, the signal is synchronized with the reference clock.

4.1 Forced Synchronization of SYNC4 Signal The SYNC4 signal is asserted with the number “0” of the SYNC1 signal. Before subordinate synchronization, the mobile station is self-running with the initialization value. However, when subordinate synchronization is completed and the number of SYNC1 becomes clear, SYNC4 is forcibly synchronized with the cycle.

When performing forced synchronization, the forced synchronization enable bit of the CSR is set during the correction value match interrupt processing of SA11. When the next correction value coincidence interrupt of SA0 occurs, SYNC4 is forcibly synchronized. SYNC
Since 4 is generated by a 12-counter circuit that receives SYNC1 as an input, the counter may be reset at this time.

5. Data Synchronization After the SA correction value is converged, the comparison by the comparator 18 is started. When the starting SA value is specified, the sampling number corresponding to the interrupt generated after one cycle of the counter 10 of the counter 10 is changed. Can be identified. (FIG. 3) For example, when the comparison is started from SA0 after the SA correction value is converged, the first coincidence interrupt is the SP synchronization point of SA0. When this processing is performed in all the stations, the coincidence interrupt (reference clock) is started from the equivalent of SA0 in all the stations.

The generation of the reference clock starts the subordinate synchronization of the sampling clock. When synchronization is completed, SYN
The C1 signal and the reference clock are synchronized. Since the reference clock is specified by the SA value, the SYNC1 synchronized therewith can also be specified by the SA value.
(FIG. 4) The signal SYNC4 is to be generated at the sampling number 0, but at this point, it is in a self-running state, so it is necessary to perform forced synchronization. That is, when SYNC1 synchronized with the SA value indicates “0”, SYNC1
Reset the counter that generates C4.

The F / W processing at this time is performed according to the following procedure. (Refer to 106 to 108 in FIG. 10) (1) The completion of the slave synchronization is known from the DPLL status of the slave synchronization unit 3.

(2) The forced interrupt bit of the control register (CSR) operated by the CPU is set by the coincidence interrupt of the sampling number 11 (loading the correction value of the number 0).

Each station uses the AI module to set the tag No. of the terminal data packet based on SYNC4. Decide. From the assertion of this signal, the tag No. To 0,1,
2,3,4 ...

The CPU and the sampling synchronization circuit manage transmission data based on the tag No. According to this, data sampled by a certain sampling clock is stored in the same transmission buffer area in all stations. (The transmission buffer is composed of 12 terminal data areas corresponding to the sampling addresses. In this process, data synchronization is realized.

When the forced synchronization processing is completed, the sampling synchronization of the own station is established. FIG. 8 shows this synchronization pattern.

5.1 SA delay time After completion of the sampling clock (SPCLK) subordinate synchronization,
Each station starts terminal data multiplexing. At this point, since terminal data can be accessed by pointer management that is consistent for all stations, the master station is a common frame, and this multi-frame MF can be multiplexed with any area data on the transmission buffer. To indicate. This value is stored in the SA delay time field located only in the common frame.

The SA delay time represents the latest sampling number at which the master station can reliably multiplex data.

As shown in FIG. 9, the loaded value of the SA delay time differs depending on the transmission delay amount of the line.

On the left side of FIG. 9, since the delay time is short, for example, the master station can reliably multiplex the data of SP0 in the multiframe MF2. On the other hand, on the right side of FIG. 9, the data of the synchronization point SP10 can be multiplexed on the multiframe MF2. This is because the longer the transmission delay time, the longer the frame takes to reach the loopback station, and consequently M
This is because SP2 corresponding to F2 is relatively delayed.

5.2 Calculation of SA Delay Time The SA delay time value set by the master station in the multiframe of the sampling address SAn is a value obtained by multiplying the transmission delay time value of the master station by １ ／. . Assuming that the converted value is m, nm is the SP number immediately before SAn transmission. In consideration of the non-synchronism between the multi-frame timing and the sampling timing, the value is further decreased by one.

On the left side of FIG. 9, since m = 1, n =
If it is 2, the SP number becomes 0. Similarly, on the right side of FIG. 9, when m = 3 and n = 2, the SP number is 10.

5.3 Handshake of Terminal Data Synchronization In the sampling synchronization process, each station starts multiplexing valid terminal data by setting an SA delay time. The UL flag (synchronization confirmation flag) defined in the common frame is used for the handshake at this time. The firmware processing is performed in the following procedure. (109 to 109 in FIG. 10)
When transmitting to the master station, the common flag is transmitted with the UL flag set to the ready state and the SA delay time set to an invalid value. Each of the slave stations transmits the UL flag as unready (sampling synchronization is not established) while sampling synchronization is not completed.

Completion of sampling synchronization (DPLL status synchronization completed + protection time + forced synchronization of SYNC4)
Then, the UL flag is transmitted in a ready (sampling synchronization established) state.

Among the invalid values of the SA delay time, dummy terminal data is multiplexed. When the master station is received, the UL flag is received in an unready state: Some stations have not completed sampling synchronization.

Receiving UL flag in ready state: sampling synchronization completed for all stations.

Thereafter, the SA delay time is set to a valid value.

Receiving the effective SA delay time, each slave station + master station multiplexes the terminal data of the transmission buffer corresponding to the value.

[0082]

Since the present invention is configured as described above, the following effects can be obtained.

(1) Each slave station converges over time with respect to the sampling synchronization shift at the time of the master station change and at the initial stage, so that the time distortion of the fixed period process can be reduced.

(2) Since each slave station converges in the same manner, sampling points can be efficiently made the same.

(3) Since a DPLL circuit is used,
The retraction time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sampling synchronization related circuit.

FIG. 2 is a graph showing a round-trip transmission time.

FIG. 3 is a block diagram of a reference clock generator.

FIG. 4 is a timing chart of a transmission delay time and a counter value.

FIG. 5 is an explanatory diagram of calculation of a correction value.

FIG. 6 is a block diagram of a dependent synchronization unit.

FIG. 7 is a timing chart of signals.

FIG. 8 is an explanatory diagram of synchronization.

FIG. 9 is a graph showing a relationship between a transmission time of a multiplex frame and a sampling synchronization signal.

FIG. 10 is a processing flowchart of sampling synchronization.

FIG. 11 is a diagram of a transmission path of a PCM current operated relay.

FIG. 12 is an explanatory diagram of a frame format.

FIG. 13 is a block diagram showing a basic configuration of a station.

FIG. 14 is an explanatory diagram of the flow of data multiplexing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Reference block generation part 2 ... Base clock source 3 ... Dependent synchronization part 4 ... SYNC signal generation part 10 ... Transmission delay measurement counter 11 ... SA latch part 12 ... Receiving SA holding register of downlink multiplexing part 13 ... Down multiplexing part Latch counter 14 ... Receiving SA holding register of the up separation unit 15 ... Latch counter of the up separation unit 16 ... Correction value calculation unit 17 ... SA-correction value table 18 ... Comparator 31 ... Divider 32 ... Phase comparison unit MS … Master station RS0-RS4… Remote station (slave station)

Claims (3)

[Claims] 1. A sampling synchronization method in a PCM relay for synchronizing a data sampling clock of a data multiplexing type PCM current relay based on a network system including a master station, a plurality of slave stations, and a serial transmission line connecting them. A reference clock generating means for measuring the transmission delay time with reference to the transmission and reception of the sampling address in each common frame and using the intermediate point as a reference of the sampling clock; and controlling the base clock of the transmission rate by DPLL control. And a means for subordinately synchronizing the sampling clock with the reference clock. 2. The communication system according to claim 1, wherein the reference clock generation means is provided in a transmission delay measurement counter having a period of one superframe time for counting a base clock, and a downlink data multiplexing unit, and a sampling address in the common frame is provided. Means for latching the sampling address value and the counter value at that time at a transmission timing; means provided in an uplink data separating unit, for latching a sampling address value at a timing at which a sampling address in a common frame is separated; Means for holding a buffer corresponding to the sampling address value, storing the average value of the count value at the time of occurrence of the interrupt as a correction value in the buffer pointed to by the sampling address corresponding to each interrupt, and setting the value of the buffer; Is the set value Matching the comparison means for generating a reference clock, the sampling synchronization in PCM relay characterized by comprising the method. 3. The method according to claim 1, wherein the UL flag defined in the common frame is used in a handshake for starting multiplexing of valid terminal data to the master station, and the UL flag is set to a ready state at the time of transmission. A means for setting the sampling address delay time to invalid and transmitting a common frame is provided, and the slave station uses a UL flag defined in the common claim for a handshake when starting multiplexing of valid terminal data. The sampling synchronization method in the PCM relay, characterized in that a means for sending the UL flag in an unready state when the sampling synchronization is incomplete and sending the UL flag in a ready state when the sampling synchronization is completed is provided.