JP2013132161A - Sampling synchronization circuit of ring system protection relay system - Google Patents

Sampling synchronization circuit of ring system protection relay system Download PDF

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JP2013132161A
JP2013132161A JP2011280953A JP2011280953A JP2013132161A JP 2013132161 A JP2013132161 A JP 2013132161A JP 2011280953 A JP2011280953 A JP 2011280953A JP 2011280953 A JP2011280953 A JP 2011280953A JP 2013132161 A JP2013132161 A JP 2013132161A
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sampling synchronization
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sampling
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terminal device
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JP5895512B2 (en
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Toshiyuki Okitsu
俊幸 興津
Takashi Ishii
隆 石井
Toshizane Kamiya
敏実 神谷
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Meidensha Electric Manufacturing Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To facilitate the design of integrating and aggregating a circuit for simultaneously sampling the system signals measured by a central relay device and each terminal with a multiplexed information transmitter while carrying out efficient sampling synchronization by single stage configuration.SOLUTION: Sampling synchronization signals synchronized between the communication unit TR of a central relay device MR and each terminal RS are generated, respectively. These sampling synchronization signals serve as the sampling synchronization signals of a system signal by the relay RY of the central relay device and the relay RY of each terminal. The sampling synchronization circuit as a master station of the communication unit in the central relay device operates as a self-propelled oscillation circuit, and the sampling synchronization circuit of the communication unit in each terminal operates as a slave synchronization circuit.

Description

本発明は、環線系統を保護する環線系統の保護継電システムに係り、特に中央通信装置と複数の端末装置で計測される系統信号を同時サンプリングして多重伝送するサンプリング同期回路に関する。   The present invention relates to a protection relay system for a ring system that protects the ring system, and more particularly to a sampling synchronization circuit that simultaneously samples and multiplex-transmits system signals measured by a central communication device and a plurality of terminal devices.

一般に、電力系統の保護継電システムは、コンピュータ資源を利用してシステムを構築し、保護対象となる電力系統から収集した系統電圧や系統電流などのディジタル情報を基にディジタル保護演算を行い、事故検出とその事故区間が特定されたときは事故区間に繋がる系統しゃ断器などを開放して事故区間を系統から切り離し、健全区間のみによる電力系統の円滑な運用を図る。   Generally, a power system protection relay system uses computer resources to build a system, performs digital protection calculations based on digital information such as system voltage and system current collected from the power system to be protected, and When the detection and the accident section are identified, the system breaker connected to the accident section is opened to disconnect the accident section from the system, and smooth operation of the power system using only the healthy section is attempted.

環線系統のディジタル保護継電システムの例を、図４に電力系統と保護継電システムの概略構成で示す。同図において、電力系統は変電所ＳＳから各需要家Ｄ１〜Ｄ３までの線路接続を環線構成とし、線路に系統事故などが発生した場合にその区間を切り離し、残りの健全区間には迂回路（変電所からみて時計方向と反時計方向の線路）を通して需要家への給電路を確保可能とする。   An example of a ring system digital protection relay system is shown in FIG. 4 in a schematic configuration of a power system and a protection relay system. In the figure, the electric power system has a line connection from the substation SS to each of the consumers D1 to D3, and when a system fault or the like occurs on the line, the section is cut off, and the remaining healthy section has a detour ( It is possible to secure a power supply path to customers through the lines (clockwise and counterclockwise as viewed from the substation).

保護継電システムは、変電所側に設けた中央通信装置ＭＳと、各需要家側に設けた複数の端末装置ＲＳ１、ＲＳ２、ＲＳ３との間を１系と２系の二重化ループ伝送路で結合し、需要家側の各端末装置ＲＳ１〜ＲＳ３が同時サンプリングで収集したデータを時分割で多重化して１系伝送路と２系伝送路を通して中央通信装置ＭＳに伝送し、中央通信装置ＭＳは受信した多重化データを需要家別に分離し、この情報と変電所ＳＳ側で同時サンプリングで収集したデータを利用して中央継電装置ＭＲが保護演算を行い、この保護演算で事故発生を検出したときには事故発生した需要家を環線系統から切り離す制御情報を含めた多重情報を中央通信装置ＭＳが伝送し、各需要家の各端末装置ＲＳ１〜ＲＳ３は中央通信装置ＭＳから伝送されてくる多重情報から自局宛の機器制御情報を分離抽出し、当該端末装置では当該需要家をそのしゃ断器のトリップで環線系統から取り除き、電力系統の運用を継続可能にする。   The protective relay system connects the central communication device MS provided on the substation side and the plurality of terminal devices RS1, RS2, and RS3 provided on each customer side with a 1-system and 2-system duplex loop transmission line. Then, the data collected by the terminal devices RS1 to RS3 on the customer side by simultaneous sampling are multiplexed in a time division manner and transmitted to the central communication device MS through the 1st transmission line and the 2nd transmission line, and the central communication device MS receives the data. When the central relay MR performs a protection operation using this information and the data collected by simultaneous sampling on the substation SS side and detects the occurrence of an accident by this protection operation. The central communication device MS transmits multiplex information including control information for disconnecting the customer in which the accident occurred from the ring system, and each terminal device RS1 to RS3 of each customer is transmitted from the central communication device MS. The device control information directed to the mobile station separates and extracts from the broadcasting, in the terminal device removes the customer from the ring line system reviews the breaker, to allow continued operation of the power system.

この保護継電システムにおける中央通信装置ＭＳと各端末装置ＲＳ１〜ＲＳ３間の情報伝送には、複数の情報を時分割で多重化して伝送する多重情報伝送が行われる。また、保護継電システムの性質から、多重情報伝送処理を実現するため、実時間処理、サイクリック伝送、同時サンプリングのための同期化等が施される。   In the information transmission between the central communication device MS and each of the terminal devices RS1 to RS3 in this protection relay system, multiple information transmission is performed in which a plurality of information is multiplexed and transmitted in a time division manner. In addition, due to the nature of the protective relay system, real-time processing, cyclic transmission, synchronization for simultaneous sampling, and the like are performed in order to realize multiple information transmission processing.

上記の中央通信装置ＭＳと各端末装置ＲＳ１〜ＲＳ３間の多重情報伝送は、図５にフレーム構成の例を示すように、所定のサイクル構成，フレーム構成及びワード構成の伝送フォーマット化処理と、伝送速度等に基づいた送受信処理と、各種インタフェースによる多重分離を行うが、これら信号処理が保護系統構成に応じて個別に設計，製作されるため系統構成の変更や新設の都度装置の設計等が必要となる。   Multiplex information transmission between the central communication device MS and each of the terminal devices RS1 to RS3 includes transmission format processing of a predetermined cycle configuration, frame configuration, and word configuration, as shown in FIG. Transmission / reception processing based on speed, etc., and demultiplexing by various interfaces, but these signal processing are individually designed and manufactured according to the protection system configuration, so it is necessary to change the system configuration or design the equipment each time it is newly installed It becomes.

この対処法として、中央通信装置ＭＳと複数の端末装置ＲＳ１〜ＲＳ３間での情報の多重伝送に、送受信情報の多重分離をバス上の送受信タイミング信号により行うことにより、多重情報伝送処理のための装置設計，変更を容易にした多重情報伝送処理装置がある（例えば、特許文献１参照）。   As a countermeasure for this, the multiplex transmission of information between the central communication device MS and the plurality of terminal devices RS1 to RS3 is performed by demultiplexing the transmission / reception information by the transmission / reception timing signal on the bus, thereby performing the multiplex information transmission processing. There is a multiple information transmission processing device that facilitates device design and change (see, for example, Patent Document 1).

中央継電装置及び各端末装置で計測される系統信号の同時サンプリング方法としては、中央継電装置に接続する中央通信装置から１系と２系のループ伝送路に対してサンプリング同期化のための送信タイミングで信号を発信し、前記発信信号が前記１系と２系のループ回線に接続された各端末装置を経て一巡し、それぞれ中央通信装置に到達するまでに必要な右回り遅延時間Ｔ1と左回り遅延時間Ｔ2とを求め、遅延時間がＴ1＝Ｔ2時には（Ｔ1＋Ｔ2）／４の時間だけ、かつ折り返し伝送になるＴ1≠Ｔ2時にはＴ1／２，Ｔ2／２の時間だけそれぞれ同期すべきタイミングより前の時刻に調整したタイミングで１系と２系のループ回線に中央通信装置から夫々サンプリング同期用タイミング信号を送出し、各端末装置は前記１系のループ回線を通して受信したサンプリング同期用タイミング信号と２系のループ回線を通して受信したサンプリング同期用タイミングとの受信タイミングの中間時刻を同時サンプリングタイミングとする方法がある（例えば、特許文献２参照）。 As a simultaneous sampling method of the system signal measured by the central relay device and each terminal device, the central communication device connected to the central relay device is for sampling synchronization with respect to the loop transmission path of the first and second systems. A signal is transmitted at a transmission timing, and the transmission signal makes a round through each terminal device connected to the 1st and 2nd loop lines, and a clockwise delay time T 1 necessary for reaching each central communication device. and seeking and counterclockwise delay time T 2, the delay time T 1 = T 2 times (T 1 + T 2) / 4 of the time only, and becomes folded transmission T 1 ≠ T 2 times T 1/2, T 2 The timing signal for sampling synchronization is sent from the central communication device to the loop lines of the 1st and 2nd systems respectively at the timing adjusted to the time prior to the timing to be synchronized by the time of / 2, respectively. loop There is a method of the intermediate time of the reception timing of the received sampled synchronization timing through the loop line of the timing signal for sampling the received synchronization and 2 system through line simultaneous sampling timing (for example, see Patent Document 2).

特許２６８９５０８「ディジタル保護継電システムの多重情報伝送処理装置」Patent 2689508 "Multiple information transmission processor for digital protection relay system" 特許２６８９５０６「ディジタル保護継電装置のサンプリング同期方法」Patent 2689506 “Sampling synchronization method of digital protection relay device”

環線系統の保護継電システムにおける従来のサンプリング同期方法は、保護と通信の責務から、それぞれを分割して処理をしていた関係から、通信部でのサンプリング同期およびリレー部でのサンプリング同期が必要となっていた。特許文献２では、このサンプリング同期について提案しているが、実際のシステムでは、図４中に示すように、中央通信装置ＭＳと端末装置ＲＳの通信部ＴＲでのサンプリング同期ＳＡ１と、端末装置ＲＳのリレー部ＲＹでのサンプリング同期ＳＡ２という二段方式となっており、冗長であった。   The conventional sampling synchronization method in the protection relay system of the trunk line system requires the sampling synchronization in the communication part and the sampling synchronization in the relay part because of the responsibility of protection and communication, because each process was divided and processed. It was. Patent Document 2 proposes this sampling synchronization, but in an actual system, as shown in FIG. 4, the sampling synchronization SA1 in the communication unit TR between the central communication device MS and the terminal device RS, and the terminal device RS. The two-stage method of sampling synchronization SA2 in the relay unit RY is redundant.

本発明の目的は、中央継電装置と各端末装置で計測される系統信号を同時サンプリングする回路を一段構成で効率的なサンプリング同期をしながら、多重分離装置と統合、集約した設計を容易にした環線系統保護継電システムのサンプリング同期回路を提供することにある。   The object of the present invention is to easily integrate and consolidate the design with a demultiplexer while efficiently sampling and synchronizing a single-stage circuit that simultaneously samples system signals measured by a central relay and each terminal device. It is an object of the present invention to provide a sampling synchronization circuit for a ring system protection relay system.

本発明は、前記の課題を解決するため、中央継電装置の通信部と各端末装置の通信部の間で同期したサンプリング同期信号をそれぞれ生成し、このサンプリング同期信号を中央継電装置のリレー部および各端末装置のリレー部による系統信号のサンプリング同期信号とし、中央継電装置の通信部がもつ親局としてのサンプリング同期回路は自走発振回路として動作し、前記各端末装置の通信部がもつサンプリング同期回路は従属同期回路として動作する構成としたもので、以下の構成を特徴とする。   In order to solve the above problems, the present invention generates a sampling synchronization signal synchronized between the communication unit of the central relay device and the communication unit of each terminal device, and the sampling synchronization signal is relayed to the relay of the central relay device. And a sampling synchronization signal of a system signal by a relay unit of each terminal device, a sampling synchronization circuit as a master station included in the communication unit of the central relay device operates as a free-running oscillation circuit, and the communication unit of each terminal device The sampling synchronization circuit has a configuration that operates as a dependent synchronization circuit, and has the following configuration.

（１）電力系統は電源変電所から各需要家までを環線で接続し、電源変電所端に配置する中央継電装置と各需要家端に配置する端末装置との間は１系と２系のループ伝送路で接続し、変電所側の中央継電装置と各端末装置で系統信号を同時サンプリングし、各端末装置で同時サンプリングした系統信号を時分割で多重化して中央継電装置にループ伝送し、中央継電装置は各端末装置からの系統信号を分離し、これら系統信号と変電所端での系統信号から保護演算を行い、必要に応じて各需要家端の機器操作信号を各端末装置にループ伝送する環線系統保護継電システムにおいて、
前記中央継電装置と各端末装置のサンプリング同期回路は、
前記中央継電装置の通信部と各端末装置の通信部の間で同期したサンプリング同期信号をそれぞれ生成し、このサンプリング同期信号を中央継電装置のリレー部および各端末装置のリレー部による系統信号のサンプリング同期信号とし、
前記中央継電装置の通信部がもつ親局としてのサンプリング同期回路は自走発振回路として動作し、前記各端末装置の通信部がもつサンプリング同期回路は従属同期回路として動作させる構成としたことを特徴とする。 (1) The power system connects the power substation to each customer with a ring line, and the 1st and 2nd systems are between the central relay device arranged at the power substation end and the terminal device arranged at each customer end. Are connected via a loop transmission line, the system signal is simultaneously sampled by the central relay device on the substation side and each terminal device, and the system signal simultaneously sampled by each terminal device is multiplexed in a time division manner and looped to the central relay device The central relay device separates the system signal from each terminal device, performs a protection operation from these system signals and the system signal at the substation end, and sends the equipment operation signal at each consumer end as necessary. In the loop system protection relay system for loop transmission to the terminal device,
Sampling synchronization circuit of the central relay device and each terminal device,
A sampling synchronization signal synchronized between the communication unit of the central relay device and the communication unit of each terminal device is generated, and this sampling synchronization signal is a system signal by the relay unit of the central relay device and the relay unit of each terminal device. Sampling synchronization signal
The sampling synchronization circuit as a master station included in the communication unit of the central relay device operates as a free-running oscillation circuit, and the sampling synchronization circuit included in the communication unit of each terminal device is configured to operate as a subordinate synchronization circuit. Features.

（２）前記中央継電装置と各端末装置の前記サンプリング同期回路は、
ループ伝送路の光−電気変換器（１，２）で変換した受信信号から１系と２系の分離インタフェース（２１、２２）が受信フレーム内のサンプリング同期用タイムスロットからサンプリング同期タイミング信号を抽出し、１系と２系の遅延測定回路（２３、２４）が１系と２系の伝送遅延（Ｔ１、Ｔ２）を測定し、遅延測定回路（２５）が１系と２系の伝送路から得られたサンプリング同期タイミング信号の伝送時間差（Ｔ３）を測定し、前記監視・設定回路（３）が伝送時間差（Ｔ３）からサンプリング同期点を演算して受信ＳＰタイミング回路（２６）に同期点を設定し、発振器（２７）とＤＰＬＬ（２８）と位相比較器（２９）との間で従属同期をとるサンプリング同期ロジック構成としたことを特徴とする。 (2) The sampling synchronization circuit of the central relay device and each terminal device is:
The 1-system and 2-system separation interfaces (21, 22) extract the sampling synchronization timing signal from the sampling synchronization time slot in the reception frame from the reception signal converted by the opto-electric converter (1, 2) of the loop transmission path. The 1st and 2nd system delay measurement circuits (23, 24) measure the 1st and 2nd system transmission delays (T1, T2), and the 1st and 2nd system delay measurement circuits (25, 24) The transmission time difference (T3) of the obtained sampling synchronization timing signal is measured, and the monitoring / setting circuit (3) calculates the sampling synchronization point from the transmission time difference (T3) and sets the synchronization point in the reception SP timing circuit (26). It is characterized in that it is set as a sampling synchronization logic configuration in which dependent synchronization is established among the oscillator (27), the DPLL (28), and the phase comparator (29).

以上のとおり、本発明によれば、中央継電装置の通信部と各端末装置の通信部の間で同期したサンプリング同期信号をそれぞれ生成し、このサンプリング同期信号を中央継電装置のリレー部および各端末装置のリレー部による系統信号のサンプリング同期信号とし、中央継電装置の通信部がもつ親局としてのサンプリング同期回路は自走発振回路として動作し、前記各端末装置の通信部がもつサンプリング同期回路は従属同期回路として動作する構成としたため、中央継電装置と各端末装置で計測される系統信号を同時サンプリングする回路を一段構成で効率的なサンプリング同期をしながら、多重化情報伝送装置と統合、集約した設計が容易になる。   As described above, according to the present invention, each of the sampling synchronization signals synchronized between the communication unit of the central relay device and the communication unit of each terminal device is generated, and the sampling synchronization signal is transmitted to the relay unit of the central relay device and The sampling synchronization signal of the system signal by the relay unit of each terminal device, the sampling synchronization circuit as the master station of the communication unit of the central relay device operates as a free-running oscillation circuit, the sampling of the communication unit of each terminal device Since the synchronization circuit is configured to operate as a subordinate synchronization circuit, the multiplexed information transmission device is configured to efficiently sample and synchronize a circuit that simultaneously samples the system signal measured by the central relay device and each terminal device in a single stage configuration. Integrated and integrated design becomes easy.

従来と本発明におけるサンプリング同期回路のブロック構成図。The block block diagram of the sampling synchronous circuit in the past and this invention. 実施形態の電力系統と保護継電システムの概略構成図。The schematic block diagram of the electric power grid | system and protection relay system of embodiment. 実施形態のサンプリング同期回路図。The sampling synchronous circuit diagram of embodiment. 従来の電力系統と保護継電システムの概略構成図。The schematic block diagram of the conventional electric power system and a protection relay system. 多重情報伝送におけるフレームの構成例。2 is a structural example of a frame in multiplex information transmission.

（１）サンプリング同期回路のブロック構成
図１は、従来と本発明におけるサンプリング同期回路のブロック構成を示す。図４で説明するように、従来、中央通信装置ＭＳと端末装置ＲＳにおけるサンプリング同期には、２つのサンプリング同期回路で構成されていた。すなわち、サンプリング同期ＳＡ１では１系と２系の伝送路上の情報に対して中央通信装置ＭＳと端末装置ＲＳの通信部ＴＲにおいてサンプリング同期を得ている。一方、サンプリング同期ＳＡ２は、中央継電装置ＭＲで取り込む計測情報のサンプリング同期と、端末装置ＲＳのリレー部ＲＹで取り込む計測情報のサンプリング同期を得ている。 (1) Block Configuration of Sampling Synchronization Circuit FIG. 1 shows a block configuration of a sampling synchronization circuit in the prior art and the present invention. As will be described with reference to FIG. 4, conventionally, the sampling synchronization in the central communication device MS and the terminal device RS has been configured by two sampling synchronization circuits. That is, in the sampling synchronization SA1, sampling synchronization is obtained in the communication unit TR of the central communication device MS and the terminal device RS with respect to information on the 1-system and 2-system transmission paths. On the other hand, the sampling synchronization SA2 obtains sampling synchronization of measurement information captured by the central relay MR and sampling synchronization of measurement information captured by the relay unit RY of the terminal device RS.

本実施形態におけるサンプリング同期ロジックは、伝送路上の通信情報のサンプリングと、変電所ＳＳおよびリレー部ＲＹでの計測情報のサンプリングという境を無くし一体化することで、図２のように、中央通信装置を中央継電装置と一体構成とし、中央継電装置ＭＲのサンプリング同期回路（親局モード）と端末装置ＲＳのサンプリング同期回路（端末局モード）として共通化して後述の多重情報伝送装置に集約可能とする。   The sampling synchronization logic in the present embodiment eliminates the boundary between sampling of communication information on the transmission line and sampling of measurement information at the substation SS and the relay unit RY, thereby integrating the central communication device as shown in FIG. Can be integrated with the central relay device and shared as the sampling synchronization circuit (master station mode) of the central relay device MR and the sampling synchronization circuit (terminal station mode) of the terminal device RS, and can be integrated into the multiplex information transmission device described later And

従来のサンプリング同期は、図１の（ａ）に示すように、中央通信装置ＭＳの通信部ＴＲと端末装置ＲＳの通信部ＴＲとの間のサンプリング同期信号と、中央通信装置ＭＳのリレー部ＲＹと端末装置ＲＳのリレー部ＲＹによるサンプリング同期信号を分離して管理していた。すなわち、中央通信装置ＭＳと端末装置ＲＳの通信部ＴＲで同期をとり、その結果の同期信号（ＳＰ同期信号）を中央継電装置および端末装置のリレー部ＲＹに渡して再度同期を取っていた。   As shown in FIG. 1A, the conventional sampling synchronization includes a sampling synchronization signal between the communication unit TR of the central communication device MS and the communication unit TR of the terminal device RS, and the relay unit RY of the central communication device MS. The sampling synchronization signal by the relay unit RY of the terminal device RS is separated and managed. That is, the communication unit TR of the central communication device MS and the terminal device RS is synchronized, and the resulting synchronization signal (SP synchronization signal) is passed to the central relay device and the relay unit RY of the terminal device to synchronize again. .

本実施形態は、図１の（ｂ）に示すように、上記の通信部ＴＲとリレー部ＲＹとの別れた情報管理を撤廃して一体化することで、より効率的なサンプリング同期を実現するものである。これにより、通信部のサンプリング同期１回路とリレー部のサンプリング同期２回路に別れていた２つのＤＰＬＬ（ディジタルＰＬＬ）回路が１つに削減される。この結果、プリント板枚数が削減され、多重情報伝送装置と同一ＦＰＧＡに統合されることで、機能が集約される。さらに、通信として必要な機能を多重情報伝送装置と合わせることで、ＩＣにワンチップ化できる。   As shown in FIG. 1B, the present embodiment realizes more efficient sampling synchronization by eliminating and integrating the separate information management of the communication unit TR and the relay unit RY. Is. As a result, the two DPLL (digital PLL) circuits separated into the sampling synchronization 1 circuit of the communication unit and the sampling synchronization 2 circuit of the relay unit are reduced to one. As a result, the number of printed boards is reduced, and the functions are integrated by being integrated into the same FPGA as the multiplex information transmission apparatus. Further, by combining functions necessary for communication with the multiplex information transmission apparatus, the IC can be made into one chip.

また、中央継電装置の通信部がもつサンプリング同期の親局機能は、自走発振回路として動作し、端末装置の通信部は従属同期回路として動作することを、一義的に「ノードアドレス」で切り替えられるように設計されることで、回路設計を容易にする。   In addition, the sampling synchronization master station function of the communication unit of the central relay device operates as a free-running oscillation circuit, and the communication unit of the terminal device operates as a subordinate synchronization circuit. The circuit design is facilitated by being designed to be switched.

（２）サンプリング同期ロジック
図３は、本実施形態によるサンプリング同期回路の構成図であり、多重分離装置１００の伝送情報入出力部と共通にして通信ボード３００に搭載される。２００は中央継電装置ＭＲまたは端末装置のリレー部ＲＹになる継電装置である。 (2) Sampling Synchronization Logic FIG. 3 is a configuration diagram of the sampling synchronization circuit according to the present embodiment, and is mounted on the communication board 300 in common with the transmission information input / output unit of the demultiplexer 100. Reference numeral 200 denotes a relay device that becomes the relay unit RY of the central relay device MR or the terminal device.

サンプリング同期回路の説明の前に、多重分離装置１００の概略構成を説明する。多重分離装置１００は、中央通信装置ＭＳ、または端末装置ＲＳ（ＲＳ１〜ＲＳ３）の通信部ＴＲに搭載され、図２の１系と２系のループ伝送路を通した多重情報伝送機能と、継電装置２００との間で回線情報や監視情報などを多重／分離して授受する機能を集約して高集積化する。   Before describing the sampling synchronization circuit, a schematic configuration of the demultiplexer 100 will be described. The demultiplexing device 100 is mounted on the communication unit TR of the central communication device MS or the terminal device RS (RS1 to RS3), and has a multiplex information transmission function through the 1-system and 2-system loop transmission paths in FIG. The functions of multiplexing / separating and transmitting / receiving line information, monitoring information, etc. to / from the electric device 200 are integrated and highly integrated.

多重分離装置１００は、伝送路との情報入出力手段として、１系の光−電気変換器（Ｏ／Ｅ）と２系の光−電気変換器（Ｏ／Ｅ）が接続され、これら光−電気変換器からの電気信号（１系のＤＡＴＡ１，ＥＣＬＫ１，２系のＤＡＴＡ２，ＥＣＬＫ２）が入力される。同様に、１系の電気−光変換器（Ｅ／Ｏ）と２系の電気−光変換器（Ｅ／Ｏ）が接続され、これら電気−光変換器からの光信号（１系のＤＡＴＡ１，ＥＣＬＫ１，２系のＤＡＴＡ２，ＥＣＬＫ２）が光伝送路に出力される。   The multiplexer / demultiplexer 100 is connected to a 1-system optical-electrical converter (O / E) and a 2-system optical-electrical converter (O / E) as information input / output means for the transmission line. An electric signal (1 system DATA1, ECLK1, 2 system DATA2, ECLK2) from the electrical converter is input. Similarly, a 1-system electro-optical converter (E / O) and a 2-system electro-optical converter (E / O) are connected, and optical signals from these electro-optical converters (system 1 DATA1, ECLK 1 and 2 systems DATA 2 and ECLK 2) are output to the optical transmission line.

また、多重分離装置１００には、中央継電装置ＭＲまたはリレー部ＲＹとの間で多重・分離した各個別の情報の入出力手段を備える。また、多重分離装置１００を搭載する通信ボード３００には、多重分離装置１００とリレー部ＲＹ２００との間の情報授受を管理する。   Further, the demultiplexing device 100 includes input / output means for individual information multiplexed / separated with the central relay device MR or the relay unit RY. The communication board 300 on which the demultiplexing device 100 is mounted manages information exchange between the demultiplexing device 100 and the relay unit RY200.

次に、図３に示すサンプリング同期回路を説明する。図３において、伝送路を通したＯ／Ｅからの信号は、多重分離装置１００中の１系受信インタフェース１から１系分離インタフェース２１にて、図５に示すフレーム内のサンプリング同期用タイムスロット（ＳＰ）からサンプリング同期タイミング信号を抽出する。同様に、２系受信インタフェース２から２系分離インタフェース２２にて、フレーム内のサンプリング同期用タイムスロットからサンプリング同期タイミング信号を抽出する。この動作は、サンプリング信号は、特許文献２で記載されているように、例えば５０ＨｚのようなＳＰ同期信号と呼ばれる信号であり、この信号を１９２ＫＨｚの多点サンプリング回線を使用して、Ｓ／Ｐ、Ｐ／Ｓ変換する。Ｓ／Ｐ、Ｐ／Ｓ変換することで、中央継電装置と端末装置間でＳＰ同期信号を授受して同時性を示す同期点を求める。   Next, the sampling synchronization circuit shown in FIG. 3 will be described. In FIG. 3, the signal from the O / E that has passed through the transmission line is sent from the 1-system reception interface 1 to the 1-system separation interface 21 in the demultiplexing apparatus 100 at the sampling synchronization time slot ( A sampling synchronization timing signal is extracted from SP). Similarly, the sampling synchronization timing signal is extracted from the sampling synchronization time slot in the frame by the 2-system separation interface 22 from the 2-system reception interface 2. In this operation, the sampling signal is a signal called an SP synchronization signal such as 50 Hz, as described in Patent Document 2, and this signal is converted into an S / P signal using a multipoint sampling line of 192 KHz. , P / S conversion. By performing S / P and P / S conversion, an SP synchronization signal is exchanged between the central relay device and the terminal device to obtain a synchronization point indicating simultaneity.

中央継電装置（親局、マスター局）としての動作では、特許文献２に記載するように、１系ＳＰ送信タイミング回路（１０）で発生させたタイミングで１系の伝送遅延Ｔ１を１系遅延測定回路２３で測定して、監視・設定回路３のＣＰＵがバス経由で処理を行う。同様に、２系ＳＰ送信タイミング回路１１で発生させたタイミングで２系の伝送遅延Ｔ２を２系遅延測定回路２４で測定して、監視・設定回路３のＣＰＵがバス経由で処理を行う。   In the operation as a central relay device (master station, master station), as described in Patent Document 2, the 1-system transmission delay T1 is set to the 1-system delay at the timing generated by the 1-system SP transmission timing circuit (10). Measurement is performed by the measurement circuit 23, and the CPU of the monitoring / setting circuit 3 performs processing via the bus. Similarly, the 2-system transmission delay T2 is measured by the 2-system delay measurement circuit 24 at the timing generated by the 2-system SP transmission timing circuit 11, and the CPU of the monitoring / setting circuit 3 performs processing via the bus.

端末装置（子局、スレーブ局）としての動作では、１系と２系の伝送路から得られたＳＰ同期信号の伝送時間差Ｔ３を遅延測定回路２５で測定し、この伝送時間差Ｔ３を監視・設定回路３のＣＰＵが（Ｔ３／２）の演算処理により受信ＳＰタイミング回路２６にサンプリング同期点を設定することで、発振器２７とＤＰＬＬ２８と位相比較器２９との間で、従属同期をとる。その従属同期した信号を元に、逓倍回路３０で、必要な周波数成分を作成して端末装置ＲＳのリレー部ＲＹで計測情報の同期したサンプリング信号（ＳＰ同期信号）に使用する。   In the operation as a terminal device (slave station or slave station), the transmission time difference T3 of the SP synchronization signal obtained from the 1-system and 2-system transmission paths is measured by the delay measurement circuit 25, and this transmission time difference T3 is monitored and set. The CPU of the circuit 3 sets the sampling synchronization point in the reception SP timing circuit 26 by the arithmetic processing of (T3 / 2), thereby obtaining dependent synchronization among the oscillator 27, the DPLL 28, and the phase comparator 29. Based on the slave-synchronized signal, a necessary frequency component is generated by the multiplication circuit 30 and used as a sampling signal (SP synchronization signal) in which measurement information is synchronized by the relay unit RY of the terminal device RS.

これらの機能を多重分離装置１００を構成するＩＣの中に集約することで、装置の小型化、低消費電力化を図る。   By consolidating these functions in the IC constituting the demultiplexing apparatus 100, the apparatus can be reduced in size and power consumption can be reduced.

なお、端末装置側でサンプリング信号（ＳＰ同期信号）で同時サンプリングした計測データは、多重分離装置１００の送信タイミング回路９で送信タイミングが生成され、この送信タイミングで１系多重インタフェース１０と２系多重インタフェース１１で多重化し、１系送信選択回路１３と２系送信選択回路１４および１系送信インタフェース１５と２系送信インタフェース１６を経て伝送される。   Note that the measurement timing simultaneously sampled with the sampling signal (SP synchronization signal) on the terminal device side is generated at the transmission timing circuit 9 of the demultiplexer 100, and at this transmission timing, the 1-system multiplexing interface 10 and the 2-system multiplexing are transmitted. The signals are multiplexed by the interface 11 and transmitted through the 1-system transmission selection circuit 13, the 2-system transmission selection circuit 14, the 1-system transmission interface 15, and the 2-system transmission interface 16.

以上のように、中央継電装置と各端末装置で計測される系統信号の同時サンプリングは、サンプリング同期をとるための１系送受信回路と２系送受信回路とＤＰＬＬ（ディジタルＰＬＬ）回路と、その結果必要とするタイミング信号を生成する回路を多重分離装置１００と同じにＩＣ化してその集積化を図ると共に通信ボード３００に一体に実装できる。   As described above, the simultaneous sampling of the system signal measured by the central relay device and each terminal device is performed by the 1-system transmission / reception circuit, the 2-system transmission / reception circuit, and the DPLL (digital PLL) circuit for sampling synchronization. A circuit for generating a required timing signal can be integrated into the IC as in the demultiplexing apparatus 100 and can be integrated with the communication board 300.

したがって、中央継電装置のサンプリング同期回路（親局モード）と端末装置のサンプリング同期回路（端末局モード）として共通化してＦＰＧＡに集約し、中央継電装置と端末装置では通信部のサンプリング同期１回路とリレー部のサンプリング同期２回路に別れていた２つのＤＰＬＬ回路が１つに削減され、プリント板枚数を削減して効率的なサンプリング同期ができる。さらに、通信として必要な機能が多重分離装置１００と統合、集約した設計ができ、ＩＣにワンチップ化もできる。さらに、サンプリング同期の親局機能は、自走発振回路として動作し、端末側はスレーブ側であり従属同期回路して動作することを、一義的に「ノードアドレス」で切り替えられるように設計されることで、設計が容易となる。   Accordingly, the sampling synchronization circuit (master station mode) of the central relay device and the sampling synchronization circuit (terminal station mode) of the terminal device are shared and integrated into the FPGA, and sampling synchronization 1 of the communication unit is performed in the central relay device and the terminal device. The two DPLL circuits, which were separated into two circuits and the sampling synchronization circuit of the relay section, are reduced to one, and the number of printed boards can be reduced to achieve efficient sampling synchronization. Furthermore, the functions required for communication can be integrated and integrated with the demultiplexer 100, and the IC can be integrated into a single chip. Furthermore, the master station function for sampling synchronization operates as a free-running oscillation circuit, and is designed so that the terminal side is a slave side and operates as a slave synchronization circuit, and can be uniquely switched by “node address”. Thus, the design becomes easy.

１００ 多重分離装置
２００ リレー部
３００ 通信ボード
３ 監視・設定回路
９ 送信タイミング回路
１０、１１ 多重インタフェース
１３，１４ 送信選択回路
１５，１６ 送信インタフェース
２１，２２ 分離インタフェース（Ｓ／Ｐ、Ｐ／Ｓ）
２３、２４ 遅延測定回路
２５ 遅延測定回路
２６ 受信ＳＰタイミング回路
２７ 発振器
２８ ＤＰＬＬ
２９ 位相比較器
３０ 逓倍回路 DESCRIPTION OF SYMBOLS 100 Demultiplexing apparatus 200 Relay part 300 Communication board 3 Monitoring and setting circuit 9 Transmission timing circuit 10, 11 Multiplexing interface 13,14 Transmission selection circuit 15,16 Transmission interface 21,22 Separation interface (S / P, P / S)
23, 24 Delay measurement circuit 25 Delay measurement circuit 26 Reception SP timing circuit 27 Oscillator 28 DPLL
29 Phase comparator 30 Multiplier circuit

Claims (2)

電力系統は電源変電所から各需要家までを環線で接続し、電源変電所端に配置する中央継電装置と各需要家端に配置する端末装置との間は１系と２系のループ伝送路で接続し、変電所側の中央継電装置と各端末装置で系統信号を同時サンプリングし、各端末装置で同時サンプリングした系統信号を時分割で多重化して中央継電装置にループ伝送し、中央継電装置は各端末装置からの系統信号を分離し、これら系統信号と変電所端での系統信号から保護演算を行い、必要に応じて各需要家端の機器操作信号を各端末装置にループ伝送する環線系統保護継電システムにおいて、
前記中央継電装置と各端末装置のサンプリング同期回路は、
前記中央継電装置の通信部と各端末装置の通信部の間で同期したサンプリング同期信号をそれぞれ生成し、このサンプリング同期信号を中央継電装置のリレー部および各端末装置のリレー部による系統信号のサンプリング同期信号とし、
前記中央継電装置の通信部がもつ親局としてのサンプリング同期回路は自走発振回路として動作し、前記各端末装置の通信部がもつサンプリング同期回路は従属同期回路として動作させる構成としたことを特徴とする環線系統保護継電システムのサンプリング同期回路。 The power system connects the power substation to each customer with a loop line, and loop transmission between the 1st and 2nd systems between the central relay device located at the power substation end and the terminal device located at each customer end Connected by road, the system signal is simultaneously sampled by the central relay device and each terminal device on the substation side, the system signal simultaneously sampled by each terminal device is multiplexed in a time-division manner and loop-transmitted to the central relay device, The central relay separates the system signal from each terminal device, performs a protection operation from these system signals and the system signal at the substation end, and sends the device operation signal at each consumer end to each terminal device as necessary. In the loop system relay system for loop transmission,
Sampling synchronization circuit of the central relay device and each terminal device,
A sampling synchronization signal synchronized between the communication unit of the central relay device and the communication unit of each terminal device is generated, and this sampling synchronization signal is a system signal by the relay unit of the central relay device and the relay unit of each terminal device. Sampling synchronization signal
The sampling synchronization circuit as a master station included in the communication unit of the central relay device operates as a free-running oscillation circuit, and the sampling synchronization circuit included in the communication unit of each terminal device is configured to operate as a subordinate synchronization circuit. Sampling synchronization circuit of the ring line system protection relay system. 前記中央継電装置と各端末装置の前記サンプリング同期回路は、
ループ伝送路の光−電気変換器（１，２）で変換した受信信号から１系と２系の分離インタフェース（２１、２２）が受信フレーム内のサンプリング同期用タイムスロットからサンプリング同期タイミング信号を抽出し、１系と２系の遅延測定回路（２３、２４）が１系と２系の伝送遅延（Ｔ１、Ｔ２）を測定し、遅延測定回路（２５）が１系と２系の伝送路から得られたサンプリング同期タイミング信号の伝送時間差（Ｔ３）を測定し、前記監視・設定回路（３）が伝送時間差（Ｔ３）からサンプリング同期点を演算して受信ＳＰタイミング回路（２６）に同期点を設定し、発振器（２７）とＤＰＬＬ（２８）と位相比較器（２９）との間で従属同期をとるサンプリング同期ロジック構成としたことを特徴とする請求項１に記載の環線系統保護継電システムのサンプリング同期回路。 The sampling relay circuit of the central relay device and each terminal device,
The 1-system and 2-system separation interfaces (21, 22) extract the sampling synchronization timing signal from the sampling synchronization time slot in the reception frame from the reception signal converted by the opto-electric converter (1, 2) of the loop transmission path. The 1st and 2nd system delay measurement circuits (23, 24) measure the 1st and 2nd system transmission delays (T1, T2), and the 1st and 2nd system delay measurement circuits (25, 24) The transmission time difference (T3) of the obtained sampling synchronization timing signal is measured, and the monitoring / setting circuit (3) calculates the sampling synchronization point from the transmission time difference (T3) and sets the synchronization point in the reception SP timing circuit (26). 2. The ring system according to claim 1, wherein a sampling synchronization logic configuration is set and subordinate synchronization is established among the oscillator (27), the DPLL (28), and the phase comparator (29). Sampling synchronization circuit MamoruTsugi electric system.
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