JP2013207526A - Clock supply method and clock supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor an abnormal clock path in each clock path even in the case where there is no clock reference signal and there are two clock paths.SOLUTION: A clock supply method includes in order: a clock returning step for extracting clock signals from two or more input signals of different paths and returning the extracted clock signals to transmission sources of the input signals; and a monitoring step for acquiring a frequency difference between the clock signal returned to the transmission source and an internal clock signal of the transmission source from the transmission source, and determining that a clock path is abnormal when the acquired frequency difference is equal to or more than a preset threshold, or determining that the clock path is normal when the frequency difference falls within the threshold.

Description

  The present invention receives an input clock signal, returns the clock signal extracted from the input clock signal to the opposite transmitting device of the device, and the transmitting device returns the returned clock signal and the internal output from the oscillation unit of the transmitting device. Compares the frequency difference with the clock signal, transmits the clock information including the frequency difference to the receiving device, the receiving device selects the received input clock signal based on the received clock information, and selects the selected clock signal. The present invention relates to a clock supply method and a clock supply device having a function of synchronizing an oscillation unit of a reception device.

Currently, as a network synchronization method for matching the operation clocks of each node in the network and each device in the node, the Japanese communication network employs a subordinate synchronization method. In slave synchronization method, a starting point for supplying node 91 ₀ and 91 ₁ of the uppermost master clock as shown in FIG. 3, nodes submaster node 92 ₀ and 92 1 of the _lower, slave node further lower node A clock signal is distributed to lower nodes such as 93A to 93H via a transmission path (clock path) (see, for example, Patent Document 1).

As shown by a solid line and a broken line in FIG. 3, the sub-master node 92 ₀ and 92 ₁ and the slave node 93A~93H clock dependent source is usually series (0-based) / standby system (system 1) taking a redundant configuration. Normally, when the input is interrupted by the 0 system clock signal distributed from the 0 system (working system) clock path and the current system is disconnected, the clock supply device uses the standby system as the standby system (1 system) clock path. Is switched to the 1-system clock signal distributed from.

In addition, when an abnormality such as a clock abnormality other than an input interruption resulting in a deterioration in clock frequency accuracy occurs in the 0-system clock path, a more detailed abnormality detection function is required. As means for solving such a problem, the clock frequency accuracy with respect to the 0-system input clock signal and the 1-system input clock signal with a signal from a GPS (Global Positioning System) receiver as shown in FIG. the calculation unit 111 ₀ and 111 ₁ is installed, there is a method of monitoring the MTIE (Maximum Time Interval Error). That is, the frequency difference between the 0-system input clock signal and the 1-system input clock signal with respect to the clock reference signal is measured by MTIE at the 0-system input clock frequency accuracy calculation unit 111 ₀ and the 1-system input clock frequency accuracy calculation unit 111 ₁ . Then, the monitoring unit 112 monitors whether or not the frequency difference exceeds a threshold value set for alarm output. If the frequency difference of the active 0-system input clock signal exceeds the threshold value, the monitoring unit 112 is monitored. Thus, the switching signal is output to the switch 114, and the input clock signal input to the oscillating unit 113 is switched by the switch. In the clock supply device 110 shown in FIG. 4, the input disconnection monitoring unit is omitted.

  FIG. 5 shows a specific input dependent source abnormal state and switching transition table in the monitoring unit 112 of FIG. FIG. 5 shows a switching method when the clock supply device 110 is subordinate to the 0-system input clock signal. When the frequency difference between the 0-system input clock signal and the reference clock signal is equal to or greater than the threshold value, it is determined that the 0-system clock path abnormality exists. If it is determined that there is an abnormality with respect to the 1-system clock path in the above state, both clock paths are in an abnormal system. The oscillation unit 113 is in a free-running state where it operates independently. Also, the input dependent source is switched to the 1-system clock path only when there is no clock abnormality in the 1-system clock path. On the other hand, when there is no abnormality in the 0-system clock path, switching is not performed regardless of whether there is an abnormality in the 1-system clock path.

  Furthermore, in contrast to the clock abnormality monitoring method described above, jitter is added to the previous stage of the MTIE calculation unit so that the failure state of the input clock signal can be accurately determined even when the frequency of the input clock signal fluctuates over time due to jitter or wander. A clock abnormality monitoring method for providing a wander removal filter has also been proposed (see, for example, Patent Document 2).

Japanese Patent No. 3370258 JP 2010-288085 A

ITU-T G. 8261

  In order to solve the above problems, an object of the present invention is to monitor an abnormal clock path in each clock path even when there is no clock reference signal and there are two clock paths.

  In order to achieve the above object, the clock supply method and the clock supply device of the present invention detect abnormalities such as clock frequency degradation by comparing the clock of the node with clock information from a lower node. It is characterized by.

  In order to achieve the above object, a clock supply method of the present invention extracts a clock signal from two or more input signals having different paths, and wraps the extracted clock signal back to the transmission source of the input signal. The frequency difference between the clock signal folded back to the transmission source and the internal clock signal of the transmission source is acquired from the transmission source, and the clock path is abnormal when the acquired frequency difference is greater than or equal to a preset threshold value And a monitoring procedure for determining that the clock path is normal if it is within the threshold.

  Since the clock supply method of the present invention includes a clock return procedure and a monitoring procedure in order, it can be determined whether or not each clock path is an abnormal clock path independently. As a result, the clock supply method of the present invention can switch to the normal system clock path even if there are two clock paths of 0 system and 1 system without using the reference clock.

  The clock supply method of the present invention may further include a switching procedure for synchronizing the frequency of the internal clock signal with the clock signal determined to have a normal clock path in the monitoring procedure after the monitoring procedure.

  In the clock supply method of the present invention, as in Synchronous Ethernet (registered trademark) (Non-patent Document 1), in the monitoring procedure, the data signal for transmitting the frequency difference is transmitted in the same manner as the input signal in the clock loopback procedure. You may transmit simultaneously using a path.

  In the clock supply method of the present invention, in the monitoring procedure, the data signal for transmitting the frequency difference and the clock signal are transmitted to the ITU-T G. You may transmit by the method according to 8261.

  In order to achieve the above object, a clock supply device of the present invention includes an input unit to which two or more input signals having different paths are input, and a clock signal included in each input signal to a transmission source of the input signal. A clock folding unit that folds back, an oscillation unit that oscillates an internal clock signal that is frequency-synchronized with a clock signal included in any one of the input signals, and a frequency of the clock signal that is folded back to the transmission source and the internal clock signal of the transmission source A clock information reading unit that reads difference information from the input signal, and determines that the clock path is abnormal if the frequency difference is equal to or greater than a preset threshold value, and if the frequency difference is within the threshold value, And a monitoring unit that determines that it is normal.

  Since the clock supply device of the present invention includes an input unit, a clock folding unit, an oscillation unit, a clock information reading unit, and a monitoring unit, there are no clock reference signals and two clocks of 0 system and 1 system are provided. Even in a redundant configuration with paths, an abnormal clock path can be determined. As a result, the clock supply device of the present invention can switch to the normal clock path.

  The clock supply apparatus according to the present invention may further include a switching unit that synchronizes the frequency of the oscillation unit with a clock signal of a clock path that is determined to be normal by the monitoring unit.

  In the clock supply device of the present invention, the clock output unit that outputs the internal clock signal oscillated by the oscillation unit, and the frequency difference between the clock signal that is turned back from the output destination of the internal clock signal and the internal clock signal are calculated. And a frequency difference output unit that outputs a data signal including a frequency difference from the clock frequency accuracy calculation unit to an output destination of the internal clock signal.

  In the clock supply device of the present invention, the clock output unit and the frequency difference output unit may simultaneously transmit the internal clock signal and the data signal using the same transmission path.

  The above inventions can be combined as much as possible.

  According to the present invention, even when there is no clock reference signal and there are two clock paths, an abnormal clock path can be monitored in each clock path.

It is a figure showing the clock supply system in the invention system. It is a figure showing the detailed structure of the clock supply apparatus of this invention. It is a figure showing the conventional clock supply system. It is a figure showing the detailed structure of the conventional clock supply apparatus. An example of switching transition when a conventional clock supply device is subordinate to a 0-system clock is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  In the present embodiment, a clock path monitoring switching method is proposed in which a clock signal and a data signal, such as Synchronous Ethernet (registered trademark), are transmitted through the same transmission path and there are two inputs of the 0 system 1 system.

FIG. 1 shows an example of a clock supply system according to this embodiment. As shown by a solid line and a broken line in FIG. 1, the sub-master node 92 ₀ and 92 ₁ and the slave node 93A~93H clock dependent source is usually series (0-based) / standby system (system 1) taking a redundant configuration. Here, the data signal and the clock signal are transmitted through the same transmission line between the solid line and the broken line between the nodes. Normally, when the input is interrupted by the 0 system clock signal distributed from the 0 system (working system) clock path and the current system is disconnected, the clock supply device uses the standby system as the standby system (1 system) clock path. Is switched to the 1-system clock signal distributed from. Each node has a structure in which the received clock signal is turned back to the subordinate source.

  Hereinafter, details of the clock supply device and the clock supply method according to the present embodiment will be described. In this embodiment, as an example, a clock supply method and a clock supply apparatus in the slave node 93A will be described.

FIG. 2 shows an example of the structure of the clock supply device according to this embodiment installed in each node of FIG. Two or more input signals with different paths are input to the input units ₁₁₀ and 11 ₁ . For example, if the clock supply device 10 is installed in the slave node 93A, the input signal is input from the sub master node 92 ₀ and 92 _1. Oscillating unit 17 oscillates either of the input unit 11 ₀ and 11 clock signal and the frequency synchronized with the internal clock signal contained in the input signal inputted to the _1.

The clock supply device 10 according to the present embodiment has a configuration for monitoring the clock path of the clock signal input to the slave node 93A. For example, the clock supply apparatus 10 according to the present embodiment includes an input unit 11 ₀ and 11 _1, a clock extraction part 12 ₀ and 12 _1, a clock information reader 13 ₀ and 13 _1, the data that functions as a clock folded portion and an output unit 14 ₀ and 14 _1, a monitoring unit 15, a.

  The clock supply device 10 according to the present embodiment has a configuration for monitoring the clock path of the clock signal input to the slave nodes 93E and 93F installed at the subsequent stage of the clock supply device 10. For example, the clock supply device 10 according to the present embodiment includes a data output unit 21 that functions as a clock output unit and a frequency difference output unit, a return clock extraction unit 22, a clock frequency accuracy calculation unit 23, and a clock information generation unit 24. And comprising.

  The clock supply method according to the present embodiment includes a clock return procedure, a monitoring procedure, and a switching procedure in order.

In the clock loopback procedure, a clock signal is extracted from two or more input signals having different paths, and the extracted clock signal is looped back to the transmission source of the input signal.
At this time, the sub-master node 92 ₀ and 92 ₁ which is disposed upstream of the slave node 93A from the data output section 21 as the clock output unit to output the internal clock signal that oscillates in each of the oscillator 17. The input unit 11 ₀ is inputted internal clock signal of the sub-master node 92 ₀ as a clock signal C _0, the input unit 11 ₁ internal clock signal of the sub-master node 92 ₁ is input as the clock signal C _1.

The clock extraction units ₁₂₀ and 12 ₁ extract the clock signals C ₀ and C ₁ from the input signal. The data output units 14 ₀ and 14 ₁ function as a clock return unit, and transmit the clock signal to the sub-master nodes 92 ₀ and 92 ₁ of the subordinate source, thereby looping back the extracted clock signal to the subordinate source. For example, the data output unit 14 ₀ transmits the extracted clock signal of the clock extraction part 12 ₀ to submaster node 92 _0, the data output unit 14 ₁ is sub-master node 92 ₁ a clock signal extracted clock extraction section 12 ₁ Send to. The data output unit 14 ₀ and 41 ₁ may be transmitted in addition to data signals of a clock signal.

Clock signal folded back from the clock supply device 10 of the slave node 93A is extracted by sub-master node 92 ₀ and 92 ₁ of the folded clock extracting unit 22 of the clock supply device 10 is a dependent source. The clock frequency accuracy calculator 23 of the sub master nodes 92 ₀ and 92 ₁ calculates the frequency difference A ₀ and A ₁ between the clock signal from the slave node 93A and the internal clock signal in its own clock supply device 10. The clock information generation unit 24 of the sub master nodes 92 ₀ and 92 ₁ creates clock information D ₀ and D ₁ including the frequency differences A ₀ and A ₁ calculated by the clock frequency accuracy calculation unit 23.

The data output unit 21 of the sub master nodes 92 ₀ and 92 ₁ supplies the data signal including the clock information D ₀ and D ₁ created by the clock information generation unit 24 to the slave node 93A as a frequency difference output unit. Transmit to device 10. Thus, clock information _{D 0} of the sub-master node 92 ₀ is inputted as an input signal to the input unit 11 _0, clock information _{D 1} of the sub-master node 92 ₁ is input as an input signal to each of the input unit 11 _1.

Here, as in Synchronous Ethernet (registered trademark) (Non-patent Document 1), the clock supply device 10 is transmitted with a clock signal and a data signal from each subordinate source through one transmission path. For example, the input signal to the input unit 11 ₀ includes clock signal C ₀ and the clock information D _0, the input signal to the input unit 11 ₁ includes a clock signal C ₁ and the clock information D _1. The transmission of the clock signal and the data signal is, for example, ITU-T G. The method is according to 8261.

In the monitoring procedure, it is determined whether or not the dependent clock path is normal.
Clock supply device of the slave node 93A 10, at the clock information reading section 13 reads the clock information D ₀ and D ₁ generated by the clock supply apparatus 10 for each dependent source calculated clock frequency difference A ₀ and A ₁ is output to the monitoring unit 15. The monitoring unit 15 compares a threshold value _{AT in} which the clock frequency differences A ₀ and A ₁ acquired from the clock information reading unit 13 are set in advance. When the clock frequency difference A ₀ is larger than the preset threshold value _AT , it is determined that the 0-system clock path is abnormal, and when the clock frequency difference A ₁ is larger than the preset threshold value _AT , It is determined that the clock path is abnormal.

In the switching procedure, the clock signal C ₁₀ oscillated by the oscillating unit 17 is frequency-synchronized with the clock information D ₀ or D ₁ determined that the clock path is normal in the monitoring procedure. When the synchronized clock path of the oscillation unit 17 is abnormal, the monitoring unit 15 sends a switching signal to the switching unit 16 to switch to a normal clock path. As a result, the oscillation unit 17 is frequency-synchronized with the clock signal of the clock path that the monitoring unit 15 determines to be normal.

For example, when the clock supply device 10 of the slave node 93A is synchronized with the 0-system input signal and the oscillation unit 17 is synchronized, and the 0-system clock signal _C0 becomes abnormal, the 0-system clock extraction unit 12 ₀ is extracted by the clock is turned back to the clock supply apparatus 10 of the sub master node 92 ₀ is a dependent source, at sub-master node 92 ₀ clock frequency accuracy calculation unit 23, is set in the monitoring portion 15 of the slave node 93A A frequency difference greater than a threshold value is calculated. Therefore the frequency difference is transmitted to the slave node 93A clock supply device 10 serving as clock information D _0, the clock signal C ₀ 0 system at the monitoring unit 15 of the slave node 93A is determined to be abnormal. Thereafter, the switching signal at the slave node 93A is transmitted to the switching unit 16, an oscillation unit 17 performs clock signal C ₁ and the frequency synchronization of the normal 1 system.

  When the clock signal output from the switching unit 16 is a clock equivalent to the clock signal output from the oscillation unit 17 without noise or the like, the clock supply device 10 may not include the oscillation unit 17.

From the above, the sub-master node 92 ₀ and 92 ₁ are the data output section 21, the folded clock extraction part 22, a clock frequency accuracy calculation unit 23 and the clock information generating unit 24, the slave node 93A is the clock extraction part 12 ₀ and 12 ₁ By providing the data output units 14 ₀ and 14 ₁ , the clock information reading units 13 ₀ and 13 ₁ , the monitoring unit 15, and the switching unit 16, the clock supply device 10 provided in the slave node 93 A has no clock reference signal, and Even in a redundant configuration with two clock paths of the 0 system and the 1 system, an abnormal clock path can be determined. As a result, the clock supply device 10 provided in the slave node 93A can switch to the normal clock path.

In the present embodiment, as an example, an example has been described of the slave node 93A, the clock supply apparatus 10 according to the present embodiment can be applied to all nodes except the master node 91 ₀ and 91 _1. For example, it may reside in any of the sub-master node 92 ₀ and 92 ₁ and the slave node 93A～93H. If the slave node 93E and 93F provided the clock supply apparatus 10, the clock signal _{C E} from the slave node 93A is input as a clock signal _{C 0,} the clock signal _{C E} from the slave node 93B is input as a clock signal _{C 1} .

In the present embodiment, the data output unit 21, the return clock extraction unit 22, the clock frequency accuracy calculation unit 23, and the clock information generation unit 24 are provided, but the present invention is not limited to this. The data output unit 21, the return clock extraction unit 22, the clock frequency accuracy calculation unit 23, and the clock information generation unit 24 may be provided with a number equal to or greater than the number of slave nodes installed at the subsequent stage of the clock supply device 10. For example, if the clock supply device 10 is provided in the master node 91 ₀ shown in FIG. 1, the clock supply apparatus 10, the data output section 21, the folded clock extraction section 22, the clock frequency accuracy calculation unit 23 and the clock information generating unit 24 4 Have more than one.

In addition, one data output unit 21 does not exist for each clock information generation unit 24, and clock information D _E and D _F from two or more clock information generation units 24 are integrated into one data output unit. A data signal may be output. In this case, the signal may be distributed using an electrical and optical distributor for transmission to a plurality of clock supply devices in the subsequent stage.

  In addition, since the node installed in the most subsequent stage does not need to monitor the clock path of the clock signal input to the node installed in the subsequent stage, the data output unit 21, the loopback clock extracting unit 22, the clock frequency accuracy calculating unit 23 and the clock information generator 24 may not be provided.

  The present invention can be applied to the information communication industry.

10: clock supply device 11 ₀ , 11 ₁ : input unit 12 ₀ , 12 ₁ : clock extraction unit 13 ₀ , 13 ₁ : clock information reading unit 14 ₀ , 14 ₁ : data output unit 15: monitoring unit 16: switching unit 17 : Oscillator 21: Data output unit 22: Loop clock extraction unit 23: Clock frequency accuracy calculation unit 24: Clock information generation unit 91 ₀ , 91 ₁ : Master node 92 ₀ , 92 ₁ : Sub master nodes 93A, 93B, 93C, 93D, 93E, 93F, 93G, 93H: Slave node 94: GPS receiver 110: Clock supply device 111 ₀ , 111 ₁ : Clock frequency accuracy calculation unit 112: Monitoring unit 113: Oscillating unit 114: Switch

Claims (8)

A clock return procedure for extracting a clock signal from two or more input signals having different paths and returning the extracted clock signal to the transmission source of the input signal;
The frequency difference between the clock signal folded back to the transmission source and the internal clock signal of the transmission source is acquired from the transmission source, and the clock path is abnormal when the acquired frequency difference is greater than or equal to a preset threshold value A monitoring procedure for determining that the clock path is normal if it is within the threshold;
The clock supply method which has in order.   2. The clock supply method according to claim 1, further comprising a switching procedure for frequency-synchronizing an internal clock signal with a clock signal determined to have a normal clock path in the monitoring procedure after the monitoring procedure.   3. The clock supply method according to claim 1, wherein in the monitoring procedure, a data signal for transmitting the frequency difference is simultaneously transmitted using the same transmission path as the input signal in the clock loopback procedure.   In the monitoring procedure, the data signal transmitting the frequency difference and the clock signal are converted into ITU-T G. The clock supply method according to claim 3, wherein the transmission is performed by a method according to 8261. An input unit to which two or more input signals having different paths are input;
A clock return unit for returning the clock signal included in each input signal to the transmission source of the input signal;
An oscillator that oscillates an internal clock signal that is frequency-synchronized with a clock signal included in any of the input signals;
A clock information reading unit for reading frequency difference information between the clock signal folded back to the transmission source and the internal clock signal of the transmission source from the input signal;
A monitoring unit that determines that the clock path is abnormal when the frequency difference is equal to or greater than a preset threshold, and that determines that the clock path is normal when the frequency difference is within the threshold;
A clock supply device comprising:   The clock supply device according to claim 5, further comprising: a switching unit that synchronizes the frequency of the oscillation unit with a clock signal of a clock path that is determined to be normal by the monitoring unit. A clock output unit for outputting an internal clock signal generated by the oscillation unit;
A clock frequency accuracy calculator that calculates a frequency difference between the clock signal folded from the output destination of the internal clock signal and the internal clock signal;
A frequency difference output unit for outputting a data signal including a frequency difference from the clock frequency accuracy calculation unit to an output destination of the internal clock signal;
The clock supply device according to claim 5, further comprising:   8. The clock supply device according to claim 7, wherein the clock output unit and the frequency difference output unit simultaneously transmit the internal clock signal and the data signal using the same transmission path.

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