WO2019167361A1 - Optical signal reception device, optical signal reception method, and non-transitory computer-readable medium - Google Patents

Optical signal reception device, optical signal reception method, and non-transitory computer-readable medium Download PDF

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Publication number
WO2019167361A1
WO2019167361A1 PCT/JP2018/043364 JP2018043364W WO2019167361A1 WO 2019167361 A1 WO2019167361 A1 WO 2019167361A1 JP 2018043364 W JP2018043364 W JP 2018043364W WO 2019167361 A1 WO2019167361 A1 WO 2019167361A1
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signal
clock signal
clock
optical signal
optical
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PCT/JP2018/043364
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French (fr)
Japanese (ja)
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高橋　森生
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日本電気株式会社
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • the present disclosure relates to an optical signal receiving apparatus, an optical signal receiving method, and a control program.
  • the client signal In an optical communication system in which a signal from a client (client signal) is wavelength-multiplexed and transmitted, the client signal is converted into a transmission method signal (line-side signal) suitable for wavelength-division multiplexing transmission.
  • a transmission method signal line-side signal
  • the signal on the line side (line signal) and the client signal are synchronized, and the client signal does not exceed or falls within the frame of the line signal.
  • the client signal when the client signal is accommodated in the frame of the line signal, data excess / deficiency occurs due to the clock frequency difference between the client signal and the line signal.
  • This excess / deficiency information is stored in JC (Justification Control) bytes in the frame of the line signal, and the client signal is decoded on the receiver (optical signal receiving device) side based on the information of the JC bytes. That is, in the asynchronous mapping method, the client signal can be decoded by generating a clock (clock signal) based on the JC byte.
  • a phase synchronization unit (PLL [Phase Locked Loop] unit) that performs phase control and multiplication processing of a clock signal has the following functions. That is, when detecting an abnormality such as an input clock signal deviating from the assumed frequency range, the PLL unit operates based on the immediately preceding phase information stored in the internal memory of the PLL unit and has a function of fixing phase control.
  • Patent Document 1 provides a configuration in which a clock is externally input to the PLL unit, and in addition to LOS (Loss of Signal), switching to an external clock is performed in the case of out of frame synchronization such as OOF (Out of Frame). Techniques to do are disclosed.
  • Patent Document 2 discloses a transmission device and a reception device for the purpose of suppressing jitter and wander caused by staff.
  • the number of client signal data mapped to the high-order transmission frame per unit timing signal and the data of the client signal to be output using the unit timing signal synchronized with the high-order transmission frame The difference with the number is integrated and measured.
  • staff and destuffing are performed so that the integration result becomes zero.
  • a high-order transmission frame is used as a backup system in the case where a clock abnormality occurs in a high-order transmission frame.
  • Information on the number of received data is stored in advance as a data string. In this receiving apparatus, the number of received data is sequentially output as the number of received data received between higher-order frame timings.
  • An object of the present disclosure is to provide an optical signal receiving device, an optical signal receiving method, and a control program that solve the above-described problems.
  • the abnormal operation time that can occur in the phase synchronization unit at the time of failure is long, and the frequency fluctuation of the decoding clock of the client signal becomes large.
  • An optical signal receiving device for the first aspect of the present disclosure is provided.
  • a clock extractor for extracting the first clock signal from the input optical signal;
  • a clock generator for generating a second clock signal;
  • a phase synchronization unit that inputs a clock signal and outputs a clock signal after phase synchronization;
  • a control unit that switches a clock signal to be input to the phase synchronization unit between the first clock signal and the second clock signal based on the light intensity of the optical signal; It is equipped with.
  • An optical signal receiving method includes: Extracting a first clock signal from the input optical signal; Generating a second clock signal; A phase synchronization step for inputting a clock signal and outputting a clock signal after phase synchronization; Switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal; It is what has.
  • the control program is: In an optical signal receiving device comprising a clock generator for generating a clock signal and a light intensity detector for detecting the light intensity of the input optical signal, Extracting a first clock signal from the input optical signal; Generating a second clock signal by the clock generator; A phase synchronization step for inputting a clock signal and outputting a clock signal after phase synchronization; Switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal; Is a control program for executing
  • the present disclosure it is possible to provide an optical signal receiving device, an optical signal receiving method, and a control program that solve the above-described problems.
  • the time of abnormal operation that can occur in the phase synchronization unit at the time of failure can be further shortened, and the frequency fluctuation of the decoding clock of the client signal can be reduced. .
  • FIG. 3 is a functional block diagram illustrating a configuration example of an optical signal receiving device according to Embodiment 1.
  • FIG. FIG. 6 is a diagram illustrating a configuration example of an optical signal receiving device according to a second embodiment. It is a figure which shows the structure of the optical signal receiver which concerns on a comparative example. It is a figure which shows the hardware structural example of a part of optical signal receiver.
  • FIG. 1 is a functional block diagram illustrating a configuration example of an optical signal receiving apparatus according to the first embodiment.
  • the optical signal receiving apparatus 1 includes a clock extraction unit 1a, a clock generation unit 1b, a phase synchronization unit (PLL unit) 1c, and a control unit 1d.
  • the optical signal receiving device 1 can be a receiving device in an optical transmission system, and can also be called an optical transmission receiving device, a receiver, or the like.
  • control unit 1d the clock extraction unit 1a, and the PLL unit 1c can be realized by an integrated circuit (Integrated Circuit). Further, a part of the control unit 1d can be realized by, for example, a CPU (Central Processing Unit), a working memory, and a non-volatile storage device storing a program.
  • CPU Central Processing Unit
  • working memory a working memory
  • non-volatile storage device storing a program.
  • the clock extraction unit 1a extracts a clock signal (hereinafter referred to as a first clock signal) from the input optical signal.
  • the clock generator 1b is a part that generates a clock signal (hereinafter referred to as a second clock signal), and can be an oscillator such as a crystal oscillator, for example.
  • the PLL unit 1c is a part that performs phase synchronization control, inputs a clock signal, and outputs a clock signal after phase synchronization.
  • the PLL unit 1c can be configured to perform not only phase synchronization control but also multiplication processing and the like.
  • the clock signal output from the PLL unit 1c can be used for decoding the input optical signal.
  • the control unit 1d switches the clock signal to be input to the PLL unit 1c between the first clock signal and the second clock signal based on the light intensity of the input optical signal.
  • the control unit 1d can also be referred to as a switching unit.
  • the second clock signal is input to the PLL unit 1c as necessary based on the light intensity of the input optical signal.
  • the light intensity can be obtained instantaneously by converting an optical signal into an electrical signal. Therefore, according to the optical signal receiving apparatus 1 according to the present embodiment, the time of abnormal operation that can occur in the PLL unit 1c at the time of failure can be made shorter than the case where it is determined after analyzing the contents of the electrical signal. The frequency fluctuation of the signal decoding clock can be reduced. Therefore, according to the optical signal receiving device 1 according to the present embodiment, the supply of the clock signal at the time of failure can be stabilized.
  • FIG. 2 is a diagram illustrating a configuration example of the optical signal receiving apparatus according to the second embodiment
  • FIG. 3 is a diagram illustrating a configuration of the optical signal receiving apparatus according to the comparative example.
  • the optical signal receiving apparatus 2 can include a client signal processing unit 10, a control unit 20, an oscillator 22, a PLL unit 30, and an optical branching unit 40.
  • the control unit 20 is a part that controls the client signal processing unit 10, and is an example of the control unit 1d in FIG.
  • the oscillator 22 and the PLL unit 30 are examples of the clock generation unit 1b and the phase synchronization unit 1c in FIG. 1, respectively.
  • the example of providing the oscillator 22 outside the control unit 20 is given.
  • a clock signal obtained by frequency division and multiplication inside the control unit 20 or a clock signal generated from the operation clock of the control unit 20 is used. It can also be used.
  • the PLL unit 30 performs phase control and multiplication processing of a clock signal supplied to the demapper unit 13 described later.
  • the optical branching unit 40 is arranged to branch the monitor light signal from the line-side signal (line signal) that is the input optical signal, that is, to branch the monitor light from the input light indicating the line signal. Yes.
  • the monitor light signal is input to the control unit 20, and the remaining input light signal branched from the monitor light is input to the client signal processing unit 10.
  • the client signal processing unit 10 decodes the line side signal (line signal) into a client signal.
  • the input optical signal is a line signal in which the client signal is accommodated, and the clock signal after phase synchronization output from the PLL unit 30 is used for decoding the client signal.
  • This line signal is a signal in which a client signal is accommodated in a frame by an asynchronous mapping method on the transmission side.
  • the client signal processing unit 10 will be specifically described.
  • the client signal processing unit 10 can include an ALM (Alarm) detection unit 11, a client signal detection unit 12, and a demapper unit 13.
  • ALM Alarm
  • the ALM detection unit 11 is an example of a failure detection unit that converts an optical signal (line signal) into an electrical signal and detects a failure of the optical signal (a frame synchronization failure indicated by the electrical signal) from the electrical signal.
  • the ALM detection unit 11 detects a failure (signal disconnection, etc.) of the line signal and notifies the control unit 20 of the failure at the time of the failure.
  • the ALM detection unit 11 monitors the frame based on the electrical signal converted from the optical signal, detects the presence or absence of a failure, and outputs a detection signal to the control unit 20 when a failure is detected. Can be configured.
  • the ALM detection unit 11 can detect that there is a failure when the state is Loss of Signal (LOS) or Loss of Frame (LOF) (3 msec protection signal of OOF).
  • LOS Loss of Signal
  • LEF Loss of Frame
  • the client signal detection unit 12 is an example of the clock extraction unit 1a in FIG. 1, and generates (extracts) a clock signal based on the JC byte included in the frame of the line signal.
  • the JC byte is frequency adjustment information and can be a stuff byte.
  • the staff byte is a recommendation G. ITU-T (International Telecommunication Union Telecommunication Standardization Sector). 709 / Y. 1331.
  • the clock signal generated by the client signal detection unit 12 is supplied to the control unit 20 that controls the client signal processing unit 10.
  • the demapper unit 13 uses the clock signal supplied from the PLL unit 30 to decode the client signal.
  • the control unit 20 controls the client signal processing unit 10 and monitors the state. Therefore, the control unit 20 monitors the phase lock state of the PLL unit 30. At normal times, the control unit 20 supplies the first clock signal supplied from the client signal detection unit 12 to the PLL unit 30.
  • the control unit 20 switches from the first clock signal from the client signal detection unit 12 to the clock signal (second clock signal) from the oscillator 22 to the PLL unit 30. Supply a clock signal.
  • the optical signal receiving apparatus 2 includes an oscillator 22, and the control unit 20 can include a selector 21, a logical sum 23, and an optical input break detection unit 24.
  • the selector 21 receives the first clock signal from the client signal detection unit 12 and the second clock signal from the oscillator 22, selects one of the clock signals, and outputs the selected clock signal to the PLL unit 30. This selection can be made based on the output from the logical sum 23.
  • the logical sum 23 can be a logical sum circuit, for example.
  • One input of the logical sum 23 can be a detection signal output from the ALM detection unit 11, and the other input can be a detection signal output from the light input break detection unit 24. For this reason, the ALM detection unit 11 outputs a detection signal to the logical sum 23 of the control unit 20 when a failure is detected.
  • the light input break detection unit 24 is an example of a light intensity detection unit that detects the light intensity of the input optical signal.
  • the light input break detection unit 24 receives the optical signal (monitor optical signal) branched by the optical branching unit 40 and inputs the optical signal. The signal strength of is detected. Then, when the detected signal intensity is equal to or less than a predetermined value (predetermined threshold value), the light input disconnection detection unit 24 outputs a detection signal that determines that the signal is interrupted and switches the selector 21 to the logical sum 23. In this way, the light input break detection unit 24 issues a light input break alarm to the logical sum 23 when the light input level from the light branching unit 40 falls below a certain value.
  • the logical sum 23 outputs to the selector 21 a signal for switching the clock signal to the second clock signal when receiving either the detection signal from the ALM detection unit 11 or the detection signal from the light input break detection unit 24. To do. As a result, the selector 21 detects the occurrence of a failure from the ALM detection unit 11 or the clock signal output to the PLL unit 30 when the light input break detection unit 24 detects the light input break. Switch to the second clock signal generated at 22.
  • control unit 20 inputs the first clock signal to the PLL unit 30 when the light intensity is equal to or greater than the predetermined value, and outputs the second clock signal to the PLL unit when the light intensity is less than the predetermined value. Switching is performed so as to input to 30.
  • the line signal is output as a client signal through the client signal processing unit 10, the ALM detection unit 11, the client signal detection unit 12, and the demapper unit 13.
  • the ALM detection unit 11 detects the presence or absence of a fault in the line signal, and the client signal detection unit 12 generates a first clock signal based on the JC byte included in the line signal frame.
  • the first clock signal generated by the client signal detection unit 12 is supplied to the control unit 20.
  • the control unit 20 supplies this clock signal to the PLL unit 30, and the PLL unit 30 performs phase control so that the demapper unit 13 can correctly decode the client signal, and supplies it to the demapper unit 13.
  • the demapper unit 13 decodes the client signal using the clock signal from the PLL unit 30.
  • the JC byte of the line signal is not a normal value, and the client signal detection unit 12 outputs an abnormal clock signal. Since phase control is performed based on this abnormal clock signal, there is a problem that it takes a very long time to stabilize.
  • the optical signal receiving device 3 according to the comparative example illustrated in FIG. 3 includes a client signal processing unit 60, a control unit 70, and a PLL unit 80.
  • the client signal processing unit 60 includes an ALM detection unit 61, a client signal detection unit 62, and a demapper unit 63.
  • the line signal is output as a client signal through the ALM detection unit 61, the client signal detection unit 62, and the demapper unit 63 of the client signal processing unit 60.
  • the ALM detection unit 61 detects the presence or absence of a line signal failure.
  • the client signal detection unit 62 generates a clock signal based on the JC byte included in the frame of the line signal.
  • the clock signal generated by the client signal detection unit 62 is supplied to the control unit 70 that controls the client signal processing unit 60.
  • the control unit 70 supplies this clock signal to the PLL unit 80, and the PLL unit 80 performs phase control and multiplication processing so that the demapper unit 63 can correctly decode the client signal, and supplies the demapper unit 63.
  • the demapper unit 63 decodes the client signal using the clock signal supplied from the PLL unit 80.
  • the JC byte of the line signal is not a normal value, and the client signal detection unit 62 outputs an abnormal clock signal.
  • the PLL unit 80 When the PLL unit 80 detects an abnormality such that the input clock signal is out of the assumed frequency range, the PLL unit 80 operates based on the immediately preceding phase information stored in the internal memory of the PLL unit 80 and fixes the phase control. However, if an abnormal clock signal as described above is intermittently input, phase control is performed based on the abnormal clock signal, and it takes a very long time to stabilize when the line signal is restored.
  • the client is notified of the occurrence of the failure on the line side. Therefore, in order to transfer these information, the same as when the line signal is normal A clock supply is required.
  • This notification corresponds to, for example, a case where the client signal is OTU [Optical Channel Transport Unit] 4) and alarm transmission of AIS (Alarm Indication Signal).
  • the client signal is Ethernet, the above notification is made by inserting an LF (Local Fault) signal or an IDLE signal.
  • the optical signal receiving device 2 detects whether or not a failure such as a signal interruption has occurred in the line signal. And it recognizes with the detection signal from the light input interruption detection part 24. When the optical signal receiving apparatus 2 recognizes any detection signal, the optical signal receiving apparatus 2 switches the selector 21 to supply the second clock signal from the oscillator 22, and stabilizes the clock signal to the PLL unit 30.
  • the optical input break detection unit 24 and the ALM detection unit 11 can determine the presence or absence of a failure, so that switching can be performed in a shorter time as follows. it can. That is, for example, when the signal disappears or the intensity becomes equal to or lower than the threshold value, the light input break detection unit 24 makes a determination based on the light intensity and switches the selector 21. Switching can be performed.
  • the optical signal receiving device 2 not only the problem in the comparative example is solved, but also an abnormal clock is generated in the PLL unit 30 as compared with the case of switching based on the result of analyzing the contents of the electric signal. It is possible to shorten the time during which the signal (JC byte) is input. Therefore, according to the optical signal receiving device 2, the operation of the PLL unit 30 is quickly stabilized when recovered from a failure such as data loss of the line signal, that is, the supply of the clock signal to the demapper unit 13 is stabilized. It can be made.
  • the first clock is extracted from the non-monitor optical signal input from the optical branching unit 40, and the control unit 20 transmits the first clock to the PLL unit 30 based on the light intensity of the monitor optical signal.
  • the input clock signal is switched between the first clock signal and the second clock signal. As a result, the clock signal can be selected through a path different from the decoding of the client signal.
  • optical signal receiving device 2 can be configured to directly input the output from the optical input break detection unit 24 to the selector 21 without providing the logical sum 23 and the ALM detection unit 11.
  • control unit 20 switches the clock signal input to the PLL unit 30 between the first clock signal and the second clock signal based on both the light intensity and the failure detection result by the ALM detection unit 11.
  • the following cases can be dealt with. That is, with such a configuration, when the optical signal is not lost and the light intensity is equal to or higher than the threshold value, but the signal has an error, the selector 21 is switched from the detection signal from the ALM detection unit 11. be able to.
  • FIG. 4 is a diagram illustrating a hardware configuration example of a part of the optical signal receiving apparatuses 1 and 2 according to the first and second embodiments. The same applies to the other embodiment [a].
  • the optical signal receiving apparatus 100 includes a clock generation unit that generates a clock signal and a light intensity detection unit that detects the light intensity of the input optical signal.
  • Part of the functions of the control unit 1d and the clock extraction unit 1a in the optical signal receiving apparatus 1 described in the first embodiment is realized by the processor 101 reading and executing a control program stored in the memory 102.
  • Part of the functions of the control unit 20 and the client signal processing unit 10 in the optical signal receiving device 2 described in the second embodiment is realized by the processor 101 reading and executing a control program stored in the memory 102.
  • Non-transitory computer readable media include various types of tangible storage media (tangible storage medium).
  • Examples of non-transitory computer readable media include magnetic recording media (eg, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (eg, magneto-optical disks).
  • this example includes a CD-ROM (Read Only Memory), a CD-R, and a CD-R / W.
  • this example includes a semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable ROM), flash ROM, RAM (Random Access Memory)).
  • the program may also be supplied to the computer by various types of temporary computer-readable media.
  • Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves.
  • the temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.
  • the present disclosure can also take a form as an optical signal receiving method.
  • the optical signal receiving method includes a step of extracting a first clock signal from an input optical signal, a step of generating a second clock signal, a phase synchronization that inputs a clock signal and outputs a clock signal after phase synchronization. Steps. Further, the optical signal receiving method includes a step of switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal.
  • the control program is a program for causing the optical signal receiving apparatus to execute each step described above.
  • Optical signal receiver 1a Clock extraction unit 1b Clock generation unit 1c, 30 Phase synchronization unit (PLL unit) 1d, 20 Control unit 10 Client signal processing unit 11 ALM detection unit 12 Client signal detection unit 13 Demapper unit 21 Selector 22 Oscillator 23 Logical sum 24 Optical input break detection unit 40 Optical branching unit 101 Processor 102 Memory

Abstract

The purpose of the present invention is to shorten the duration of a possible abnormal operation of a phase synchronization unit of an optical signal reception device in the event of a fault, and to reduce fluctuation in the frequency of a clock used for decoding a client signal. The optical signal reception device (1) is provided with: a clock extraction unit (1a) for extracting a first clock signal from an optical signal having been input; a clock generation unit (1b) for generating a second clock signal; and a phase-synchronization unit (1c) for receiving input of a clock signal and outputting a phase-synchronized clock signal. The optical signal reception device (1) is further provided with a control unit (1d) for switching the clock signal to be input to the phase synchronization unit (1c) between the first clock signal and the second clock signal on the basis of the light intensity of the optical signal.

Description

光信号受信装置、光信号受信方法、及び非一時的なコンピュータ可読媒体Optical signal receiving apparatus, optical signal receiving method, and non-transitory computer-readable medium
　本開示は、光信号受信装置、光信号受信方法、及び制御プログラムに関する。 The present disclosure relates to an optical signal receiving apparatus, an optical signal receiving method, and a control program.
　クライアントからの信号（クライアント信号）を波長多重して伝送する光通信システムでは、クライアント信号を波長多重伝送に適した伝送方式の信号（ライン側の信号）に変換される。この変換方法として、同期マッピング方式と非同期マッピング方式の２種類がある。同期マッピング方式では、ライン側の信号（ライン信号）とクライアント信号の同期がとれており、クライアント信号が過不足なく、ライン信号のフレーム内に収まる。 In an optical communication system in which a signal from a client (client signal) is wavelength-multiplexed and transmitted, the client signal is converted into a transmission method signal (line-side signal) suitable for wavelength-division multiplexing transmission. There are two types of conversion methods, a synchronous mapping method and an asynchronous mapping method. In the synchronous mapping method, the signal on the line side (line signal) and the client signal are synchronized, and the client signal does not exceed or falls within the frame of the line signal.
　これに対し、非同期マッピング方式では、クライアント信号をライン信号のフレーム内に収容する際に、クライアント信号とライン信号のクロック周波数差が原因でデータの過不足が生じる。この過不足の情報を、ライン信号のフレーム内のＪＣ（Justification Control）バイトに収納しておき、受信機（光信号受信装置）側で、このＪＣバイトの情報を基にクライアント信号を復号する。即ち、非同期マッピング方式では、ＪＣバイトを基にクロック（クロック信号）を生成することで、クライアント信号を復号することができる。 On the other hand, in the asynchronous mapping method, when the client signal is accommodated in the frame of the line signal, data excess / deficiency occurs due to the clock frequency difference between the client signal and the line signal. This excess / deficiency information is stored in JC (Justification Control) bytes in the frame of the line signal, and the client signal is decoded on the receiver (optical signal receiving device) side based on the information of the JC bytes. That is, in the asynchronous mapping method, the client signal can be decoded by generating a clock (clock signal) based on the JC byte.
　この時、ライン信号に信号断などの障害が発生すると、ライン信号のＪＣバイトが正常な値でなくなり、正常でないクロック信号を基にクライアント信号の復号が行われてしまう。これに対応するため、クロック信号の位相制御や逓倍処理する位相同期部（ＰＬＬ［Phase Locked Loop］部）は、次の機能を有する。即ち、ＰＬＬ部は、入力クロック信号が想定周波数範囲から外れるなどの異常を検知すると、ＰＬＬ部の内部メモリに記憶された直前の位相情報に基づいて動作し、位相制御を固定する機能を有する。 At this time, if a failure such as a signal interruption occurs in the line signal, the JC byte of the line signal is not a normal value, and the client signal is decoded based on the abnormal clock signal. In order to deal with this, a phase synchronization unit (PLL [Phase Locked Loop] unit) that performs phase control and multiplication processing of a clock signal has the following functions. That is, when detecting an abnormality such as an input clock signal deviating from the assumed frequency range, the PLL unit operates based on the immediately preceding phase information stored in the internal memory of the PLL unit and has a function of fixing phase control.
　しかしながら、ＰＬＬ部が直前の位相情報に基づいて動作する場合の問題として、上述のような正常でないクロック信号が断続的に入力されると、その正常でないクロック信号に基づいて位相制御を行ってしまう。そのため、ライン信号の復旧時に、安定するまでに非常に時間がかかってしまうという問題がある。 However, as a problem when the PLL unit operates based on the immediately preceding phase information, when the abnormal clock signal as described above is intermittently input, phase control is performed based on the abnormal clock signal. . Therefore, there is a problem that it takes a very long time to stabilize when the line signal is restored.
　特許文献１には、ＰＬＬ部に外部からクロックを入力する構成を設け、ＬＯＳ（Loss of Signal）の他、ＯＯＦ（Out of Frame）のようなフレーム同期はずれの場合に、外部クロックへの切り替えを行う技術が開示されている。 Patent Document 1 provides a configuration in which a clock is externally input to the PLL unit, and in addition to LOS (Loss of Signal), switching to an external clock is performed in the case of out of frame synchronization such as OOF (Out of Frame). Techniques to do are disclosed.
　また、特許文献２には、スタッフによるジッタ及びワンダを抑圧することを目的とした送信装置、受信装置が開示されている。特許文献２に記載の技術では、高次伝送フレームに同期した単位タイミング信号を使用して、単位タイミング信号あたりに高次伝送フレームにマッピングされるクライアント信号のデータ数と出力されるクライアント信号のデータ数との差分を積算して計測する。そして、この技術では、その積算結果がゼロになるようにスタッフ及びデスタッフを行う。特許文献２に記載の受信装置では、高次伝送フレームにクロック異常が発生した場合の予備系として高次伝送フレームが正常時に高次フレームタイミング間に検出すると想定されるデスタッフの頻度に応じた受信データ数の情報をデータ列として事前に格納する。そして、この受信装置では、その受信データ数を高次フレームタイミング間で受信した受信データ数として順次出力している。 Patent Document 2 discloses a transmission device and a reception device for the purpose of suppressing jitter and wander caused by staff. In the technique described in Patent Document 2, the number of client signal data mapped to the high-order transmission frame per unit timing signal and the data of the client signal to be output using the unit timing signal synchronized with the high-order transmission frame The difference with the number is integrated and measured. In this technique, staff and destuffing are performed so that the integration result becomes zero. In the receiving apparatus described in Patent Document 2, a high-order transmission frame is used as a backup system in the case where a clock abnormality occurs in a high-order transmission frame. Information on the number of received data is stored in advance as a data string. In this receiving apparatus, the number of received data is sequentially output as the number of received data received between higher-order frame timings.
特開２０１０－２０６６２５号公報JP 2010-206625 A 特開２００８－１４８２５０号公報JP 2008-148250 A
　しかしながら、特許文献１に記載の技術では、光信号が変換された電気信号のフレームに基づきＬＯＳ、ＬＯＦ（ＯＯＦの３ｍｓｅｃ保護信号）を判断している。そのため、この技術では、その判断がなされるまでの時間は、異常なＪＣバイト受信によるＰＬＬ部の異常動作が発生し、クライアント信号の復号用クロックの周波数が変動してしまう。また、特許文献２に記載の技術においても、予備系としての受信データ数を出力するまでの時間は、同様にＰＬＬ部の異常動作が発生し、クライアント信号の復号用クロックの周波数が変動してしまう。よって、光信号受信装置において、障害時の位相同期部に生じ得る異常動作の時間をより短くし、クライアント信号の復号用クロックの周波数変動を小さくすることが求められる。 However, in the technique described in Patent Document 1, LOS and LOF (OOF 3 msec protection signal) are determined based on a frame of an electric signal converted from an optical signal. Therefore, in this technique, during the time until the determination is made, an abnormal operation of the PLL unit due to abnormal JC byte reception occurs, and the frequency of the decoding clock of the client signal fluctuates. Also, in the technique described in Patent Document 2, the time until the number of received data as a standby system is output also causes an abnormal operation of the PLL unit, and the frequency of the client signal decoding clock fluctuates. End up. Therefore, in the optical signal receiving apparatus, it is required to shorten the time of abnormal operation that can occur in the phase synchronization unit at the time of failure, and to reduce the frequency fluctuation of the decoding clock of the client signal.
　本開示の目的は、上述した課題を解決する光信号受信装置、光信号受信方法、及び制御プログラムを提供することにある。上記課題は、光信号受信装置において、障害時の位相同期部に生じ得る異常動作の時間が長く、クライアント信号の復号用クロックの周波数変動が大きくなるというものである。 An object of the present disclosure is to provide an optical signal receiving device, an optical signal receiving method, and a control program that solve the above-described problems. In the optical signal receiving apparatus, the abnormal operation time that can occur in the phase synchronization unit at the time of failure is long, and the frequency fluctuation of the decoding clock of the client signal becomes large.
　本開示の第１の態様に係る光信号受信装置は、
　入力された光信号から第１クロック信号を抽出するクロック抽出部と、
　第２クロック信号を発生するクロック発生部と、
　クロック信号を入力し、位相同期後のクロック信号を出力する位相同期部と、
　前記光信号の光強度に基づいて、前記位相同期部へ入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替える制御部と、
　を備えたものである。 An optical signal receiving device according to the first aspect of the present disclosure is provided.
A clock extractor for extracting the first clock signal from the input optical signal;
A clock generator for generating a second clock signal;
A phase synchronization unit that inputs a clock signal and outputs a clock signal after phase synchronization;
A control unit that switches a clock signal to be input to the phase synchronization unit between the first clock signal and the second clock signal based on the light intensity of the optical signal;
It is equipped with.
　本開示の第２の態様に係る光信号受信方法は、
　入力された光信号から第１クロック信号を抽出するステップと、
　第２クロック信号を発生するステップと、
　クロック信号を入力し、位相同期後のクロック信号を出力する位相同期ステップと、
　前記光信号の光強度に基づいて、前記位相同期ステップにおいて入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替えるステップと、
　を有するものである。 An optical signal receiving method according to the second aspect of the present disclosure includes:
Extracting a first clock signal from the input optical signal;
Generating a second clock signal;
A phase synchronization step for inputting a clock signal and outputting a clock signal after phase synchronization;
Switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal;
It is what has.
　本開示の第３の態様に係る制御プログラムは、
　クロック信号を発生するクロック発生部と、入力された光信号の光強度を検出する光強度検出部と、を備えた光信号受信装置に、
　入力された光信号から第１クロック信号を抽出するステップと、
　前記クロック発生部により第２クロック信号を発生するステップと、
　クロック信号を入力し、位相同期後のクロック信号を出力する位相同期ステップと、
　前記光信号の光強度に基づいて、前記位相同期ステップにおいて入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替えるステップと、
　を実行させるための制御プログラムである。 The control program according to the third aspect of the present disclosure is:
In an optical signal receiving device comprising a clock generator for generating a clock signal and a light intensity detector for detecting the light intensity of the input optical signal,
Extracting a first clock signal from the input optical signal;
Generating a second clock signal by the clock generator;
A phase synchronization step for inputting a clock signal and outputting a clock signal after phase synchronization;
Switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal;
Is a control program for executing
　本開示により、上記課題を解決する光信号受信装置、光信号受信方法、及び制御プログラムを提供することができる。即ち、本開示によれば、光信号受信装置において、障害時の位相同期部に生じ得る異常動作の時間をより短くすることができ、クライアント信号の復号用クロックの周波数変動を小さくすることができる。 According to the present disclosure, it is possible to provide an optical signal receiving device, an optical signal receiving method, and a control program that solve the above-described problems. In other words, according to the present disclosure, in the optical signal receiving apparatus, the time of abnormal operation that can occur in the phase synchronization unit at the time of failure can be further shortened, and the frequency fluctuation of the decoding clock of the client signal can be reduced. .
実施形態１に係る光信号受信装置の一構成例を示す機能ブロック図である。3 is a functional block diagram illustrating a configuration example of an optical signal receiving device according to Embodiment 1. FIG. 実施形態２に係る光信号受信装置の一構成例を示す図である。FIG. 6 is a diagram illustrating a configuration example of an optical signal receiving device according to a second embodiment. 比較例に係る光信号受信装置の構成を示す図である。It is a figure which shows the structure of the optical signal receiver which concerns on a comparative example. 光信号受信装置の一部のハードウェア構成例を示す図である。It is a figure which shows the hardware structural example of a part of optical signal receiver.
　以下、図面を参照して、実施形態について説明する。 Hereinafter, embodiments will be described with reference to the drawings.
＜実施形態１＞
　図１は、実施形態１に係る光信号受信装置の一構成例を示す機能ブロック図である。
　図１に示すように、本実施形態に係る光信号受信装置１は、クロック抽出部１ａ、クロック発生部１ｂ、位相同期部（ＰＬＬ部）１ｃ、及び制御部１ｄを有する。光信号受信装置１は、光伝送システムにおける受信側の装置とすることができ、光伝送受信装置、受信機などと称することもできる。 <Embodiment 1>
FIG. 1 is a functional block diagram illustrating a configuration example of an optical signal receiving apparatus according to the first embodiment.
As shown in FIG. 1, the optical signal receiving apparatus 1 according to the present embodiment includes a clock extraction unit 1a, a clock generation unit 1b, a phase synchronization unit (PLL unit) 1c, and a control unit 1d. The optical signal receiving device 1 can be a receiving device in an optical transmission system, and can also be called an optical transmission receiving device, a receiver, or the like.
　例えば、制御部１ｄ、クロック抽出部１ａ、ＰＬＬ部１ｃは集積回路（Integrated Circuit）によって実現することができる。また、制御部１ｄの一部は、例えば、ＣＰＵ（Central Processing Unit）、作業用メモリ、及びプログラムを記憶した不揮発性の記憶装置などによって実現することもできる。 For example, the control unit 1d, the clock extraction unit 1a, and the PLL unit 1c can be realized by an integrated circuit (Integrated Circuit). Further, a part of the control unit 1d can be realized by, for example, a CPU (Central Processing Unit), a working memory, and a non-volatile storage device storing a program.
　クロック抽出部１ａは、入力された光信号からクロック信号（以下、第１クロック信号）を抽出する。クロック発生部１ｂは、クロック信号（以下、第２クロック信号）を発生する部位であり、例えば、水晶発振器等の発振器とすることができる。 The clock extraction unit 1a extracts a clock signal (hereinafter referred to as a first clock signal) from the input optical signal. The clock generator 1b is a part that generates a clock signal (hereinafter referred to as a second clock signal), and can be an oscillator such as a crystal oscillator, for example.
　ＰＬＬ部１ｃは、位相同期制御を行う部位であり、クロック信号を入力し、位相同期後のクロック信号を出力する。無論、ＰＬＬ部１ｃは、位相同期制御のみならず逓倍処理等も併せて行うように構成することができる。ＰＬＬ部１ｃから出力されるクロック信号は、入力された光信号の復号に用いることができる。 The PLL unit 1c is a part that performs phase synchronization control, inputs a clock signal, and outputs a clock signal after phase synchronization. Of course, the PLL unit 1c can be configured to perform not only phase synchronization control but also multiplication processing and the like. The clock signal output from the PLL unit 1c can be used for decoding the input optical signal.
　制御部１ｄは、入力された光信号の光強度に基づいて、ＰＬＬ部１ｃへ入力するクロック信号を第１クロック信号と第２クロック信号との間で切り替える。制御部１ｄは、切り替え部と称することもできる。 The control unit 1d switches the clock signal to be input to the PLL unit 1c between the first clock signal and the second clock signal based on the light intensity of the input optical signal. The control unit 1d can also be referred to as a switching unit.
　本実施形態に係る光信号受信装置１では、上述のように、入力された光信号の光強度に基づいて必要に応じて第２クロック信号をＰＬＬ部１ｃに入力する。そして、光強度は、光信号を電気信号に変換することで瞬時に得ることができる。従って、本実施形態に係る光信号受信装置１によれば、障害時のＰＬＬ部１ｃに生じ得る異常動作の時間を電気信号の内容を解析してから判断する場合より短くすることができ、クライアント信号の復号用クロックの周波数変動を小さくすることができる。よって、本実施形態に係る光信号受信装置１によれば、障害時におけるクロック信号の供給を安定化させることができる。 In the optical signal receiving device 1 according to the present embodiment, as described above, the second clock signal is input to the PLL unit 1c as necessary based on the light intensity of the input optical signal. The light intensity can be obtained instantaneously by converting an optical signal into an electrical signal. Therefore, according to the optical signal receiving apparatus 1 according to the present embodiment, the time of abnormal operation that can occur in the PLL unit 1c at the time of failure can be made shorter than the case where it is determined after analyzing the contents of the electrical signal. The frequency fluctuation of the signal decoding clock can be reduced. Therefore, according to the optical signal receiving device 1 according to the present embodiment, the supply of the clock signal at the time of failure can be stabilized.
＜実施形態２＞
　実施形態２について、図２及び図３を併せて参照しながら、実施形態１との相違点を中心に説明するが、実施形態１で説明した様々な例が適用できる。図２は、実施形態２に係る光信号受信装置の一構成例を示す図で、図３は、比較例に係る光信号受信装置の構成を示す図である。 <Embodiment 2>
The second embodiment will be described mainly with respect to differences from the first embodiment with reference to FIGS. 2 and 3 together, but various examples described in the first embodiment can be applied. FIG. 2 is a diagram illustrating a configuration example of the optical signal receiving apparatus according to the second embodiment, and FIG. 3 is a diagram illustrating a configuration of the optical signal receiving apparatus according to the comparative example.
　図２に示すように、本実施形態に係る光信号受信装置２は、クライアント信号処理部１０、制御部２０、発振器２２、ＰＬＬ部３０、及び光分岐部４０を有することができる。 As shown in FIG. 2, the optical signal receiving apparatus 2 according to the present embodiment can include a client signal processing unit 10, a control unit 20, an oscillator 22, a PLL unit 30, and an optical branching unit 40.
　制御部２０は、クライアント信号処理部１０を制御する部位で、図１の制御部１ｄの一例である。発振器２２、ＰＬＬ部３０は、それぞれ図１のクロック発生部１ｂ、位相同期部１ｃの一例である。発振器２２は、制御部２０の外部に設けた例を挙げているが、制御部２０の内部で分周、逓倍により得られるクロック信号、或いは、制御部２０の動作クロックから生成されるクロック信号を用いることもできる。ＰＬＬ部３０は、後述するデマッパ部１３に供給するクロック信号の位相制御や逓倍処理を行うことになる。 The control unit 20 is a part that controls the client signal processing unit 10, and is an example of the control unit 1d in FIG. The oscillator 22 and the PLL unit 30 are examples of the clock generation unit 1b and the phase synchronization unit 1c in FIG. 1, respectively. The example of providing the oscillator 22 outside the control unit 20 is given. However, a clock signal obtained by frequency division and multiplication inside the control unit 20 or a clock signal generated from the operation clock of the control unit 20 is used. It can also be used. The PLL unit 30 performs phase control and multiplication processing of a clock signal supplied to the demapper unit 13 described later.
　光分岐部４０は、入力された光信号であるライン側の信号（ライン信号）からモニタ光信号を分岐するために、つまりライン信号を示す入力光からモニタ光を分岐するために配設されている。モニタ光信号は制御部２０に入力され、モニタ光を分岐した残りの入力光の信号はクライアント信号処理部１０に入力される。 The optical branching unit 40 is arranged to branch the monitor light signal from the line-side signal (line signal) that is the input optical signal, that is, to branch the monitor light from the input light indicating the line signal. Yes. The monitor light signal is input to the control unit 20, and the remaining input light signal branched from the monitor light is input to the client signal processing unit 10.
　クライアント信号処理部１０は、ライン側の信号（ライン信号）を、クライアント信号に復号する。このように、本実施形態では、入力された光信号は、クライアント信号が収容されたライン信号であり、ＰＬＬ部３０から出力される位相同期後のクロック信号は、クライアント信号の復号に使用される。このライン信号は、送信側において、非同期マッピング方式でフレーム内にクライアント信号収容したものである。 The client signal processing unit 10 decodes the line side signal (line signal) into a client signal. Thus, in this embodiment, the input optical signal is a line signal in which the client signal is accommodated, and the clock signal after phase synchronization output from the PLL unit 30 is used for decoding the client signal. . This line signal is a signal in which a client signal is accommodated in a frame by an asynchronous mapping method on the transmission side.
　クライアント信号処理部１０について具体的に説明する。クライアント信号処理部１０は、ＡＬＭ（Alarm）検出部１１、クライアント信号検出部１２、及びデマッパ部１３を有することができる。 The client signal processing unit 10 will be specifically described. The client signal processing unit 10 can include an ALM (Alarm) detection unit 11, a client signal detection unit 12, and a demapper unit 13.
　ＡＬＭ検出部１１は、光信号（ライン信号）を電気信号に変換し、その電気信号から光信号の障害（その電気信号が示すフレームの同期障害）を検出する障害検出部の一例である。ＡＬＭ検出部１１は、ライン信号の障害（信号断等）を検出し、障害時に制御部２０に障害を伝える。 The ALM detection unit 11 is an example of a failure detection unit that converts an optical signal (line signal) into an electrical signal and detects a failure of the optical signal (a frame synchronization failure indicated by the electrical signal) from the electrical signal. The ALM detection unit 11 detects a failure (signal disconnection, etc.) of the line signal and notifies the control unit 20 of the failure at the time of the failure.
　具体的には、ＡＬＭ検出部１１は、光信号が変換された電気信号に基づきフレームをモニタして障害の有無を検出し、障害を検出した場合に検出信号を制御部２０に出力するように構成することができる。ここで、ＡＬＭ検出部１１は、Ｌｏｓｓ　ｏｆ　Ｓｉｇｎａｌ（ＬＯＳ）、Ｌｏｓｓ　ｏｆ　Ｆｒａｍｅ（ＬＯＦ）（ＯＯＦの３ｍｓｅｃ保護信号）の状態になった場合に、障害有りと検出するようにしておくことができる。 Specifically, the ALM detection unit 11 monitors the frame based on the electrical signal converted from the optical signal, detects the presence or absence of a failure, and outputs a detection signal to the control unit 20 when a failure is detected. Can be configured. Here, the ALM detection unit 11 can detect that there is a failure when the state is Loss of Signal (LOS) or Loss of Frame (LOF) (3 msec protection signal of OOF).
　クライアント信号検出部１２は、図１のクロック抽出部１ａの一例であり、ライン信号のフレームに含まれるＪＣバイトを基にクロック信号を生成（抽出）する。ＪＣバイトは、周波数調整情報であり、スタッフバイトとすることができる。スタッフバイトは、ＩＴＵ－Ｔ（International Telecommunication Union Telecommunication Standardization Sector）の勧告Ｇ．７０９／Ｙ．１３３１に規定されている。 The client signal detection unit 12 is an example of the clock extraction unit 1a in FIG. 1, and generates (extracts) a clock signal based on the JC byte included in the frame of the line signal. The JC byte is frequency adjustment information and can be a stuff byte. The staff byte is a recommendation G. ITU-T (International Telecommunication Union Telecommunication Standardization Sector). 709 / Y. 1331.
　クライアント信号検出部１２で生成されたクロック信号は、クライアント信号処理部１０を制御する制御部２０に供給される。デマッパ部１３は、ＰＬＬ部３０から供給されるクロック信号を用いて、クライアント信号の復号を行う。 The clock signal generated by the client signal detection unit 12 is supplied to the control unit 20 that controls the client signal processing unit 10. The demapper unit 13 uses the clock signal supplied from the PLL unit 30 to decode the client signal.
　制御部２０は、クライアント信号処理部１０の制御、及び状態監視を行う。そのため、制御部２０はＰＬＬ部３０の位相ロック状態の監視を行う。通常時には、制御部２０は、クライアント信号検出部１２から供給された第１クロック信号を、ＰＬＬ部３０に供給する。 The control unit 20 controls the client signal processing unit 10 and monitors the state. Therefore, the control unit 20 monitors the phase lock state of the PLL unit 30. At normal times, the control unit 20 supplies the first clock signal supplied from the client signal detection unit 12 to the PLL unit 30.
　一方、ライン信号の信号断などの障害時には、制御部２０は、クライアント信号検出部１２からの第１クロック信号から、発振器２２からのクロック信号（第２クロック信号）に切り替えて、ＰＬＬ部３０にクロック信号を供給する。 On the other hand, at the time of failure such as signal interruption of the line signal, the control unit 20 switches from the first clock signal from the client signal detection unit 12 to the clock signal (second clock signal) from the oscillator 22 to the PLL unit 30. Supply a clock signal.
　そのための構成として、光信号受信装置２は発振器２２を備えるとともに、制御部２０は、セレクタ２１、論理和２３、及び光入力断検出部２４を有することができる。セレクタ２１は、クライアント信号検出部１２からの第１クロック信号と発振器２２からの第２クロック信号とを入力し、いずれか一方のクロック信号を選択してＰＬＬ部３０に出力する。この選択は、論理和２３からの出力に基づき行うことができる。 As a configuration for that, the optical signal receiving apparatus 2 includes an oscillator 22, and the control unit 20 can include a selector 21, a logical sum 23, and an optical input break detection unit 24. The selector 21 receives the first clock signal from the client signal detection unit 12 and the second clock signal from the oscillator 22, selects one of the clock signals, and outputs the selected clock signal to the PLL unit 30. This selection can be made based on the output from the logical sum 23.
　論理和２３は、例えば論理和回路とすることができる。論理和２３の一方の入力はＡＬＭ検出部１１から出力された検出信号とし、他方の入力は光入力断検出部２４から出力された検出信号とすることができる。そのため、ＡＬＭ検出部１１は、障害を検出した場合に検出信号を制御部２０の論理和２３に出力する。 The logical sum 23 can be a logical sum circuit, for example. One input of the logical sum 23 can be a detection signal output from the ALM detection unit 11, and the other input can be a detection signal output from the light input break detection unit 24. For this reason, the ALM detection unit 11 outputs a detection signal to the logical sum 23 of the control unit 20 when a failure is detected.
　光入力断検出部２４は、入力された光信号の光強度を検出する光強度検出部の一例であり、光分岐部４０で分岐された光信号（モニタ光信号）を入力し、当該光信号の信号強度を検出する。そして、光入力断検出部２４は、検出した信号強度が所定値（所定の閾値）以下であるとき、信号断と判断しセレクタ２１の切り替えを行うような検出信号を論理和２３に出力する。このように、光入力断検出部２４は、光分岐部４０からの光入力レベルが一定値以下になると光入力断のアラームを論理和２３に発出する。 The light input break detection unit 24 is an example of a light intensity detection unit that detects the light intensity of the input optical signal. The light input break detection unit 24 receives the optical signal (monitor optical signal) branched by the optical branching unit 40 and inputs the optical signal. The signal strength of is detected. Then, when the detected signal intensity is equal to or less than a predetermined value (predetermined threshold value), the light input disconnection detection unit 24 outputs a detection signal that determines that the signal is interrupted and switches the selector 21 to the logical sum 23. In this way, the light input break detection unit 24 issues a light input break alarm to the logical sum 23 when the light input level from the light branching unit 40 falls below a certain value.
　論理和２３は、ＡＬＭ検出部１１からの検出信号及び光入力断検出部２４からの検出信号のいずれか一方を受けた場合、クロック信号を第２クロック信号に切り替えるような信号をセレクタ２１に出力する。これにより、セレクタ２１は、ＡＬＭ検出部１１から障害が発生したことが検出されたか、或いは光入力断検出部２４で光入力断が検出された場合に、ＰＬＬ部３０に出力するクロック信号を発振器２２で生成された第２クロック信号に切り替える。 The logical sum 23 outputs to the selector 21 a signal for switching the clock signal to the second clock signal when receiving either the detection signal from the ALM detection unit 11 or the detection signal from the light input break detection unit 24. To do. As a result, the selector 21 detects the occurrence of a failure from the ALM detection unit 11 or the clock signal output to the PLL unit 30 when the light input break detection unit 24 detects the light input break. Switch to the second clock signal generated at 22.
　このように、本実施形態における制御部２０は、光強度が所定値以上である場合に第１クロック信号をＰＬＬ部３０に入力し、上記所定値未満である場合に第２クロック信号をＰＬＬ部３０に入力するように、切り替えを行う。 As described above, the control unit 20 according to the present embodiment inputs the first clock signal to the PLL unit 30 when the light intensity is equal to or greater than the predetermined value, and outputs the second clock signal to the PLL unit when the light intensity is less than the predetermined value. Switching is performed so as to input to 30.
　次に、上述のような構成の光信号受信装置２における動作例について説明する。
　まず、ライン信号に障害（信号断等）がない場合は、次のような動作になる。ライン信号は、クライアント信号処理部１０、ＡＬＭ検出部１１、クライアント信号検出部１２、及びデマッパ部１３を経て、クライアント信号として出力される。ＡＬＭ検出部１１は、ライン信号の障害の有無を検出し、クライアント信号検出部１２は、ライン信号のフレームに含まれるＪＣバイトを基に第１クロック信号を生成する。クライアント信号検出部１２で生成された第１クロック信号は、制御部２０に供給される。制御部２０は、このクロック信号を、ＰＬＬ部３０に供給し、ＰＬＬ部３０は、デマッパ部１３が、正しくクライアント信号を復号できるように位相制御を行い、デマッパ部１３に供給する。デマッパ部１３は、ＰＬＬ部３０からのクロック信号を用いて、クライアント信号を復号する。 Next, an operation example in the optical signal receiving apparatus 2 configured as described above will be described.
First, when there is no failure (signal interruption, etc.) in the line signal, the following operation is performed. The line signal is output as a client signal through the client signal processing unit 10, the ALM detection unit 11, the client signal detection unit 12, and the demapper unit 13. The ALM detection unit 11 detects the presence or absence of a fault in the line signal, and the client signal detection unit 12 generates a first clock signal based on the JC byte included in the line signal frame. The first clock signal generated by the client signal detection unit 12 is supplied to the control unit 20. The control unit 20 supplies this clock signal to the PLL unit 30, and the PLL unit 30 performs phase control so that the demapper unit 13 can correctly decode the client signal, and supplies it to the demapper unit 13. The demapper unit 13 decodes the client signal using the clock signal from the PLL unit 30.
　一方で、もし、ライン信号に信号断等の障害が発生すると、ライン信号のＪＣバイトが正常な値でなくなり、クライアント信号検出部１２は、正常でないクロック信号を出力する。この正常でないクロック信号に基づいて位相制御を行うので、安定するまでに非常に時間がかかるという問題がある。 On the other hand, if a failure such as a signal interruption occurs in the line signal, the JC byte of the line signal is not a normal value, and the client signal detection unit 12 outputs an abnormal clock signal. Since phase control is performed based on this abnormal clock signal, there is a problem that it takes a very long time to stabilize.
　この問題について、図３を参照しながら、比較例に係る光信号受信装置について説明する。図３に示す比較例に係る光信号受信装置３は、クライアント信号処理部６０、制御部７０、及びＰＬＬ部８０を有する。クライアント信号処理部６０は、ＡＬＭ検出部６１、クライアント信号検出部６２、及びデマッパ部６３を有する。 Regarding this problem, an optical signal receiving apparatus according to a comparative example will be described with reference to FIG. The optical signal receiving device 3 according to the comparative example illustrated in FIG. 3 includes a client signal processing unit 60, a control unit 70, and a PLL unit 80. The client signal processing unit 60 includes an ALM detection unit 61, a client signal detection unit 62, and a demapper unit 63.
　ライン信号は、クライアント信号処理部６０の、ＡＬＭ検出部６１、クライアント信号検出部６２、及びデマッパ部６３を経て、クライアント信号として出力される。ＡＬＭ検出部６１は、ライン信号の障害の有無を検出する。クライアント信号検出部６２は、ライン信号のフレームに含まれるＪＣバイトを基にクロック信号を生成する。 The line signal is output as a client signal through the ALM detection unit 61, the client signal detection unit 62, and the demapper unit 63 of the client signal processing unit 60. The ALM detection unit 61 detects the presence or absence of a line signal failure. The client signal detection unit 62 generates a clock signal based on the JC byte included in the frame of the line signal.
　クライアント信号検出部６２で生成されたクロック信号は、クライアント信号処理部６０を制御する制御部７０に供給される。制御部７０は、このクロック信号を、ＰＬＬ部８０に供給し、ＰＬＬ部８０は、デマッパ部６３が正しくクライアント信号を復号できるように位相制御及び逓倍処理を行い、デマッパ部６３に供給する。デマッパ部６３は、ＰＬＬ部８０から供給されたクロック信号を用いて、クライアント信号を復号する。 The clock signal generated by the client signal detection unit 62 is supplied to the control unit 70 that controls the client signal processing unit 60. The control unit 70 supplies this clock signal to the PLL unit 80, and the PLL unit 80 performs phase control and multiplication processing so that the demapper unit 63 can correctly decode the client signal, and supplies the demapper unit 63. The demapper unit 63 decodes the client signal using the clock signal supplied from the PLL unit 80.
　この時、ライン信号に信号断などの障害が発生すると、ライン信号のＪＣバイトが正常な値でなくなり、クライアント信号検出部６２は、正常でないクロック信号を出力することになる。 At this time, if a failure such as a signal interruption occurs in the line signal, the JC byte of the line signal is not a normal value, and the client signal detection unit 62 outputs an abnormal clock signal.
　ＰＬＬ部８０は、入力されるクロック信号が想定周波数範囲から外れるなどの異常を検知すると、ＰＬＬ部８０の内部メモリに記憶された直前の位相情報に基づいて動作し、位相制御を固定する。しかしながら、上述のような正常でないクロック信号が断続的に入力されると、その正常でないクロック信号に基づいて位相制御を行ってしまい、ライン信号の復旧時に安定するまでに非常に時間がかかる。 When the PLL unit 80 detects an abnormality such that the input clock signal is out of the assumed frequency range, the PLL unit 80 operates based on the immediately preceding phase information stored in the internal memory of the PLL unit 80 and fixes the phase control. However, if an abnormal clock signal as described above is intermittently input, phase control is performed based on the abnormal clock signal, and it takes a very long time to stabilize when the line signal is restored.
　一般に、ライン側の信号（ライン側信号）に、信号断等の障害が発生すると、ライン側の障害発生をクライアントに通知するので、これらの情報を転送するために、ライン信号正常時と同様なクロック供給が求められる。この通知は、例えば、クライアント信号がＯＴＵ［Optical Channel Transport Unit］４の場合）、ＡＩＳ（Alarm Indication Signal）の警報転送が該当する。また、クライアント信号がＥｔｈｅｒｎｅｔの場合には、ＬＦ（Local Fault）信号やＩＤＬＥ信号が挿入されることにより、上記通知がなされる。 In general, when a failure such as a signal interruption occurs in a signal on the line side (line side signal), the client is notified of the occurrence of the failure on the line side. Therefore, in order to transfer these information, the same as when the line signal is normal A clock supply is required. This notification corresponds to, for example, a case where the client signal is OTU [Optical Channel Transport Unit] 4) and alarm transmission of AIS (Alarm Indication Signal). When the client signal is Ethernet, the above notification is made by inserting an LF (Local Fault) signal or an IDLE signal.
　比較例での問題を回避するため、本実施形態に係る光信号受信装置２は、上述したように、ライン信号に信号断などの障害が発生したか否かをＡＬＭ検出部１１からの検出信号及び光入力断検出部２４からの検出信号で認識する。そして、光信号受信装置２は、いずれかの検出信号を認識した場合にセレクタ２１を切り替えて、発振器２２から第２クロック信号を供給するようにし、ＰＬＬ部３０へのクロック信号を安定化させる。 In order to avoid the problem in the comparative example, as described above, the optical signal receiving device 2 according to the present embodiment detects whether or not a failure such as a signal interruption has occurred in the line signal. And it recognizes with the detection signal from the light input interruption detection part 24. When the optical signal receiving apparatus 2 recognizes any detection signal, the optical signal receiving apparatus 2 switches the selector 21 to supply the second clock signal from the oscillator 22, and stabilizes the clock signal to the PLL unit 30.
　さらに、本実施形態に係る光信号受信装置２では、光入力断検出部２４及びＡＬＭ検出部１１のそれぞれで障害の有無を判断することができるため、次のように、より短い時間で切り替えができる。即ち、例えば、信号が消失した場合又は閾値以下の強度となった場合には、光入力断検出部２４にて光強度に基づき判断を行ってセレクタ２１を切り替えるため、より短い時間でセレクタ２１の切り替えを実行できる。 Furthermore, in the optical signal receiving device 2 according to the present embodiment, the optical input break detection unit 24 and the ALM detection unit 11 can determine the presence or absence of a failure, so that switching can be performed in a shorter time as follows. it can. That is, for example, when the signal disappears or the intensity becomes equal to or lower than the threshold value, the light input break detection unit 24 makes a determination based on the light intensity and switches the selector 21. Switching can be performed.
　これにより、光信号受信装置２によれば、比較例での問題を解決するだけでなく、電気信号の内容を解析した結果に基づき切り替えを行う場合と比較して、ＰＬＬ部３０に異常なクロック信号（ＪＣバイト）が入力される時間をより短くすることが可能となる。よって、光信号受信装置２によれば、ライン信号のデータ断などの障害から復旧した際に、ＰＬＬ部３０の動作を速やかに安定化させること、つまりデマッパ部１３へのクロック信号の供給を安定化させることができる。 As a result, according to the optical signal receiving device 2, not only the problem in the comparative example is solved, but also an abnormal clock is generated in the PLL unit 30 as compared with the case of switching based on the result of analyzing the contents of the electric signal. It is possible to shorten the time during which the signal (JC byte) is input. Therefore, according to the optical signal receiving device 2, the operation of the PLL unit 30 is quickly stabilized when recovered from a failure such as data loss of the line signal, that is, the supply of the clock signal to the demapper unit 13 is stabilized. It can be made.
　また、上述のように本実施形態では、第１クロックを光分岐部４０から入力された非モニタ光信号から抽出し、制御部２０が、モニタ光信号の光強度に基づいて、ＰＬＬ部３０へ入力するクロック信号を第１クロック信号と第２クロック信号との間で切り替える。これにより、クライアント信号の復号とは別の経路でクロック信号の選択を行うことができる。 Further, as described above, in the present embodiment, the first clock is extracted from the non-monitor optical signal input from the optical branching unit 40, and the control unit 20 transmits the first clock to the PLL unit 30 based on the light intensity of the monitor optical signal. The input clock signal is switched between the first clock signal and the second clock signal. As a result, the clock signal can be selected through a path different from the decoding of the client signal.
　また、光信号受信装置２は、論理和２３及びＡＬＭ検出部１１を設けず、光入力断検出部２４からの出力を直接セレクタ２１に入力するように構成することもできる。 Also, the optical signal receiving device 2 can be configured to directly input the output from the optical input break detection unit 24 to the selector 21 without providing the logical sum 23 and the ALM detection unit 11.
　但し、制御部２０は、光強度及びＡＬＭ検出部１１による障害検出結果の双方に基づいて、ＰＬＬ部３０へ入力するクロック信号を第１クロック信号と第２クロック信号との間で切り替えることで、次のような場合に対応することができる。即ち、このような構成により、光信号が消失しておらず光強度が閾値以上ではあるが信号にエラーが生じている場合に、ＡＬＭ検出部１１からの検出信号からセレクタ２１の切り替えを実行することができる。 However, the control unit 20 switches the clock signal input to the PLL unit 30 between the first clock signal and the second clock signal based on both the light intensity and the failure detection result by the ALM detection unit 11. The following cases can be dealt with. That is, with such a configuration, when the optical signal is not lost and the light intensity is equal to or higher than the threshold value, but the signal has an error, the selector 21 is switched from the detection signal from the ALM detection unit 11. be able to.
＜他の実施形態＞
［ａ］
　実施形態１では、図１に示す光信号受信装置１の各部１ａ～１ｄの機能について説明したが、光信号受信装置１としてこれらの機能が実現できればよい。同様に、実施形態２では、図２に示す光信号受信装置２内の各構成要素の機能について説明したが、光信号受信装置２としてこれらの機能が実現できればよい。 <Other embodiments>
[A]
In the first embodiment, the functions of the respective units 1a to 1d of the optical signal receiving apparatus 1 shown in FIG. 1 have been described. Similarly, in Embodiment 2, the function of each component in the optical signal receiving apparatus 2 illustrated in FIG. 2 has been described, but it is sufficient that these functions can be realized as the optical signal receiving apparatus 2.
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　実施形態１，２に係る光信号受信装置１，２は、次のようなハードウェア構成を有していてもよい。図４は、実施形態１，２に係る光信号受信装置１，２の一部のハードウェア構成例を示す図である。なお、上記他の実施形態［ａ］についても同様である。 [B]
The optical signal receiving apparatuses 1 and 2 according to the first and second embodiments may have the following hardware configuration. FIG. 4 is a diagram illustrating a hardware configuration example of a part of the optical signal receiving apparatuses 1 and 2 according to the first and second embodiments. The same applies to the other embodiment [a].
　図４に示す光信号受信装置１００は、プロセッサ１０１及びメモリ１０２を有する。その他、光信号受信装置１００は、図示しないが、クロック信号を発生するクロック発生部と、入力された光信号の光強度を検出する光強度検出部と、を備える。実施形態１で説明した光信号受信装置１における制御部１ｄ及びクロック抽出部１ａの機能の一部は、プロセッサ１０１がメモリ１０２に記憶された制御プログラムを読み込んで実行することにより実現される。実施形態２で説明した光信号受信装置２における制御部２０及びクライアント信号処理部１０の機能の一部は、プロセッサ１０１がメモリ１０２に記憶された制御プログラムを読み込んで実行することにより実現される。 4 includes a processor 101 and a memory 102. The optical signal receiving apparatus 100 illustrated in FIG. In addition, although not shown, the optical signal receiving apparatus 100 includes a clock generation unit that generates a clock signal and a light intensity detection unit that detects the light intensity of the input optical signal. Part of the functions of the control unit 1d and the clock extraction unit 1a in the optical signal receiving apparatus 1 described in the first embodiment is realized by the processor 101 reading and executing a control program stored in the memory 102. Part of the functions of the control unit 20 and the client signal processing unit 10 in the optical signal receiving device 2 described in the second embodiment is realized by the processor 101 reading and executing a control program stored in the memory 102.
　上述の例において、制御プログラムは、様々なタイプの非一時的なコンピュータ可読媒体（non-transitory computer readable medium）を用いて格納され、コンピュータに供給することができる。非一時的なコンピュータ可読媒体は、様々なタイプの実体のある記録媒体（tangible storage medium）を含む。非一時的なコンピュータ可読媒体の例は、磁気記録媒体（例えばフレキシブルディスク、磁気テープ、ハードディスクドライブ）、光磁気記録媒体（例えば光磁気ディスク）を含む。さらに、この例は、ＣＤ－ＲＯＭ（Read Only Memory）、ＣＤ－Ｒ、ＣＤ－Ｒ／Ｗを含む。さらに、この例は、半導体メモリ（例えば、マスクＲＯＭ、ＰＲＯＭ（Programmable ROM）、ＥＰＲＯＭ（Erasable PROM）、フラッシュＲＯＭ、ＲＡＭ（Random Access Memory））を含む。また、プログラムは、様々なタイプの一時的なコンピュータ可読媒体（transitory computer readable medium）によってコンピュータに供給されてもよい。一時的なコンピュータ可読媒体の例は、電気信号、光信号、及び電磁波を含む。一時的なコンピュータ可読媒体は、電線及び光ファイバ等の有線通信路、又は無線通信路を介して、プログラムをコンピュータに供給できる。 In the above example, the control program can be stored using various types of non-transitory computer-readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media (tangible storage medium). Examples of non-transitory computer readable media include magnetic recording media (eg, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (eg, magneto-optical disks). Further, this example includes a CD-ROM (Read Only Memory), a CD-R, and a CD-R / W. Further, this example includes a semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable ROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of temporary computer-readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.
［ｃ］
　さらに、上述した様々な実施形態において、光信号受信装置における光信号受信方法の手順を例示したように、本開示は、光信号受信方法としての形態も採り得る。この光信号受信方法は、入力された光信号から第１クロック信号を抽出するステップと、第２クロック信号を発生するステップと、クロック信号を入力し、位相同期後のクロック信号を出力する位相同期ステップと、を有する。さらに、この光信号受信方法は、上記光信号の光強度に基づいて、上記位相同期ステップにおいて入力するクロック信号を第１クロック信号と第２クロック信号との間で切り替えるステップを有する。なお、その他の例については、上述した様々な実施形態で説明した通りである。また、上記制御プログラムは、光信号受信装置に上述した各ステップを実行させるためのプログラムであると言える。 [C]
Furthermore, in the various embodiments described above, as illustrated in the procedure of the optical signal receiving method in the optical signal receiving apparatus, the present disclosure can also take a form as an optical signal receiving method. The optical signal receiving method includes a step of extracting a first clock signal from an input optical signal, a step of generating a second clock signal, a phase synchronization that inputs a clock signal and outputs a clock signal after phase synchronization. Steps. Further, the optical signal receiving method includes a step of switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal. Other examples are as described in the various embodiments described above. Further, it can be said that the control program is a program for causing the optical signal receiving apparatus to execute each step described above.
　なお、本開示は上記実施形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。また、本開示は、それぞれの実施形態を適宜組み合わせて実施されてもよい。 Note that the present disclosure is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present disclosure. In addition, the present disclosure may be implemented by appropriately combining the embodiments.
　以上、実施の形態を参照して本願発明を説明したが、本願発明は上記によって限定されるものではない。本願発明の構成や詳細には、発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 The present invention has been described above with reference to the embodiment, but the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.
　この出願は、２０１８年２月２７日に出願された日本出願特願２０１８－０３２６６１を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2018-032661 filed on February 27, 2018, the entire disclosure of which is incorporated herein.
１、２、１００　光信号受信装置
１ａ　クロック抽出部
１ｂ　クロック発生部
１ｃ、３０　位相同期部（ＰＬＬ部）
１ｄ、２０　制御部
１０　クライアント信号処理部
１１　ＡＬＭ検出部
１２　クライアント信号検出部
１３　デマッパ部
２１　セレクタ
２２　発振器
２３　論理和
２４　光入力断検出部
４０　光分岐部
１０１　プロセッサ
１０２　メモリ 1, 2, 100 Optical signal receiver 1a Clock extraction unit 1b Clock generation unit 1c, 30 Phase synchronization unit (PLL unit)
1d, 20 Control unit 10 Client signal processing unit 11 ALM detection unit 12 Client signal detection unit 13 Demapper unit 21 Selector 22 Oscillator 23 Logical sum 24 Optical input break detection unit 40 Optical branching unit 101 Processor 102 Memory

Claims (7)

  1. 　入力された光信号から第１クロック信号を抽出するクロック抽出手段と、
    　第２クロック信号を発生するクロック発生手段と、
    　クロック信号を入力し、位相同期後のクロック信号を出力する位相同期手段と、
    　前記光信号の光強度に基づいて、前記位相同期手段へ入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替える制御手段と、
    　を備えた、光信号受信装置。     Clock extraction means for extracting the first clock signal from the input optical signal;
    Clock generating means for generating a second clock signal;
    Phase synchronization means for inputting a clock signal and outputting a clock signal after phase synchronization;
    Control means for switching a clock signal input to the phase synchronization means between the first clock signal and the second clock signal based on the light intensity of the optical signal;
    An optical signal receiving device.
  2. 　前記制御手段は、前記光強度が所定値以上である場合に前記第１クロック信号を前記位相同期手段に入力し、前記所定値未満である場合に前記第２クロック信号を前記位相同期手段に入力するように切り替える、
    　請求項１に記載の光信号受信装置。     The control means inputs the first clock signal to the phase synchronization means when the light intensity is greater than or equal to a predetermined value, and inputs the second clock signal to the phase synchronization means when it is less than the predetermined value. Switch to
    The optical signal receiving apparatus according to claim 1.
  3. 　前記光信号を電気信号に変換し、前記電気信号から前記光信号の障害を検出する障害検出手段をさらに備え、
    　前記制御手段は、前記光強度及び前記障害検出手段による障害検出結果に基づいて、前記位相同期手段へ入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替える、
    　請求項１又は２に記載の光信号受信装置。     It further comprises failure detection means for converting the optical signal into an electrical signal and detecting a failure of the optical signal from the electrical signal,
    The control means switches a clock signal to be input to the phase synchronization means between the first clock signal and the second clock signal based on the light intensity and a failure detection result by the failure detection means.
    The optical signal receiving device according to claim 1.
  4. 　入力光信号からモニタ光信号を分岐する光分岐手段を備え、
    　前記クロック抽出手段は、前記光分岐手段から入力された光信号から前記第１クロック信号を抽出し、
    　前記制御手段は、前記モニタ光信号の光強度に基づいて、前記位相同期手段へ入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替える、
    　請求項１から３のいずれか１項に記載の光信号受信装置。     Comprising optical branching means for branching the monitor optical signal from the input optical signal;
    The clock extraction means extracts the first clock signal from the optical signal input from the optical branching means,
    The control means switches the clock signal input to the phase synchronization means between the first clock signal and the second clock signal based on the light intensity of the monitor light signal.
    The optical signal receiving device according to claim 1.
  5. 　前記光信号は、クライアント信号が収容されたライン信号であり、
    　前記位相同期手段から出力される位相同期後のクロック信号は、前記クライアント信号の復号に使用される、
    　請求項１から４のいずれか１項に記載の光信号受信装置。     The optical signal is a line signal in which a client signal is accommodated,
    The phase-synchronized clock signal output from the phase synchronization means is used for decoding the client signal.
    The optical signal receiving device according to claim 1.
  6. 　入力された光信号から第１クロック信号を抽出するステップと、
    　第２クロック信号を発生するステップと、
    　クロック信号を入力し、位相同期後のクロック信号を出力する位相同期ステップと、
    　前記光信号の光強度に基づいて、前記位相同期ステップにおいて入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替えるステップと、
    　を有する、光信号受信方法。     Extracting a first clock signal from the input optical signal;
    Generating a second clock signal;
    A phase synchronization step for inputting a clock signal and outputting a clock signal after phase synchronization;
    Switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal;
    An optical signal receiving method.
  7. 　クロック信号を発生するクロック発生手段と、入力された光信号の光強度を検出する光強度検出手段と、を備えた光信号受信装置に、
    　入力された光信号から第１クロック信号を抽出するステップと、
    　前記クロック発生手段により第２クロック信号を発生するステップと、
    　クロック信号を入力し、位相同期後のクロック信号を出力する位相同期ステップと、
    　前記光信号の光強度に基づいて、前記位相同期ステップにおいて入力するクロック信号を前記第１クロック信号と前記第２クロック信号との間で切り替えるステップと、
    　を実行させるための制御プログラムが格納された非一時的なコンピュータ可読媒体。     An optical signal receiving device comprising a clock generating means for generating a clock signal and a light intensity detecting means for detecting the light intensity of the inputted optical signal,
    Extracting a first clock signal from the input optical signal;
    Generating a second clock signal by the clock generating means;
    A phase synchronization step for inputting a clock signal and outputting a clock signal after phase synchronization;
    Switching the clock signal input in the phase synchronization step between the first clock signal and the second clock signal based on the light intensity of the optical signal;
    A non-transitory computer-readable medium storing a control program for executing the program.
PCT/JP2018/043364 2018-02-27 2018-11-26 Optical signal reception device, optical signal reception method, and non-transitory computer-readable medium WO2019167361A1 (en)

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JPH1155700A (en) * 1997-08-05 1999-02-26 Nec Corp Wavelength light adm device, optical signal fault monitor system using the device and ring network
WO2006085356A1 (en) * 2005-02-08 2006-08-17 Fujitsu Limited Light input break detection device
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JP2010206625A (en) * 2009-03-04 2010-09-16 Fujitsu Ltd Optical transmission apparatus and optical transmission method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05344104A (en) * 1992-06-09 1993-12-24 Nippon Telegr & Teleph Corp <Ntt> Transmission path switching device
JPH1155700A (en) * 1997-08-05 1999-02-26 Nec Corp Wavelength light adm device, optical signal fault monitor system using the device and ring network
US7542483B1 (en) * 2003-06-25 2009-06-02 Cisco Technology, Inc. Recoverable reference clock architecture for SONET/SDH and ethernet mixed bidirectional applications
WO2006085356A1 (en) * 2005-02-08 2006-08-17 Fujitsu Limited Light input break detection device
JP2009290256A (en) * 2008-05-27 2009-12-10 Fujitsu Ltd Optical transmission apparatus
JP2010206625A (en) * 2009-03-04 2010-09-16 Fujitsu Ltd Optical transmission apparatus and optical transmission method

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