WO2016101792A1

WO2016101792A1 - Clock device and method for maintaining clock

Info

Publication number: WO2016101792A1
Application number: PCT/CN2015/097014
Authority: WO
Inventors: 赵亮
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-12-26
Filing date: 2015-12-10
Publication date: 2016-06-30
Also published as: CN105790873B; CN105790873A

Abstract

Disclosed in the present invention are a clock device and method for maintaining clock, the clock device comprising: a clock interface module and a clock processing module, the clock interface module being configured to monitor a received clock link signal, when the clock link signal is detected to be abnormal, turning off a clock output of the clock interface module; the clock processing module is configured to enter a clock maintaining state and output a system clock when the clock output of the clock interface module is detected to be a turned-off state.

Description

Clock device and method for keeping clock

Technical field

This application relates to, but is not limited to, the field of communication technology.

Background technique

At present, in the synchronous digital system clock transmission, Ethernet-based clock transmission technology has been more and more widely used, and its output clock performance can basically meet the ITU-T for ITU Telecommunication Standardization Sector. The specified clock characteristics. However, due to the variety of application scenarios, the application methods are also various, and the clock performance needs to be improved in some application scenarios. For example, when an upstream clock device transmits a clock to a downstream clock device through Ethernet, if the link is suddenly broken or the clock suddenly disappears, the ITU-T standard requires the downstream clock device to enter the hold mode, that is, the clock hold state, and maintain the accuracy. Meet the performance requirements specified by the standard.

Summary of the invention

The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims.

A common method of the related art is that after detecting that the clock in the link is out of lock, the downstream clock interface device sends the unavailable clock quality level information DNU to the downstream clock processing device. After receiving the DNU information, the downstream clock processing device needs to The DNU information is parsed, and the analysis mode is completed before entering the hold mode. In this way, when the downstream clock interface device detects that the clock in the link is out of lock until the downstream clock processing device enters the hold mode, the DNU information needs to be forwarded and parsed, and the locking source of the downstream clock processing device is The original link clock becomes a local crystal oscillator, causing the output clock to jump and the system clock to jump. It has been found that the time that the downstream clock interface device detects that the clock in the link is out of lock, after the DNU information is forwarded and parsed until the downstream clock processing device enters the hold mode takes ms (milliseconds). The system clock generates a frequency jump of ppm level and cannot meet the ITU-T standard. The required downstream clock device should have the retention performance.

The present invention provides a clock device and method for maintaining a clock to solve the technical problem that the system clock hopping in the related art clock device takes too long.

A clock device for holding a clock, the clock device includes: a clock interface module and a clock processing module, wherein

The clock interface module is configured to: monitor a received clock link signal, and when it is determined that the clock link signal is abnormal, turn off a clock output of the clock interface module;

The clock processing module is configured to: when detecting that the clock output of the clock interface module is in a closed state, enter a clock hold state and output a system clock.

Optionally, the clock interface module includes: a detecting unit and a clock driving unit, where

The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit;

The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.

Optionally, the clock interface module includes a detecting unit, a filtering unit, and a clock driving unit, where:

The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and notify the filtering unit when determining that the state of the clock link signal is abnormal;

The filtering unit is configured to perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, sending a switch control signal to the clock driving unit;

Optionally, the clock processing module is configured to:

When the phase locked loop circuit detects that the clock interface module has no clock output within a preset time When it enters the clock hold state, it outputs the system clock.

Optionally, the clock link signal is an Ethernet signal or a second pulse signal.

A clock holding method of a clock device, the clock device includes: a clock interface module and a clock processing module, and the method includes:

The clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;

The clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.

Optionally, the clock interface module monitors the received clock link signal, and when determining that the clock link signal is abnormal, the step of turning off the clock output of the clock interface module includes:

The clock interface module receives and detects a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, generates a switch control signal, and closes the clock interface module according to the switch control signal. Clock output.

The clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.

Optionally, the clock processing module enters a clock hold state when detecting that the clock output of the clock interface module is in an off state, and the step of outputting the system clock includes:

When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.

A computer readable storage medium storing computer executable instructions, the computer being executable The line instructions are used to perform the method of any of the above.

The clock device and method for maintaining a clock according to the embodiment of the present invention, when the clock interface module in the clock device detects that an abnormality occurs in the clock link signal sent by the upstream clock device, the clock output of the clock interface module is turned off; When the clock processing module in the clock device detects that the clock output of the clock interface module is in the off state, it can know that the clock link signal is abnormal, and immediately enters the clock hold state and outputs the system clock without the clock interface module being When the clock link signal is abnormal, the DNU information is sent to the clock processing module, and the clock processing module parses the DNU information to enter the clock hold state, thereby reducing the cumbersome operation of forwarding and parsing the DNU information, so that the clock device is in the clock device. The clock processing module can quickly enter the clock hold state, which minimizes the time from the clock interface module detecting the clock link signal abnormality to the clock processing module entering the clock hold state, thereby greatly reducing the clock processing module output system clock. Frequency jump and control Within 1ppb, clock device to satisfy the performance retention should have.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF abstract

1 is a schematic diagram of functional modules of a first embodiment of a clock device for holding a clock according to an embodiment of the present invention;

2 is a schematic diagram of a refinement function module of the clock interface module 01 of FIG. 1;

3 is a schematic diagram of a refinement function module of a clock interface module 01 in a second embodiment of a clock device for holding a clock according to the present invention;

4 is a schematic flow chart of an embodiment of a clock holding method of a clock device according to the present invention.

Embodiments of the invention

Embodiments of the present invention provide a clock device that holds a clock.

Referring to FIG. 1, FIG. 1 is a schematic diagram of functional modules of a first embodiment of a clock device for holding a clock according to the present invention.

In the first embodiment, the clock device includes: a clock interface module 01 and a clock processing module 02, where

The clock interface module 01 is configured to: monitor the received clock link signal, and when it is determined that the clock link signal is abnormal, turn off the clock output of the clock interface module 01;

The clock processing module 02 is configured to enter a clock hold state and output a system clock when detecting that the clock output of the clock interface module 01 is in a closed state.

In this embodiment, when the clock interface module 01 in the clock device detects that the clock link signal sent by the upstream clock device is abnormal, the clock output of the clock interface module 01 is turned off; thus, the clock processing module 02 in the clock device detects When the clock output of the clock interface module 01 is in the off state, the clock link signal is abnormal, and the clock hold state is immediately entered, and the system clock is output, without the clock interface module 01 detecting the abnormality of the clock link signal. The DNU information is sent to the clock processing module 02, and the clock processing module 02 can parse the DNU information to enter the clock hold state, thereby reducing the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module 02 in the clock device can Quickly enter the clock hold state, which minimizes the time from when the clock interface module 01 detects the clock link signal abnormality to when the clock processing module 02 enters the clock hold state, thereby greatly reducing the frequency hop of the clock processing module 02 outputting the system clock. Change and control within 1 ppb to meet the clock device It has maintained performance.

As shown in FIG. 2, the clock interface module 01 includes: a detecting unit 03 and a clock driving unit 04, where

The detecting unit 03 is configured to: receive and detect a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit 04;

The clock driving unit 04 is configured to turn off the clock output of the clock interface module 01 according to the switch control signal.

The detecting unit 03 monitors the clock link signal sent by the upstream clock device in real time, and detects the state of the received clock link signal. When the state of the clock link signal is abnormal, the description is If the data link is disconnected or the clock link signal is lost, the clock interface module 01 loses the clock source input from the upstream clock device, and cannot recover the clock in the clock link signal, that is, it automatically locks on the local crystal oscillator, but this The clock interface module 01 does not output the local crystal oscillator locked at this time, that is, the local oscillator clock, but the detection unit 03 sends a switch control signal to the clock drive unit 04; the clock drive unit 04 controls the switch according to the detection unit 03. The signal is used to control the clock output of the clock interface module 01. When the detecting unit 03 detects that the state of the clock link signal is abnormal, the switch control signal is sent to the clock driving unit 04, and the clock driving unit 04 can be turned off according to the switch control signal. The clock output of the clock interface module 01 is such that the output clock of the clock interface module 01 becomes a high impedance state.

The above clock processing module 02 is set to:

When the phase-locked loop circuit detects that the clock interface module 01 has no clock output within a preset time, it enters a clock hold state and outputs a system clock.

When the clock output of the clock interface module 01 is in the off state, that is, the output clock of the clock interface module 01 becomes a high impedance state, the clock processing module 02 can perform detection by using a phase locked loop circuit. The clock processing module 02 uses a phase-locked loop circuit to lock the clock of the normal clock link signal recovery or enters the clock hold state, and the phase-locked loop circuit enters the clock hold state, except that the configuration command can be issued. It can also automatically enter the clock hold state when the phase-locked loop circuit detects the loss of the clock source. This is a basic function that most phase-locked loop chips have, and is used in the clock device of the synchronous digital system. Phase-locked loop circuits must have this capability. Therefore, the clock processing module 02 of the clock device in this embodiment can use the phase-locked loop circuit to detect the clock output state of the clock interface module 01, and the phase-locked loop circuit in the clock processing module 02 detects the preset time. When the clock interface module 01 has no clock output, it can be known that the clock link signal is abnormal, and the clock source is lost, the clock processing module 02 immediately enters the clock hold state and outputs the system clock. It should be noted that, before using the phase-locked loop circuit to detect the clock output state of the clock interface module 01 within a preset time, the preset time may be set, and the preset time may be set lower according to requirements. For example, 1 to 2 cycles, in this way, when the clock interface module 01 is detected to have no clock output in 1 to 2 cycles by using the phase-locked loop circuit, the clock processing module 02 can immediately enter the clock hold state, thereby reducing the detection cost. Time to make the clock Processing module 02 enters the clock hold state more quickly, thereby reducing the frequency hopping of the output system clock.

In the embodiment, the clock processing module 02 uses the hardware of the phase-locked loop circuit to detect the clock output state of the clock interface module 01 within a preset time, and when detecting that the clock interface module 01 has no clock output, Automatically enters the clock hold state, outputs the system clock, and shortens the time when the clock processing module 02 enters the clock hold state as much as possible, without the clock interface module 01 sending the DNU information to the clock processing module 02 when detecting that the clock link signal is abnormal. After the clock processing module 02 parses the DNU information, it can enter the clock hold state, which reduces the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module 02 in the clock device can quickly enter the clock hold state, maximizing The time from when the clock interface module 01 detects the abnormality of the clock link signal to the time when the clock processing module 02 enters the clock hold state is shortened, thereby greatly reducing the frequency jump of the output system clock of the clock processing module 02, and controlling it within 1 ppb, Meet the retention performance that clock devices should have.

As shown in FIG. 3, a second embodiment of the present invention provides a clock device for holding a clock. Based on the foregoing first embodiment, the clock interface module 01 includes a detecting unit 03, a filtering unit 05, and a clock driving unit 04. ,among them:

The detecting unit 03 is configured to: receive and detect a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, notify the filtering unit 05;

The filtering unit 05 is configured to: perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit 03, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, send a switch control signal to the clock drive unit 04;

In this embodiment, when the detecting unit 03 detects that the state of the clock link signal is abnormal, the filtering unit 05 first performs noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit 03, and continues to perform the noise filtering process. The clock link signal processed by the noise filtering is detected, if Still detecting the abnormal state of the clock link signal, the switch control signal is sent to the clock drive unit 04, so that the clock drive unit 04 turns off the clock output of the clock interface module 01 according to the switch control signal. Thus, in this embodiment, only when the detection unit 03 and the filtering unit 05 detect that the state of the clock link signal is abnormal, the switch control signal is sent to the clock driving unit 04, effectively avoiding the upstream The short-term instability or environmental interference of the clock transmission link of the clock device may cause the detection unit 03 to misjudge the situation, and the state of the clock link signal sent by the upstream clock device may be more accurately determined, thereby confirming the clock link. When the signal is an abnormal state such as a signal loss, the clock driving unit 04 turns off the clock output of the clock interface module 01, which reduces the possibility that the clock processing module 02 enters the clock holding state due to misjudgment, and enhances the clock device. stability.

The clock link signal sent by the upstream clock device may be an Ethernet signal or a second pulse (1PPS) signal.

The interface type of the Ethernet-based clock transmission is Ethernet optical port and Ethernet electrical port. When the clock interface module 01 receives the synchronous Ethernet signal transmitted by the upstream clock device through the optical fiber, the optical module itself can generate signal loss. The LOS indicator signal, and the noise filtering process is performed inside the optical module, that is, the optical module itself performs noise filtering, loss detection, and the like on the signal loss. Therefore, in the actual application, if the detecting unit 03 of the clock interface module 01 acquires the synchronization ether When the LOS indication signal in the network signal is directly informed that the state of the clock link signal is abnormal, and no further noise filtering processing is required, and the switch control signal is sent to the clock drive according to the LOS indication signal in the synchronous Ethernet signal. The unit 04 is configured to cause the clock driving unit 04 to turn off the clock output of the clock interface module 01 according to the switch control signal.

When the clock interface module 01 receives the synchronous Ethernet signal transmitted by the upstream clock device through the network cable, the synchronous Ethernet physical layer chip will generate a signal loss interrupt, and the interrupt will also generate noise inside the synchronous Ethernet physical layer chip. Filtering processing, therefore, in the actual application, if the detecting unit 03 of the clock interface module 01 acquires the signal loss interrupt in the synchronous Ethernet signal, the state of the clock link signal is directly known to be abnormal, and no further noise filtering processing is required. And transmitting a switch control signal to the clock driving unit 04 according to a signal loss in the synchronous Ethernet signal, so that the clock driving unit 04 turns off the clock according to the switch control signal Clock output of interface module 01.

When the clock interface module 01 receives the second pulse (1PPS) signal transmitted by the upstream clock device through the 1PPS interface, the detecting unit 03 of the clock interface module 01 detects the state of the received 1PPS signal in real time, and detects that the state of the 1PPS signal is abnormal. The 1PPS signal is sent to the filtering unit 05, and the filtering unit 05 performs noise filtering processing on the 1PPS signal, and continues to detect the 1PPS signal after the noise filtering process. If the state of the 1PPS signal is still abnormal, the signal is sent. The control signal is switched to the clock driving unit 04 to cause the clock driving unit 04 to turn off the clock output of the clock interface module 01 according to the switching control signal. Further, when the phase locked loop circuit in the clock processing module 02 detects that the clock interface module 01 has no clock output within a preset time, it can immediately enter the clock hold state and output the system clock.

Embodiments of the present invention provide a clock holding method of a clock device. The clock device includes: a clock interface module and a clock processing module.

Referring to FIG. 4, FIG. 4 is a schematic flowchart diagram of an embodiment of a clock holding method of a clock device according to the present invention.

In an embodiment, the clock keeping method of the clock device includes:

Step S10, the clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;

Step S20, the clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.

In this embodiment, when the clock interface module in the clock device detects that the clock link signal sent by the upstream clock device is abnormal, the clock output of the clock interface module is turned off; thus, the clock processing module in the clock device detects the When the clock output of the clock interface module is off, you can know that the clock link signal is abnormal, and immediately enter the clock hold state and output the system clock. When the clock interface module detects that the clock link signal is abnormal, the clock processing module is sent to the clock processing module. After the DNU information is sent, the clock processing module parses the DNU information to enter the clock hold state, which reduces the cumbersome operation of forwarding and parsing the DNU information, so that the clock processing module in the clock device can quickly enter the clock hold state, and the maximum Limiting the slave clock interface module The time when the clock link signal is abnormal until the clock processing module enters the clock hold state is detected, thereby greatly reducing the frequency jump of the clock processing module output system clock, and controlling it within 1 ppb to meet the retention performance that the clock device should have.

In other embodiments, the step S10 may include: the clock interface module receives and detects a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, generates a switch control signal, and according to The switch control signal turns off the clock output of the clock interface module.

The clock interface module monitors the clock link signal sent by the upstream clock device in real time, and detects the state of the received clock link signal. When the state of the clock link signal is abnormal, the data link is disconnected or If the clock link signal is lost, the clock interface module loses the clock source input from the upstream clock device and cannot recover the clock in the clock link signal, that is, it is automatically locked on the local crystal oscillator. However, the clock interface module does not output. The local crystal oscillator locked at this time is the local oscillator clock, but generates a switch control signal, and controls the clock output of the clock interface module according to the generated switch control signal. When the state of the clock link signal is abnormal, The clock output of the clock interface module is turned off according to the generated switch control signal, so that the output clock of the clock interface module becomes a high impedance state.

In other embodiments, the foregoing step S20 may include:

When the clock output of the clock interface module is in the off state, that is, the output clock of the clock interface module becomes a high impedance state, the clock processing module may use a phase locked loop circuit for detecting. Because the clock processing module uses a phase-locked loop circuit to lock the clock of the normal clock link signal recovery or enters the clock hold state, and the phase-locked loop circuit enters the clock hold state, in addition to the way of issuing the configuration command, When the phase-locked loop circuit detects that the clock source is lost, it automatically enters the clock hold state, which is a basic function of most phase-locked loop chips, and the lock used in the clock device of the synchronous digital system. Phase loop circuits must have this capability. Therefore, The clock processing module of the clock device in this embodiment may use a phase locked loop circuit to detect a clock output state of the clock interface module, and the phase locked loop circuit in the clock processing module detects the clock interface module within a preset time. When there is no clock output, the clock link signal is abnormal. If the clock source is lost, the clock processing module immediately enters the clock hold state and outputs the system clock. It should be noted that, before using the phase-locked loop circuit to detect the clock output state of the clock interface module within a preset time, the preset time may be set, and the preset time may be set to be lower as needed. 1 to 2 cycles, so that when the clock interface module detects no clock output in 1 to 2 cycles by using the phase-locked loop circuit, the clock processing module can immediately enter the clock hold state, reducing the time taken for the detection, This enables the clock processing module to enter the clock hold state more quickly, thereby reducing the frequency hopping of the output system clock.

In this embodiment, the clock processing module uses the hardware means of the phase-locked loop circuit to detect the clock output state of the clock interface module within a preset time, and automatically enters the clock when detecting that the clock interface module has no clock output. Maintaining the state, outputting the system clock, shortening the time that the clock processing module enters the clock hold state as much as possible, without the clock interface module sending DNU information to the clock processing module when the clock link signal is abnormal, and the clock processing module is again After the DNU information is parsed, it can enter the clock hold state, which reduces the cumbersome operation of DNU information forwarding and parsing, so that the clock processing module in the clock device can quickly enter the clock hold state, and the slave clock interface module detection is minimized. The time until the clock link signal is abnormal until the clock processing module enters the clock hold state, thereby greatly reducing the frequency jump of the clock processing module output system clock, and controlling it within 1 ppb to meet the retention performance that the clock device should have.

The second embodiment of the present invention provides a clock holding method for a clock device. Based on the foregoing first embodiment, the foregoing step S10 includes:

In this embodiment, when the clock interface module detects that the state of the clock link signal is abnormal, Performing noise filtering processing on the clock link signal that is determined to be abnormal, and continuing to detect the clock link signal after the noise filtering process, and if the state of the clock link signal is still abnormal, And switching a control signal to turn off a clock output of the clock interface module according to the switch control signal. In this way, in this embodiment, the switch control signal is generated only when the state of the clock link signal is abnormally detected, which effectively avoids the short-term instability that may exist due to the clock transmission link of the upstream clock device. When the environmental interference causes the misjudgment of the detection, the state of the clock link signal sent by the upstream clock device can be more accurately judged, and then the clock interface signal is turned off when the clock link signal is in an abnormal state such as a signal loss. The clock output reduces the possibility of the clock processing module entering the clock hold state due to misjudgment, and enhances the stability of the clock device.

Ethernet interface-based clock transmission commonly used as Ethernet optical port and Ethernet electrical port. When the clock interface module receives the synchronous Ethernet signal transmitted by the upstream clock device through the optical fiber, the optical module itself can generate signal loss LOS. The signal is indicated, and noise filtering is performed inside the optical module, that is, the optical module itself performs noise filtering and loss detection on the signal loss. Therefore, in practical applications, if the clock interface module acquires the LOS in the synchronous Ethernet signal. The indication signal can directly know that the state of the clock link signal is abnormal, and no further noise filtering processing is needed, and a switch control signal is generated according to the LOS indication signal in the synchronous Ethernet signal to turn off the switch according to the switch control signal. Clock output of the clock interface module.

When the clock interface module receives the synchronous Ethernet signal transmitted by the upstream clock device through the network cable, the synchronous Ethernet physical layer chip generates a signal loss interrupt, and the interrupt is generated by noise filtering inside the synchronous Ethernet physical layer chip. Processing, therefore, in the actual application, if the clock interface module acquires the signal loss interrupt in the synchronous Ethernet signal, it can directly know that the state of the clock link signal is abnormal, and no further noise filtering processing is required, and according to the synchronous Ethernet A signal loss interrupt in the signal generates a switch control signal to turn off the clock output of the clock interface module in accordance with the switch control signal.

When the clock interface module receives the second pulse transmitted by the upstream clock device through the 1PPS interface When the (1PPS) signal is used, the clock interface module detects the state of the received 1PPS signal in real time. When the state of the 1PPS signal is abnormal, the noise filtering process is performed on the 1PPS signal, and the 1PPS signal after the noise filtering process is continued. The detection is performed, and if the state of the 1PPS signal is still abnormal, the switch control signal is generated to turn off the clock output of the clock interface module according to the switch control signal. Furthermore, when the phase locked loop circuit in the clock processing module detects that the clock interface module has no clock output within a preset time, it can immediately enter the clock hold state and output the system clock.

One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium, such as on a corresponding hardware platform (eg, The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.

Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.

The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.

When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Industrial applicability

The clock device and method for maintaining a clock according to the embodiment of the present invention, when the clock interface module in the clock device detects that an abnormality occurs in the clock link signal sent by the upstream clock device, the clock output of the clock interface module is turned off; The clock processing module in the clock device can know the clock link signal when detecting that the clock output of the clock interface module is in the off state. Normally, the clock state is immediately entered and the system clock is output, and the clock interface module does not need to send DNU information to the clock processing module when the clock link signal is abnormal. The clock processing module parses the DNU information before entering the clock. Maintaining the state reduces the cumbersome operation of DNU information forwarding and parsing, so that the clock processing module in the clock device can quickly enter the clock hold state, which minimizes the detection of the clock link signal abnormality from the clock interface module to the clock processing. The time that the module enters the clock hold state greatly reduces the frequency jump of the clock processing module output system clock and controls it within 1 ppb to meet the retention performance of the clock device.

Claims

A clock device for holding a clock, the clock device includes: a clock interface module and a clock processing module, wherein

The clock interface module is configured to: monitor a received clock link signal, and when it is determined that the clock link signal is abnormal, turn off a clock output of the clock interface module;

The clock processing module is configured to: when detecting that the clock output of the clock interface module is in a closed state, enter a clock hold state and output a system clock.
The clock device according to claim 1, wherein the clock interface module comprises: a detecting unit and a clock driving unit, wherein

The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and when determining that the state of the clock link signal is abnormal, send a switch control signal to the clock driving unit;

The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
The clock device according to claim 1, wherein said clock interface module comprises a detecting unit, a filtering unit, and a clock driving unit, wherein:

The detecting unit is configured to: receive and detect a clock link signal sent by the upstream clock device, and notify the filtering unit when determining that the state of the clock link signal is abnormal;

The filtering unit is configured to perform noise filtering processing on the clock link signal that is determined to be abnormal by the detecting unit, and detect the clock link signal after the noise filtering process, when determining the When the state of the clock link signal after the noise filtering process is abnormal, sending a switch control signal to the clock driving unit;

The clock driving unit is configured to turn off a clock output of the clock interface module according to the switch control signal.
The clock device according to any one of claims 1 to 3, wherein the clock processing module is configured to:

When the phase locked loop circuit detects that the clock interface module has no clock output within a preset time When it enters the clock hold state, it outputs the system clock.
The clock device of claim 4, wherein the clock link signal is an Ethernet signal or a second pulse signal.
A clock holding method of a clock device, the clock device includes: a clock interface module and a clock processing module, and the method includes:

The clock interface module monitors the received clock link signal, and when it is determined that the clock link signal is abnormal, the clock output of the clock interface module is turned off;

The clock processing module enters a clock hold state and outputs a system clock when detecting that the clock output of the clock interface module is in a closed state.
The clock keeping method of a clock device according to claim 6, wherein the clock interface module monitors the received clock link signal, and when the clock link signal is abnormal, the clock output of the clock interface module is turned off. The steps include:

The clock interface module receives and detects a clock link signal sent by the upstream clock device, and when it is determined that the state of the clock link signal is abnormal, generates a switch control signal, and closes the clock interface module according to the switch control signal. Clock output.
The clock keeping method of a clock device according to claim 6, wherein the clock interface module monitors the received clock link signal, and when the clock link signal is abnormal, the clock output of the clock interface module is turned off. The steps include:

The clock interface module receives and detects a clock link signal sent by the upstream clock device, performs noise filtering processing on the clock link signal that is determined to be abnormal, and detects the clock link signal after the noise filtering process. And determining that a state of the clock link signal after the noise filtering process is abnormal, generating a switch control signal, and turning off a clock output of the clock interface module according to the switch control signal.
The clock holding method of a clock device according to any one of claims 6 to 8, wherein the clock processing module enters a clock hold state when detecting that the clock output of the clock interface module is in an off state, and outputs the system The steps of the clock include:

When the phase-locked loop circuit detects that the clock interface module has no clock output within a preset time, it enters a clock hold state and outputs a system clock.
A clock holding method of a clock device according to claim 9, wherein said clock link signal is an Ethernet signal or a second pulse signal.
A computer readable storage medium storing computer executable instructions for performing the method of any of claims 6-10.