CN105790873A - Clock equipment for retaining clock and clock retaining method for clock equipment - Google Patents
Clock equipment for retaining clock and clock retaining method for clock equipment Download PDFInfo
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- CN105790873A CN105790873A CN201410837161.6A CN201410837161A CN105790873A CN 105790873 A CN105790873 A CN 105790873A CN 201410837161 A CN201410837161 A CN 201410837161A CN 105790873 A CN105790873 A CN 105790873A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Abstract
The invention discloses clock equipment for retaining a clock. The clock equipment comprises a clock interface module and a clock processing module, wherein the clock interface module is used for monitoring a received clock link signal and closing clock output of the clock interface module when judging that the clock link signal is abnormal; the clock processing module is used for entering into a clock retaining state when detecting that the clock output of the clock interface module is in a closed state and outputting a system clock. The invention also discloses a clock retaining method for the clock equipment. According to the clock equipment and the method, the time from detection of the abnormal clock link signal through the clock interface module to entrance of the clock processing module into the clock retaining state is minimized, so that the frequency jump of the system clock, which is output by the clock processing module, is greatly reduced and is controlled within 1ppb to meet the retaining performance of the clock equipment.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of clockwork keeping clock and method.
Background technology
At present in SDH clock transmission, clock tranmission techniques based on Ethernet is increasingly widely applied, and its output clock performance can meet the clock characteristic of International Telecommunication Union's telecommunication standardsization tissue (ITU-TforITUTelecommunicationStandardizationSector) defined substantially.But owing to application scenarios is changeful, application mode is also of all kinds, under some application scenario, clock performance need to improve.Such as, when upstream clock equipment transmits clock to downstream clockwork by Ethernet, if the unexpected drop of link or clock suddenly disappear, ITU-T standard requires downstream clockwork can enter into maintenance pattern and clock keeps state, and keeps precision to meet the performance requirement that standard specifies.
Existing conventional mode is downstream clock interface equipment once after the clock losing lock that detects in link, then send unavailable clock quality class information DNU and process equipment to downstream clock, after downstream clock process equipment receives this DNU information, need this DNU information is resolved, after being parsed, just can enter into maintenance pattern.So, clock losing lock in downstream clock interface equipment Inspection to link is until downstream clock processes equipment and enters into and need through operating processes such as the forwarding of DNU information and parsings in the process of maintenance pattern, simultaneously, downstream clock processes the locking source of equipment and is become local crystal oscillator from original link clock, making output clock generation saltus step, system clock is saltus step therewith also.Find after tested, clock losing lock in downstream clock interface equipment Inspection to link, the process entering into maintenance pattern until downstream clock process equipment through forwarding and the parsing operation of DNU information needs the time spent to be ms (millisecond) level, system clock is made to produce the frequency hopping of ppm level, it is impossible to meet the maintenance performance that the downstream clockwork of ITU-T standard requirement should possess.
Foregoing is only used for assisting understanding technical scheme, does not represent and admits that foregoing is prior art.
Summary of the invention
Present invention is primarily targeted at a kind of clockwork keeping clock of offer and method, to solve the technical problem that in existing clockwork, system clock saltus step spended time is long.
For achieving the above object, a kind of clockwork keeping clock provided by the invention, described clockwork includes: clock interface module and clock processing module, wherein,
Described clock interface module, for monitoring the clock chain circuit signal of reception, when judging described clock chain circuit abnormal signal, closes the clock output of described clock interface module；
Described clock processing module, when being closed for exporting when the clock described clock interface module being detected, enters clock and keeps state, export system clock.
Preferably, described clock interface module includes: detection unit, clock driver cell, wherein,
Described detection unit, for receiving and detect the clock chain circuit signal that upstream clock equipment sends, when judging the abnormal state of described clock chain circuit signal, sends switch controlling signal extremely described clock driver cell；
Described clock driver cell, for closing the clock output of described clock interface module according to described switch controlling signal.
Preferably, described clock interface module also includes:
Filter unit, for the described clock chain circuit signal being abnormal through described detection unit judges carries out noise filtering process, and detects the described clock chain circuit signal after noise filtering processes.
Preferably, described clock processing module specifically for:
When described clock interface module exports without clock in Preset Time when utilizing phase-locked loop circuit to detect, enter clock and keep state, export system clock.
Preferably, described clock chain circuit signal is ethernet signal or pps pulse per second signal.
Additionally, for achieving the above object, the present invention also provides for the clock keeping method of a kind of clockwork, and described clockwork includes: clock interface module and clock processing module, said method comprising the steps of:
The clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, closes the clock output of described clock interface module；
Described clock processing module, when the clock output described clock interface module being detected is closed, enters clock and keeps state, export system clock.
Preferably, the clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, the step of the clock output closing described clock interface module includes:
Described clock interface module receives and detects the clock chain circuit signal that upstream clock equipment sends, when judging the abnormal state of described clock chain circuit signal, generate switch controlling signal, and close the clock output of described clock interface module according to described switch controlling signal.
Preferably, the clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, the step of the clock output closing described clock interface module also includes:
To being judged as that abnormal described clock chain circuit signal carries out noise filtering process, and the described clock chain circuit signal after noise filtering processes is detected.
Preferably, described clock processing module, when the clock output described clock interface module being detected is closed, enters clock and keeps state, and the step of output system clock specifically includes:
When described clock interface module exports without clock in Preset Time when utilizing phase-locked loop circuit to detect, enter clock and keep state, export system clock.
Preferably, described clock chain circuit signal is ethernet signal or pps pulse per second signal.
A kind of clockwork keeping clock of present invention proposition and method, when detecting that the clock chain circuit signal that upstream clock equipment sends occurs abnormal by the clock interface module in clockwork, close the clock output of described clock interface module；nullSo，Clock processing module in clockwork is when the clock output described clock interface module being detected is closed，Namely would know that clock chain circuit abnormal signal，Then immediately enter clock and keep state，Output system clock，Without clock interface module when clock chain circuit abnormal signal being detected，DNU information is sent to clock processing module，Clock processing module just can enter into clock and keep state after again DNU information being resolved，The troublesome operation such as the forwarding and the parsing that decrease DNU information，Make the clock processing module in clockwork can quickly enter clock and keep state，Shorten to greatest extent and detect that clock chain circuit abnormal signal enters clock to clock processing module and keeps the time of state from clock interface module，Thus greatly reducing the frequency hopping of clock processing module output system clock，And control within 1ppb，To meet the maintenance performance that clockwork should possess.
Accompanying drawing explanation
Fig. 1 is the high-level schematic functional block diagram that the present invention keeps the clockwork first embodiment of clock；
Fig. 2 is the refinement high-level schematic functional block diagram of clock interface module 01 in Fig. 1；
Fig. 3 is that the present invention keeps the refinement high-level schematic functional block diagram of clock interface module 01 in clockwork second embodiment of clock；
Fig. 4 is the schematic flow sheet of clock keeping method one embodiment of clockwork of the present invention.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Detailed description of the invention
Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
The present invention provides a kind of clockwork keeping clock.
It is the high-level schematic functional block diagram that the present invention keeps the clockwork first embodiment of clock with reference to Fig. 1, Fig. 1.
In the first embodiment, this clockwork includes: clock interface module 01 and clock processing module 02, wherein,
Described clock interface module 01, for monitoring the clock chain circuit signal of reception, when judging described clock chain circuit abnormal signal, closes the clock output of described clock interface module 01；
Described clock processing module 02, when being closed for exporting when the clock described clock interface module 01 being detected, enters clock and keeps state, export system clock.
When the present embodiment detects that the clock chain circuit signal that upstream clock equipment sends occurs abnormal by the clock interface module 01 in clockwork, close the clock output of described clock interface module 01；nullSo，Clock processing module 02 in clockwork is when the clock output described clock interface module 01 being detected is closed，Namely would know that clock chain circuit abnormal signal，Then immediately enter clock and keep state，Output system clock，Without clock interface module 01 when clock chain circuit abnormal signal being detected，DNU information is sent to clock processing module 02，Clock processing module 02 just can enter into clock and keep state after again DNU information being resolved，The troublesome operation such as the forwarding and the parsing that decrease DNU information，Make the clock processing module 02 in clockwork can quickly enter clock and keep state，Shorten to greatest extent and detect that clock chain circuit abnormal signal enters clock to clock processing module 02 and keeps the time of state from clock interface module 01，Thus greatly reducing clock processing module 02 to export the frequency hopping of system clock，And control within 1ppb，To meet the maintenance performance that clockwork should possess.
Further, as in figure 2 it is shown, above-mentioned clock interface module 01 includes: detection unit 03, clock driver cell 04, wherein,
Described detection unit 03, for receiving and detect the clock chain circuit signal that upstream clock equipment sends, when judging the abnormal state of described clock chain circuit signal, sends switch controlling signal extremely described clock driver cell 04；
Described clock driver cell 04, for closing the clock output of described clock interface module 01 according to described switch controlling signal.
Detection unit 03 monitors the clock chain circuit signal that upstream clock equipment sends in real time, and the state of the clock chain circuit signal received is detected, during the abnormal state of clock link signal upon this detection, illustrate that the situations such as disconnection or clock chain circuit dropout occurs in data link, then clock interface module 01 loses the clock source of upstream clock equipment input, the clock in clock chain circuit signal cannot be recovered, namely it is automatically locked on local crystal oscillator, but now clock interface module 01 can't export the local crystal oscillator and local oscillator clock that now lock, but sent switch controlling signal extremely described clock driver cell 04 by detection unit 03；Clock driver cell 04 controls the clock output of described clock interface module 01 according to the switch controlling signal that detection unit 03 sends, when detecting the abnormal state that unit 03 detects clock chain circuit signal, switch controlling signal is sent to clock driver cell 04, clock driver cell 04 can close the clock output of described clock interface module 01 according to this switch controlling signal, so, namely the output clock of described clock interface module 01 becomes high-impedance state.
Further, above-mentioned clock processing module 02 specifically for:
When described clock interface module 01 exports without clock in Preset Time when utilizing phase-locked loop circuit to detect, enter clock and keep state, export system clock.
It is closed when the clock of described clock interface module 01 exports, namely when the output clock of described clock interface module 01 becomes high-impedance state, clock processing module 02 can adopt phase-locked loop circuit to detect.Due to clock processing module 02 employing is that phase-locked loop circuit is to lock the clock of normal clock chain circuit signal recovery or to enter clock maintenance state, and during phase-locked loop circuit entrance clock maintenance state except can passing through the mode of distribution configuration command, also can when detecting that clock source is lost when phase-locked loop circuit, state is kept automatically into clock, this is a kind of basic function that most phase-locked loop chip all possesses, and the phase-locked loop circuit adopted in the clockwork of SDH must possess this function.Therefore, in the present embodiment, the clock processing module 02 of clockwork can adopt phase-locked loop circuit that the clock output state of clock interface module 01 is detected, when the phase-locked loop circuit in clock processing module 02 detects that described clock interface module 01 exports without clock in Preset Time, namely would know that clock chain circuit signal occurs abnormal, clock source is lost, then clock processing module 02 immediately enters clock maintenance state, exports system clock.It should be noted that, before utilizing phase-locked loop circuit to detect the clock output state of described clock interface module 01 in Preset Time, this Preset Time can be configured, as required this Preset Time can be set to relatively low such as 1 to 2 cycle, so, phase-locked loop circuit is utilized to detect when described clock interface module 01 exports without clock within 1 to 2 cycle, clock processing module 02 can immediately enter clock and keep state, decrease the time of detection cost, clock processing module 02 can be made to enter clock faster and to keep state, thus reducing the frequency hopping of output system clock.
nullIn the present embodiment, clock processing module 02 utilizes this hardware means of phase-locked loop circuit to detect the clock output state of described clock interface module 01 in Preset Time，And when detecting that described clock interface module 01 exports without clock，State is kept automatically into clock，Output system clock，Shorten clock processing module 02 as much as possible and enter the time of clock maintenance state，Without clock interface module 01 when clock chain circuit abnormal signal being detected，DNU information is sent to clock processing module 02，Clock processing module 02 just can enter into clock and keep state after again DNU information being resolved，The troublesome operation such as the forwarding and the parsing that decrease DNU information，Make the clock processing module 02 in clockwork can quickly enter clock and keep state，Shorten to greatest extent and detect that clock chain circuit abnormal signal enters clock to clock processing module 02 and keeps the time of state from clock interface module 01，Thus greatly reducing clock processing module 02 to export the frequency hopping of system clock，And control within 1ppb，To meet the maintenance performance that clockwork should possess.
Further, as it is shown on figure 3, second embodiment of the invention proposes a kind of clockwork keeping clock, on the basis of above-mentioned first embodiment, described clock interface module 01 also includes:
Filter unit 05, for being judged as that abnormal described clock chain circuit signal carries out noise filtering process to through described detection unit 03, and detects the described clock chain circuit signal after noise filtering processes.
In the present embodiment, when detecting the abnormal state that unit 03 detects clock chain circuit signal, first pass through filter unit 05 and be judged as that abnormal described clock chain circuit signal carries out noise filtering process to through described detection unit 03, and continue the described clock chain circuit signal after noise filtering processes is detected, if still detecting the abnormal state of described clock chain circuit signal, just send switch controlling signal to described clock driver cell 04, so that clock driver cell 04 closes the clock output of described clock interface module 01 according to described switch controlling signal.So, in the present embodiment only when unit 03 after testing and filter unit 05 all detect the abnormal state of described clock chain circuit signal, just can send switch controlling signal extremely described clock driver cell 04, efficiently avoid the situation because the clock transfer link of upstream clock equipment is that may be present unstable in short-term or environmental disturbances causes detection unit 03 to judge by accident, the clock chain circuit signal condition that more accurately upstream clock equipment can be sent judges, and then when confirming that clock chain circuit signal is the abnormalities such as dropout, clock driver cell 04 is just made to close the clock output of described clock interface module 01, reduce and keep the probability of state because erroneous judgement causes clock processing module 02 to enter clock, enhance the stability of clockwork.
Further, the clock chain circuit signal that upstream clock equipment sends can be ethernet signal or pulse per second (PPS) (1PPS) signal.
nullThe clock commonly used interface type of transmission based on Ethernet is Ethernet light mouth and Ethernet electricity mouth，When clock interface module 01 receives the synchronous ethernet signal that upstream clock equipment is transmitted by optical fiber，Owing to optical module itself can produce dropout LOS indication signal，And noise filtering process can be carried out inside optical module，Namely dropout can be carried out noise filtering by optical module itself、Loss detection etc. process，Therefore，If the detection unit 03 of clock interface module 01 obtains the LOS indication signal in synchronous ethernet signal in actual applications，Then can directly know the abnormal state of clock chain circuit signal，And without further carrying out noise filtering process，And send switch controlling signal extremely described clock driver cell 04 according to the LOS indication signal in synchronous ethernet signal，So that clock driver cell 04 closes the clock output of described clock interface module 01 according to described switch controlling signal.
When clock interface module 01 receives the synchronous ethernet signal that upstream clock equipment is transmitted by netting twine, synchronous ethernet physical chip interrupts owing to can produce dropout, and the generation of this interruption also can process through noise filtering inside synchronous ethernet physical chip, therefore, if the detection unit 03 of clock interface module 01 obtains the dropout interruption in synchronous ethernet signal in actual applications, then can directly know the abnormal state of clock chain circuit signal, and without further carrying out noise filtering process, and interrupt sending switch controlling signal extremely described clock driver cell 04 according to the dropout in synchronous ethernet signal, so that clock driver cell 04 closes the clock output of described clock interface module 01 according to described switch controlling signal.
When clock interface module 01 receives pulse per second (PPS) (1PPS) signal that upstream clock equipment is transmitted by 1PPS interface, the state of the detection unit 03 of the clock interface module 01 1PPS signal to receiving detects in real time, when the abnormal state of 1PPS signal being detected, this 1PPS signal is sent to filter unit 05, by filter unit 05, this 1PPS signal is carried out noise filtering process, and continue the 1PPS signal after noise filtering processes is detected, if still detecting the abnormal state of 1PPS signal, just send switch controlling signal extremely described clock driver cell 04, so that clock driver cell 04 closes the clock output of described clock interface module 01 according to described switch controlling signal.And then, when the phase-locked loop circuit in clock processing module 02 detects that described clock interface module 01 exports without clock in Preset Time, clock can be immediately entered and keep state, export system clock.
The present invention further provides the clock keeping method of a kind of clockwork.Described clockwork includes: clock interface module and clock processing module.
Schematic flow sheet with reference to clock keeping method one embodiment that Fig. 4, Fig. 4 are clockwork of the present invention.
In one embodiment, the clock keeping method of this clockwork includes:
Step S10, the clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, close the clock output of described clock interface module；
Step S20, described clock processing module, when the clock output described clock interface module being detected is closed, enters clock and keeps state, export system clock.
When the present embodiment detects that the clock chain circuit signal that upstream clock equipment sends occurs abnormal by the clock interface module in clockwork, close the clock output of described clock interface module；nullSo，Clock processing module in clockwork is when the clock output described clock interface module being detected is closed，Namely would know that clock chain circuit abnormal signal，Then immediately enter clock and keep state，Output system clock，Without clock interface module when clock chain circuit abnormal signal being detected，DNU information is sent to clock processing module，Clock processing module just can enter into clock and keep state after again DNU information being resolved，The troublesome operation such as the forwarding and the parsing that decrease DNU information，Make the clock processing module in clockwork can quickly enter clock and keep state，Shorten to greatest extent and detect that clock chain circuit abnormal signal enters clock to clock processing module and keeps the time of state from clock interface module，Thus greatly reducing the frequency hopping of clock processing module output system clock，And control within 1ppb，To meet the maintenance performance that clockwork should possess.
Further, in other embodiments, above-mentioned steps S10 may include that described clock interface module receives and detect the clock chain circuit signal that upstream clock equipment sends, when judging the abnormal state of described clock chain circuit signal, generate switch controlling signal, and close the clock output of described clock interface module according to described switch controlling signal.
nullDescribed clock interface module monitors the clock chain circuit signal that upstream clock equipment sends in real time，And the state of the clock chain circuit signal received is detected，During the abnormal state of clock link signal upon this detection，Illustrate that the situations such as disconnection or clock chain circuit dropout occurs in data link，Then clock interface module loses the clock source of upstream clock equipment input，The clock in clock chain circuit signal cannot be recovered，Namely it is automatically locked on local crystal oscillator，But now clock interface module can't export the local crystal oscillator and local oscillator clock that now lock，But generation switch controlling signal，And the clock output of described clock interface module is controlled according to the switch controlling signal generated，During the abnormal state of clock link signal upon this detection，The clock output of described clock interface module can be closed according to the switch controlling signal generated，So，Namely the output clock of described clock interface module becomes high-impedance state.
Further, in other embodiments, above-mentioned steps S20 may include that
When described clock interface module exports without clock in Preset Time when utilizing phase-locked loop circuit to detect, enter clock and keep state, export system clock.
It is closed when the clock of described clock interface module exports, namely when the output clock of described clock interface module becomes high-impedance state, clock processing module can adopt phase-locked loop circuit to detect.Due to the employing of clock processing module is that phase-locked loop circuit is to lock the clock of normal clock chain circuit signal recovery or to enter clock maintenance state, and during phase-locked loop circuit entrance clock maintenance state except can passing through the mode of distribution configuration command, also can when detecting that clock source is lost when phase-locked loop circuit, state is kept automatically into clock, this is a kind of basic function that most phase-locked loop chip all possesses, and the phase-locked loop circuit adopted in the clockwork of SDH must possess this function.Therefore, in the present embodiment, the clock processing module of clockwork can adopt phase-locked loop circuit that the clock output state of clock interface module is detected, when the phase-locked loop circuit in clock processing module detects that described clock interface module exports without clock in Preset Time, namely would know that clock chain circuit signal occurs abnormal, clock source is lost, then clock processing module immediately enters clock maintenance state, exports system clock.It should be noted that, before utilizing phase-locked loop circuit to detect the clock output state of described clock interface module in Preset Time, this Preset Time can be configured, as required this Preset Time can be set to relatively low such as 1 to 2 cycle, so, phase-locked loop circuit is utilized to detect when described clock interface module exports without clock within 1 to 2 cycle, clock processing module can immediately enter clock and keep state, decrease the time of detection cost, clock processing module can be made to enter clock faster and to keep state, thus reducing the frequency hopping of output system clock.
nullIn the present embodiment, clock processing module utilizes this hardware means of phase-locked loop circuit to detect the clock output state of described clock interface module in Preset Time，And when detecting that described clock interface module exports without clock，State is kept automatically into clock，Output system clock，Shorten clock processing module as much as possible and enter the time of clock maintenance state，Without clock interface module when clock chain circuit abnormal signal being detected，DNU information is sent to clock processing module，Clock processing module just can enter into clock and keep state after again DNU information being resolved，The troublesome operation such as the forwarding and the parsing that decrease DNU information，Make the clock processing module in clockwork can quickly enter clock and keep state，Shorten to greatest extent and detect that clock chain circuit abnormal signal enters clock to clock processing module and keeps the time of state from clock interface module，Thus greatly reducing the frequency hopping of clock processing module output system clock，And control within 1ppb，To meet the maintenance performance that clockwork should possess.
Further, second embodiment of the invention proposes the clock keeping method of a kind of clockwork, and on the basis of above-mentioned first embodiment, above-mentioned steps S10 also includes:
To being judged as that abnormal described clock chain circuit signal carries out noise filtering process, and the described clock chain circuit signal after noise filtering processes is detected.
In the present embodiment, when described clock interface module detects the abnormal state of clock chain circuit signal, first to being judged as that abnormal described clock chain circuit signal carries out noise filtering process, and continue the described clock chain circuit signal after noise filtering processes is detected, if still detecting the abnormal state of described clock chain circuit signal, just generate switch controlling signal, to close the clock output of described clock interface module according to described switch controlling signal.So, only when the abnormal state of clock chain circuit signal described in double check in the present embodiment, just can generate switch controlling signal, efficiently avoid the situation because the clock transfer link of upstream clock equipment is that may be present unstable in short-term or environmental disturbances causes detection to judge by accident, the clock chain circuit signal condition that more accurately upstream clock equipment can be sent judges, and then when confirming that clock chain circuit signal is the abnormalities such as dropout, just close the clock output of described clock interface module, reduce and keep the probability of state because erroneous judgement causes clock processing module to enter clock, enhance the stability of clockwork.
Further, the clock chain circuit signal that upstream clock equipment sends can be ethernet signal or pulse per second (PPS) (1PPS) signal.
The clock commonly used interface type of transmission based on Ethernet is Ethernet light mouth and Ethernet electricity mouth, when clock interface module receives the synchronous ethernet signal that upstream clock equipment is transmitted by optical fiber, owing to optical module itself can produce dropout LOS indication signal, and noise filtering process can be carried out inside optical module, namely dropout can be carried out noise filtering by optical module itself, loss detection etc. process, therefore, if clock interface module gets the LOS indication signal in synchronous ethernet signal in actual applications, then can directly know the abnormal state of clock chain circuit signal, and without further carrying out noise filtering process, and generate switch controlling signal according to the LOS indication signal in synchronous ethernet signal, to close the clock output of described clock interface module according to described switch controlling signal.
When clock interface module receives the synchronous ethernet signal that upstream clock equipment is transmitted by netting twine, synchronous ethernet physical chip interrupts owing to can produce dropout, and the generation of this interruption also can process through noise filtering inside synchronous ethernet physical chip, therefore, if clock interface module gets the dropout interruption in synchronous ethernet signal in actual applications, then can directly know the abnormal state of clock chain circuit signal, and without further carrying out noise filtering process, and interrupt generating switch controlling signal according to the dropout in synchronous ethernet signal, to close the clock output of described clock interface module according to described switch controlling signal.
When clock interface module receives pulse per second (PPS) (1PPS) signal that upstream clock equipment is transmitted by 1PPS interface, the state of the clock interface module 1PPS signal to receiving detects in real time, when the abnormal state of 1PPS signal being detected, this 1PPS signal is carried out noise filtering process, and continue the 1PPS signal after noise filtering processes is detected, if still detecting the abnormal state of 1PPS signal, just generate switch controlling signal, to close the clock output of described clock interface module according to described switch controlling signal.And then, when the phase-locked loop circuit in clock processing module detects that described clock interface module exports without clock in Preset Time, clock can be immediately entered and keep state, export system clock.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.Through the above description of the embodiments, those skilled in the art is it can be understood that can add the mode of required general hardware platform by software to above-described embodiment method and realize, hardware can certainly be passed through, but in a lot of situation, the former is embodiment more preferably.Based on such understanding, the part that prior art is contributed by technical scheme substantially in other words can embody with the form of software product, this computer software product is stored in a storage medium (such as ROM/RAM, magnetic disc, CD), including some instructions with so that a station terminal equipment (can be mobile phone, computer, server, or the network equipment etc.) perform the method described in each embodiment of the present invention.
These are only the preferred embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every equivalent structure utilizing description of the present invention and accompanying drawing content to make or equivalence flow process conversion; or directly or indirectly it is used in other relevant technical fields, all in like manner include in the scope of patent protection of the present invention.
Claims (10)
1. the clockwork keeping clock, it is characterised in that described clockwork includes: clock interface module and clock processing module, wherein,
Described clock interface module, for monitoring the clock chain circuit signal of reception, when judging described clock chain circuit abnormal signal, closes the clock output of described clock interface module；
Described clock processing module, when being closed for exporting when the clock described clock interface module being detected, enters clock and keeps state, export system clock.
2. clockwork as claimed in claim 1, it is characterised in that described clock interface module includes: detection unit, clock driver cell, wherein,
Described detection unit, for receiving and detect the clock chain circuit signal that upstream clock equipment sends, when judging the abnormal state of described clock chain circuit signal, sends switch controlling signal extremely described clock driver cell；
Described clock driver cell, for closing the clock output of described clock interface module according to described switch controlling signal.
3. clockwork as claimed in claim 2, it is characterised in that described clock interface module also includes:
Filter unit, for the described clock chain circuit signal being abnormal through described detection unit judges carries out noise filtering process, and detects the described clock chain circuit signal after noise filtering processes.
4. clockwork as described in any one in claims 1 to 3, it is characterised in that described clock processing module specifically for:
When described clock interface module exports without clock in Preset Time when utilizing phase-locked loop circuit to detect, enter clock and keep state, export system clock.
5. clockwork as claimed in claim 4, it is characterised in that described clock chain circuit signal is ethernet signal or pps pulse per second signal.
6. the clock keeping method of a clockwork, it is characterised in that described clockwork includes: clock interface module and clock processing module, said method comprising the steps of:
The clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, closes the clock output of described clock interface module；
Described clock processing module, when the clock output described clock interface module being detected is closed, enters clock and keeps state, export system clock.
7. the clock keeping method of clockwork as claimed in claim 6, it is characterized in that, the clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, the step of the clock output closing described clock interface module includes:
Described clock interface module receives and detects the clock chain circuit signal that upstream clock equipment sends, when judging the abnormal state of described clock chain circuit signal, generate switch controlling signal, and close the clock output of described clock interface module according to described switch controlling signal.
8. the clock keeping method of clockwork as claimed in claim 7, it is characterized in that, the clock chain circuit signal that described clock interface module monitors receives, when judging described clock chain circuit abnormal signal, the step of the clock output closing described clock interface module also includes:
To being judged as that abnormal described clock chain circuit signal carries out noise filtering process, and the described clock chain circuit signal after noise filtering processes is detected.
9. the clock keeping method of the clockwork as described in any one in claim 6 to 8, it is characterized in that, described clock processing module, when the clock output described clock interface module being detected is closed, enters clock and keeps state, and the step of output system clock specifically includes:
When described clock interface module exports without clock in Preset Time when utilizing phase-locked loop circuit to detect, enter clock and keep state, export system clock.
10. the clock keeping method of clockwork as claimed in claim 9, it is characterised in that described clock chain circuit signal is ethernet signal or pps pulse per second signal.
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| CN201410837161.6A CN105790873B (en) | 2014-12-26 | 2014-12-26 | Keep the clockwork and method of clock |
| PCT/CN2015/097014 WO2016101792A1 (en) | 2014-12-26 | 2015-12-10 | Clock device and method for maintaining clock |
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| CN201410837161.6A CN105790873B (en) | 2014-12-26 | 2014-12-26 | Keep the clockwork and method of clock |
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| CN111355551A (en) * | 2020-02-11 | 2020-06-30 | 西安电子科技大学 | Network clock synchronization method and device suitable for semi-stable link |
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| CN101645718B (en) * | 2008-08-07 | 2013-08-07 | 中兴通讯股份有限公司 | Method and device for holding clock |
| CN102946291A (en) * | 2012-11-12 | 2013-02-27 | 华为技术有限公司 | Clock maintaining method and clock equipment |
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| US20050149775A1 (en) * | 2004-01-06 | 2005-07-07 | Alcatel | Redundant synchronous clock distribution method, a related clock module and a related clock slave device |
| CN101431444A (en) * | 2007-11-07 | 2009-05-13 | 中兴通讯股份有限公司 | Test method for transmission equipment clock synchronous information switching time delay |
| CN101252405A (en) * | 2008-03-27 | 2008-08-27 | 华为技术有限公司 | Clock detection and auto switching method, system and testing circuit |
| CN101547053A (en) * | 2008-03-28 | 2009-09-30 | 华为技术有限公司 | Clock-switching method and clock-generating device |
| CN101853192A (en) * | 2010-05-31 | 2010-10-06 | 华为技术有限公司 | Exception handling method and system, off-chip logic device and chip |
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| CN111355551A (en) * | 2020-02-11 | 2020-06-30 | 西安电子科技大学 | Network clock synchronization method and device suitable for semi-stable link |
Also Published As
| Publication number | Publication date |
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| CN105790873B (en) | 2019-06-21 |
| WO2016101792A1 (en) | 2016-06-30 |
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