CN116886227A - Clock switching method and network equipment - Google Patents

Clock switching method and network equipment Download PDF

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Publication number
CN116886227A
CN116886227A CN202310759853.2A CN202310759853A CN116886227A CN 116886227 A CN116886227 A CN 116886227A CN 202310759853 A CN202310759853 A CN 202310759853A CN 116886227 A CN116886227 A CN 116886227A
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CN
China
Prior art keywords
clock
state
chip
clock chip
clock source
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CN202310759853.2A
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Chinese (zh)
Inventor
王凡
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New H3C Technologies Co Ltd
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New H3C Technologies Co Ltd
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Priority to CN202310759853.2A priority Critical patent/CN116886227A/en
Publication of CN116886227A publication Critical patent/CN116886227A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The present specification provides a method and a network device for clock switching, where the method includes: and monitoring an external clock source state of the access clock chip, when the external clock source state is abnormal, placing the clock chip in a Holdover state, enabling the clock chip to provide a clock signal for lower-level equipment in the Holdover state, and when the external clock source state is identified to be recovered to be normal, canceling the Holdover state of the clock chip and enabling the clock chip to receive the external clock source signal. By the method, when an external clock source is unstable, the clock chip can be ensured to provide a normal clock signal, and the situation of service interruption is avoided.

Description

Clock switching method and network equipment
Technical Field
The disclosure relates to the field of communication technologies, and in particular, to a clock switching method and network equipment.
Background
When the current network equipment communicates with the external equipment, clock synchronization is usually used to realize accurate synchronization of time of the two equipment, clock signals of the opposite end are recovered from an interface of the opposite end in a butt joint mode generally through a synchronous Ethernet technology, the local end equipment locks the recovered clock signals by using a clock chip and provides locked clock output for the current network equipment, and therefore the purpose of clock synchronization of the two equipment is achieved through clock chip locking.
When the devices are interconnected by different interfaces and different network devices, the frequencies of clock signals recovered by the different interfaces are different due to different rates of the interfaces, as shown in fig. 1: the default network device uses the clock source 1 of the interface 1, and when the interface 1 fails, the clock chip switches to the clock source 2 of the interface 2 in real time. In the process of clock switching, the state of the clock chip can lock the clock source 1 to lose lock and then lock the clock source 2 again, and in the switching process, the clock signal quality recovered by the clock chip 1 can be degraded due to different clock signal frequencies of different interfaces, so that the system reference clock source is unstable and further the situation that the service is affected, such as packet loss, occurs.
Disclosure of Invention
The embodiment of the disclosure provides a clock switching method and network equipment, by which a clock chip can be ensured to provide a normal clock signal when an external clock source is unstable, and the situation of service interruption is avoided.
The embodiment of the disclosure provides a clock switching method, which comprises the following steps:
monitoring the state of an external clock source connected to a clock chip;
when the state of the external clock source is abnormal, the clock chip is placed in a Holdover state, so that the clock chip provides a clock signal for the lower-level equipment in the Holdover state;
and when the state of the external clock source is identified to be recovered to be normal, canceling the Holdover state of the clock chip, and enabling the clock chip to receive the signal of the external clock source.
The monitoring the external clock source state of the access clock chip comprises the following steps:
the state of an interface receiving an external clock source signal is monitored.
And when the condition of the interface receiving the external clock source signal is monitored to generate jitter or noise exceeding a threshold value, determining that the condition of the external clock source is abnormal.
Wherein, when the external clock source state is abnormal, the method further comprises:
the clock chip acquires a local clock crystal oscillator signal.
Wherein, when the external clock source state is identified to be recovered to normal, the method further comprises:
the clock chip is switched from acquiring a local clock crystal oscillator signal to acquiring an external clock source signal.
According to the embodiment, when the abnormal state of the external clock source is detected, the clock chip can be placed in the Holdover state, and when the lower-level clock chip exists, the lower-level clock chip can be indicated to be placed in the Holdover state, so that the clock chip can output a stable clock signal under the condition that the external clock source is dithered, and the condition that service is interrupted by equipment is prevented.
The embodiment of the disclosure also provides a network device, which includes: clock chip and monitoring module
The monitoring module is used for monitoring the state of an external clock source accessed to the clock chip;
the clock chip is used for monitoring the abnormal state notification of the external clock source sent by the module, judging whether a lower clock chip exists, if so, notifying the lower clock chip to be in a Holdover state, and if not, placing the target clock chip in the Holdover state;
the clock chip is also used for receiving the external clock source state recovery notice sent by the monitoring module, notifying the lower-level clock chip to cancel the Holdover state or canceling the target clock chip from the Holdover state, and enabling the target clock chip to receive the external clock source signal.
The monitoring module is used for monitoring the state of an interface receiving an external clock source signal.
The monitoring module is used for determining that the state of the external clock source is abnormal when the condition of the interface receiving the external clock source signal is monitored to shake or noise exceeds a threshold value.
The clock chip is further used for acquiring a local clock crystal oscillator signal when the state of the external clock source is abnormal.
And after receiving the notification of the recovery of the external clock source state sent by the monitoring module, the clock chip switches from acquiring the local clock crystal oscillator signal to acquiring the external clock source signal.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and together with the description, serve to explain the principles of the specification.
Fig. 1 is a schematic diagram of a network architecture for obtaining a clock signal according to an embodiment of the disclosure.
Fig. 2 is a flowchart of a method for clock switching according to an embodiment of the disclosure.
Fig. 3 is a schematic diagram of a network architecture for obtaining a clock signal according to an embodiment of the disclosure.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present description as detailed in the accompanying claims.
The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
In order to solve the problem of signal quality such as clock jitter generated by clock source switching, the current clock chip manufacturer designs a corresponding clock switching mode to optimize jitter performance, for example, hitless Input Switching mode can be used for clock source switching with the same frequency, and the purpose of reducing jitter of output clock signals is achieved by calculating differences of two clock sources in advance and performing optimization processing.
However, the clock source switching configuration of the existing chip has the following disadvantages:
for example, there is a requirement on the clock source frequency, hitless Input Switching requires that the two clock source frequencies are the same, glitchless Input Switching requires that the two clock source frequencies differ within a certain range (+ -500 ppm), because the network device cannot recover clock signals with any frequency corresponding to the limitation of the hardware design of the NP processor chip, only a specified frequency division coefficient can be configured to recover clock signals, the clock signals recovered by interfaces with different rates cannot be identical, taking 400G/100G interfaces as an example, according to the configuration of a NP chip, as shown in table 1, wherein the NP configurable frequency division coefficient is 2,3,4,5,8,25,33 fixed values, the minimum difference between the clock frequencies recovered by the two interfaces is 400G/33.203M, 100G/32.2265625M, which cannot meet the requirements of Hitless Input Switching and Glitchless Input Switching, and cannot be optimized.
TABLE 1
In order to solve the above technical problem, an embodiment of the present disclosure provides a method for clock switching, as shown in fig. 2, the method includes:
s201, monitoring the state of an external clock source accessed to a target clock chip;
s202, when the state of an external clock source is abnormal, judging whether a lower-level clock chip exists, if so, informing the lower-level clock chip to be in a Holdover state, and if not, putting a target clock chip to be in the Holdover state;
and S203, when the external clock source state is identified to be recovered to be normal, informing the lower-level clock chip to cancel the Holdover state or canceling the target clock chip to cancel the Holdover state, and enabling the target clock chip to receive an external clock source signal.
As shown in fig. 3, the system architecture in this embodiment may be a multi-level clock chip, the clock chip 2 is the next level clock chip of the clock chip 1, the clock chip 1 receives the external clock source signal 1 and the external clock source signal 2, and the frequencies of the external clock source signal 1 and the external clock source signal 2 are different. In other embodiments, it may be a single-level clock chip, i.e. only clock chip 1 is present.
In step S201, the state of the external clock source accessing the target clock chip may be monitored by the management module, for example, the state of the interface receiving the external clock source signal 1 and the state of the interface receiving the external clock source signal 2 of the clock chip 1, such as jitter, noise, delay, and packet loss, is monitored by the management module, and when the state of the interface recognizes that the state of the interface receiving the external clock source signal has jitter or noise exceeding a threshold value, the management module may determine that the abnormality exists in the receiving the external clock source signal by the clock chip 1.
In this embodiment, when it is determined that there is an abnormality in the external clock source signal received by the clock chip, two processes may be performed, one of which, when it is applied in the case that there is a multilevel clock chip, as shown in fig. 3, it is assumed that there is an abnormality in the external interface clock source 1, at this time, the clock chip 1 determines that there is a lower clock chip 2, at this time, the clock chip 1 notifies the clock chip 2 to be placed in the Holdover state, and at the same time, the clock chip 1 switches the external interface clock source 2, so that, because the clock chip 1 notifies the clock chip 2 to be placed in the Holdover state before switching the external interface clock source 2, and breaks down the clock signal transmission between the clock chip 1 and the clock chip 2, the clock chip 2 will not receive the influence of the oscillation generated in the switching process of the clock chip 1, and still can provide a stable clock signal for the downstream device, and after the clock chip 1 completes the clock source switching process, the clock chip 1 notifies the clock chip 2 to cancel being placed in the Holdover state and receive the clock signal provided by the clock chip 1.
In another case, when only one stage of clock chip exists, when the abnormality of the external interface clock source 1 is identified, the external interface clock source 1 can be placed in the hold over state at this time, then the external interface clock source is switched, and after the switching is completed, the hold over state of the external interface clock source is canceled.
In this embodiment, when all external clock sources of the clock chip fail, a local clock source signal can be provided for the clock chip by using a local clock crystal oscillator signal.
According to the embodiments, when the abnormal state of the external clock source is detected, the clock chip can be placed in the hold over state, and when the lower clock chip exists, the lower clock chip can be indicated to be placed in the hold over state, so that the clock chip can output a stable clock signal under the condition of jitter of the external clock source, and the condition of service interruption of equipment is prevented.
The embodiment of the disclosure also provides a network device, which includes: clock chip and monitoring module
The monitoring module is used for monitoring the state of an external clock source accessed to the clock chip;
the clock chip is used for monitoring the abnormal state notification of the external clock source sent by the module, judging whether a lower clock chip exists, if so, notifying the lower clock chip to be in a Holdover state, and if not, placing the target clock chip in the Holdover state;
the clock chip is also used for receiving the external clock source state recovery notice sent by the monitoring module, notifying the lower-level clock chip to cancel the Holdover state or canceling the target clock chip from the Holdover state, and enabling the target clock chip to receive the external clock source signal.
The monitoring module is used for monitoring the state of an interface receiving an external clock source signal.
The monitoring module is used for determining that the state of the external clock source is abnormal when the condition of the interface receiving the external clock source signal is monitored to shake or noise exceeds a threshold value.
The clock chip is further used for acquiring a local clock crystal oscillator signal when the state of the external clock source is abnormal.
And after receiving the notification of the recovery of the external clock source state sent by the monitoring module, the clock chip switches from acquiring the local clock crystal oscillator signal to acquiring the external clock source signal.
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.
It is to be understood that the present description is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims (11)

1. A method of clock switching, the method comprising:
monitoring the state of an external clock source accessed to a target clock chip;
when the state of the external clock source is abnormal, judging whether a lower-level clock chip exists, if so, informing the lower-level clock chip to be in a Holdover state, and if not, putting the target clock chip to be in the Holdover state;
when the external clock source state is identified to be recovered to be normal, the lower clock chip is informed to cancel the Holdover state or the target clock chip is informed to cancel the Holdover state, and the target clock chip is enabled to receive an external clock source signal.
2. The method of claim 1, wherein monitoring the external clock source state of the access clock chip comprises:
the state of an interface receiving an external clock source signal is monitored.
3. The method of claim 2, wherein the external clock source state anomaly is determined when a jitter or noise exceeding a threshold is monitored in an interface state of the received external clock source signal.
4. The method of claim 1, wherein when the external clock source state is abnormal, the method further comprises:
the clock chip acquires a local clock crystal oscillator signal.
5. The method of claim 1, wherein notifying the lower level clock chip to be placed in the Holdover state further comprises:
disconnecting clock signal transmission of the target clock chip and the lower clock chip;
when the state of the external clock source is identified to be recovered to be normal, the method further comprises the following steps:
and recovering clock signal transmission of the target clock chip and the lower-level clock chip.
6. The method of claim 1, wherein when the external clock source state is identified as returning to normal, the method further comprises:
the clock chip is switched from acquiring a local clock crystal oscillator signal to acquiring an external clock source signal.
7. A network device, the network device comprising: clock chip and monitoring module
The monitoring module is used for monitoring the state of an external clock source accessed to the clock chip;
the clock chip is used for monitoring the abnormal state notification of the external clock source sent by the module, judging whether a lower clock chip exists, if so, notifying the lower clock chip to be in a Holdover state, and if not, placing the target clock chip in the Holdover state;
the clock chip is also used for receiving the external clock source state recovery notice sent by the monitoring module, notifying the lower-level clock chip to cancel the Holdover state or canceling the target clock chip from the Holdover state, and enabling the target clock chip to receive the external clock source signal.
8. The network device of claim 7, wherein the network device,
the monitoring module is used for monitoring the state of an interface receiving an external clock source signal.
9. The network device of claim 8, wherein the network device,
the monitoring module is used for determining that the state of the external clock source is abnormal when the condition of the interface receiving the signal of the external clock source is monitored to generate jitter or noise exceeding a threshold value.
10. The network device of claim 7, wherein the network device,
the clock chip is also used for acquiring a local clock crystal oscillator signal when the state of the external clock source is abnormal.
11. The network device of claim 7, wherein the network device,
and after receiving the notification of external clock source state recovery sent by the monitoring module, the clock chip switches from acquiring the local clock crystal oscillator signal to acquiring the external clock source signal.
CN202310759853.2A 2023-06-26 2023-06-26 Clock switching method and network equipment Pending CN116886227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310759853.2A CN116886227A (en) 2023-06-26 2023-06-26 Clock switching method and network equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310759853.2A CN116886227A (en) 2023-06-26 2023-06-26 Clock switching method and network equipment

Publications (1)

Publication Number Publication Date
CN116886227A true CN116886227A (en) 2023-10-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310759853.2A Pending CN116886227A (en) 2023-06-26 2023-06-26 Clock switching method and network equipment

Country Status (1)

Country Link
CN (1) CN116886227A (en)

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