JPH0330541A - Loop type communication system - Google Patents

Abstract

PURPOSE:To suppress frame jitter and to reduce the generation of frame error by comparing the first clock extracted from received data with the second clock outputted from an oscillator, selecting the second clock when the abnormality of the oscillator is not detected and executing transmission to the next station. CONSTITUTION:An oscillator 33 outputs the clock to a frequency abnormality detecting part 21 and a selector 23. The frequency abnormality detecting part 21 compares the clock, which is extracted from the received data outputted from an optical/electric converting part 21, with the clock outputted from the oscillator 33. When the frequency of the clock from the oscillator 33 is extremely widely deviated in comparison with the extracted clock, otherwise, when the oscillator 33 breaks down and the clock is interrupted, the abnormality of the oscillator 33 is detected and the result of the detection is outputted to the selector 23. When the abnormality of the oscillator 33 is not detected by the detector 21, the selector 23 selects the clock from the oscillator 33 and when the abnormality is detected, the clock extracted from the received data is selected. Then, the selected clock is outputted to an electric/optical converter 35, parallel/serial converter 37 and timing control part 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a distributed clocking loop communication system.

(Prior Art) In recent years, 100M to 400MbpS class local network systems (LANs) have been developed that use optical fibers as transmission paths and enable video communication and high-speed terminal communication.

In a loop communication system, which is one type of LAN, a plurality of (n) stations are connected in a loop through a transmission path 3, as shown in FIG. One of the stations is control station (SVS) 1
-1, and the others are slave stations (US N) 1-2-1-
It is n.

The office has 5 private exchanges (PBX), an image codec, and a MAC
By connecting other LANs such as bridges and ATMs,
Can provide various application services.

As shown in Figure 6, if the transmission line 3 is duplexed, even if an abnormality occurs in the transmission line 3 or the station, the network will go down due to RAS functions such as switching the transmission line from the active system to the standby system and loopback. The network becomes more reliable.

The transmission line 3 has a frame 7 of 125 μsec shown in FIG.
The frame 7 is composed of a preamble 9, a frame synchronization pattern 11, and a C0NT/data section 13. The frame synchronization pattern 11 is an area for synchronizing frames, and the C0NT/data section 13
is an area consisting of a large number of time slots and loaded with data.

The control station 1-1 generates a clock synchronized with the wide area network, and generates a frame 7 of 125 μsec based on the clock.

At each station, a repeater regenerates and relays the received data, transfers the data to frame 7 after passing through the station logic section, and transmits it to the next station. Since this data transmission and reception uses the clock extracted from the received data, the entire loop becomes a network synchronized with the clock of the control station 1-1.

After passing through the station logic of a station, the clock is still used as a transmission means for the next station. Therefore, noise in the station logic section of each station and clock jitter caused by the repeater are accumulated each time the station passes. System functionality is affected more by accumulated jitter than by the error rate characteristics of a single repeater. Therefore, since the error rate characteristics deteriorate, the number of connected stations is limited when considering the functionality of the system.

Accumulation of such jitter can be prevented by a distributed clocking method in which an oscillator is provided in each station and the clock from this oscillator is transmitted to the next station.

In other words, the data received by the repeater is sent to the elastic buffer (
FIFO), and reading data is transmitted to the next station using the clock of the oscillator provided in the station. FI
Data jitter is absorbed by the FO, and the data is read out and transmitted using an oscillator clock with no fluctuations, so jitter only occurs within one span between stations and does not accumulate.

This distributed clocking method can be regarded as performing independent synchronization as a network.

In the distributed clocking method, each station has an oscillator, so even if the upstream station goes down and frame 7 is no longer sent to the local station, the local station still has the frame generation function.
The advantage is that frame 7 can be transmitted to downstream stations.

Applications of distributed clocking LANs are unknown, and it is thought that in the future it will be possible to use LANs as terminals.

However, in the distributed clocking method, if the accuracy of the oscillator of each station varies, or if the frequency difference becomes large due to a failure, the next frame cannot be transmitted before the next frame is transmitted to the next station. Timing may occur. In this case, the degree of preamble increase/decrease increases or the front or rear part of the frame is destroyed.

To prevent damage to the rear of the frame, it is necessary to add many preamble bits in advance.

Furthermore, in order to transmit excluding the front part of the next frame when the preamble becomes 0, a large number of frame synchronization patterns are inserted at the front part of the frame.

However, if the preamble becomes 0 and all frame synchronization patterns are destroyed during multi-station relay, a frame error will occur and the frame will become invalid.

Therefore, if the frequency of the oscillator clock of each station varies or if there is a failure, the number of preamble bits added to the frame increases or decreases, causing frame fluctuations and increasing frame jitter. . Furthermore, there is a problem in that frame errors frequently occur, making it impossible to perform normal communication.

(Problems to be Solved by the Invention) In the conventional distributed clocking system, when the frequency of the clock of the oscillator of each station varies or when a failure occurs,
There are problems in that frame jitter increases and frame errors occur frequently.

In view of the above problems, the present invention aims to:
It is an object of the present invention to provide a loop communication system that suppresses frame jitter and further reduces the occurrence of frame errors.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a loop communication system in which a plurality of stations are connected in a loop through a transmission path and each station communicates according to a predetermined clock. includes a clock extraction means for extracting a first clock from received data, an oscillator for outputting a second clock, and an abnormality for detecting an abnormality in the oscillator by comparing the first clock and the second clock. It is characterized by comprising a detection means and a selection means for selecting the second clock in normal times and selecting the first clock when an abnormality in the oscillator is detected by the abnormality detection means. .

(Function) In the present invention, in each station, the abnormality detection means compares the first clock extracted from the received data by the clock extraction means and the second clock output from the oscillator, and detects an abnormality in the oscillator. When the oscillator is not detected, the selection means selects the second clock, and when an abnormality in the oscillator is detected, the selection means selects the first clock and transmits to the next station. The frequency difference between the clocks of transmitted data does not become large. Therefore, the degree of preamble bit increase/decrease is determined only by the frequency accuracy between stations, so it becomes small, frame jitter is suppressed,
Furthermore, the occurrence of frame errors is reduced.

(Example) Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 shows the configuration of a distributed clocking control section of each station according to an embodiment of the present invention.

If an abnormality occurs in the active distributed clocking control unit, the standby distributed clocking control unit replaces the active one, but the configuration of the standby distributed clocking control unit is the same as the active distributed clocking control unit. It is the same as the section.

The optical/electrical converter (0/E converter) 15 converts the optical signal received from the optical fiber transmission line 3 into an electrical signal, and outputs the converted received data to the serial/parallel converter 17. Further, the extracted clock extracted from the received data is output to the serial/parallel converter 17, the counter 19, the frequency abnormality detector 21, the selector 23, and the timing controller 25.

The serial/parallel converter 17 converts the received data from serial data to parallel data using the extracted clock and outputs it to the decode 27, and also detects the frame synchronization pattern 11 (see FIG. 7) and outputs it to the timing controller 25. do.

The counter 19 counts the extracted clock and converts it into words.
The word clock is sent to the decode 27, and the write clock is sent to the elastic buffer (FIFO, First in
I'1rst out) Output to 29.

The decode 27 processes the received data input from the serial/parallel converter 17 using the word clock input from the counter 19 and outputs it to the FIFO 29.

The FIFO 29 receives data input using the write clock of the counter 19 and transfers it to the station logic section 3 using the read clock output from the timing control section 25.
Output to 1.

The station logic section 31 latches the input data, receives the data loaded in the frame 7, and passes the received data to the interface device in the station logic section 31.

The oscillator 33 includes the frequency abnormality detection section 21 and the selector 23
Outputs the clock to.

The frequency abnormality detection unit 21 detects the optical/electrical conversion unit 1 except for a state in which a clock is not extracted from received data (carrier disconnection).
The frequencies of the clock extracted from the received data outputted from the oscillator 5 and the clock outputted from the oscillator 33 are compared.

If the frequency of the clock of the oscillator 33 deviates significantly from the extracted clock, or if the oscillator 33 is broken and the clock is cut off, the frequency abnormality detection unit 21 detects the abnormality of the oscillator 33 and uses the result. It is output to the selector 23.

The selector 23 selects the clock from the oscillator 33 when the frequency abnormality detection section 21 does not detect an abnormality in the oscillator 33, and selects the clock extracted from the received data when the frequency abnormality detection section 21 detects an abnormality. do. Selector 23
converts the selected clock to the electrical/optical converter 35, normal/li!
It is output to the converter 37 and the timing controller 25.

The timing control section 25 creates a read clock and preamble insertion timing based on the clock input from the selector 23 and the frame synchronization detection signal input from the serial/parallel conversion section 17. The read clock is output to the encoder 39, and the FIFO 29 is also read. The preamble insertion timing is output to the preamble bit generation section 41.

The encoder 39 encodes the data output from the station logic section 31 and outputs it to the parallel/direct converter 37 .

The parallel/direct converter 37 converts the parallel data input from the encoder 39 into serial data and outputs the serial data to the selector 43.

The preamble generating section 41 generates a preamble according to the preamble insertion timing inputted from the timing control section 25 and outputs it to the selector 43 . At this time, the preamble generator 41 generates and transmits a preamble until the frame synchronization pattern 11 is detected from the received data. After the frame synchronization pattern 11 is detected, no preamble is generated.

The selector 43 selects the preamble input from the preamble generator 41 or the data input from the parallel/direct converter 37 and outputs it to the electrical/optical converter 35 as transmission data.

The electrical/optical converter 35 outputs the transmission data from the selector 43 to the transmission line 3 using the transmission clock from the selector 23.

As described above, the reading of received data from the FIFO 29, the generation of a preamble by the preamble generator 41, and the transmission of transmission data are normally performed using the clock from the oscillator 33.

If an abnormality occurs in the oscillator 33, the clock extracted from the received data is used. Therefore, there is no difference in tarock frequency between the local station and the next station, and the preamble bits do not increase or decrease between these stations.

Therefore, frame jitter can be suppressed and frame errors do not occur.

Since it is unlikely that an abnormality occurs in the oscillators 33 of all stations, the number of stations that use the clock extracted from the received data to be regenerated and relayed as a transmitting means is limited. Therefore, increase in frame jitter and occurrence of frame errors are suppressed.

FIG. 2 shows the oscillator 33 and frequency abnormality detection section 2 shown in FIG.
1 and a circuit diagram of the selector 23.

The frequency abnormality detection section 21 includes a phase comparator 45, a comparator 53, an AND gate 47, an AND gate 49, and an ant gate 51, and the selector includes an OR gate 57.

The extracted clock extracted from the received data is sent to the phase comparator 4.
5. Input to AND gate 47 and AND gate 49.

The clock output from the oscillator 33 is sent to the phase comparator 45.
and is input to the AND gate 51.

The phase comparator 45 converts the frequency difference between the frequency fO of the extracted clock and the frequency fl of the oscillator 33 into a phase difference, and outputs a voltage corresponding to the phase difference to the comparators 53 and 55.

The reference voltage of comparator 53 is Vrefl. When the voltage input to the comparator 53 is higher than the reference voltage VreH, "0" is output to the AND gate 47 and the AND gate 51, and "0" is output to the AND gate 49. When the manually input voltage is smaller than the reference voltage VreN, "1" is set to the AND gate 47.
and "0" in AND gate 51 and AND gate 49
is output to.

The reference voltage of the comparator 55 is ■rer2. When the voltage input to the comparator 55 is higher than the reference voltage ■rer2, "1" is output to the AND gate 49 and the AND gate 51, and "0" is output to the AND gate 47. When the input voltage is smaller than the reference voltage Vrer2, “0” is output to the AND gate 49 and the AND gate 51, and “1” is output to the AND gate 47.

The AND gate 47 is configured so that the human power from the comparator 53 is "
1", and when the input from the comparator 55 is "1", the extracted clock is output to the OR gate 57. If the input from comparator 53 or comparator 55 is
0'', the extraction clock is cut off.

The AND gate 49 is configured so that the human power from the comparator 53 is “
1", and when the input from the comparator 55 is "1", the extracted clock is output to the OR gate 57. If the input from comparator 53 or comparator 55 is
0'', the extraction clock is cut off.

The AND gate 51 is configured so that the input from the comparator 53 is "
1", and when the input from the comparator 55 is "1", the clock of the oscillator 33 is output to the OR gate 57. When the input from comparator 53 or comparator 55 is "0", the clock of oscillator 33 is cut off.

OR gate 57 is AND gate 47, AND gate 4
9 and the output of the ant gate 51, and either the extracted clock or the clock of the oscillator 33 is selected and output as the transmission clock.

Next, the operations of the frequency abnormality detection section 21 and the selector 23 will be explained in detail using FIG.

As shown in FIG. 3, the upper limit of the frequency f1 of the clock of the oscillator 33 allowed for the frequency fO of the extracted clock is f2, and the lower limit is f3. moreover,
The output of the phase comparator 45 indicating the frequency f2 is VrerL, and the output of the phase comparator 45 indicating the frequency f3 is Vrel'2. When the frequency fO of the extracted clock and the frequency f1 of the clock of the oscillator 33 are the same, the output of the phase comparator 45 is Vopt. The allowed frequencies ±Δf correspond to voltage amplitudes ±ΔV.

A case will be described in which the oscillator 33 is normal and the frequency f1 of the clock of the oscillator 33 is between the upper limit frequency f2 and the lower limit frequency f3.

Since the voltage input to the comparator 53 is smaller than the reference voltage V r c f'l, the output is "1",
The inverted output becomes "0".

Since the voltage input to the comparator 55 is higher than the reference voltage Vref2, the output is "1" and the inverted output is "0".

That is, since "1" is input to the AND gate 51 from the comparators 53 and 55, the clock of the oscillator 33 is output.

Since "1" is input to the AND gate 47 from the comparator 53 and "0" from the comparator 55, the extraction clock is cut off.

Since "0" is input from the comparator 53 and "1" from the comparator 55 to the AND gate 49, the extraction clock is cut off.

Therefore, the clock of the oscillator 33 from the AND gate 51 is output from the OR gate 57.

A case will be described in which the oscillator 33 is abnormal and the frequency fl of the clock of the oscillator 33 is higher than the upper limit frequency f2.

Since the voltage input to the comparator 53 is higher than the reference voltage Vref'l, the output is "0" and the inverted output is "1".

Since the voltage input to the comparator 55 is higher than the reference voltage vref'2, the output is "1" and the inverted output is "0".

That is, since "1" is inputted to the AND gate 49 from the comparator 53 and the comparator 55, the extracted clock is outputted.

Since "0" is input to the AND gate 47 from the comparators 53 and 55, the extraction clock is cut off.

Since "0" is input from the comparator 53 and "1" from the comparator 55 to the AND gate 51, the clock of the oscillator 33 is cut off.

Therefore, the clock extracted from the AND gate 49 is output from the OR gate 57.

A case will be described in which the oscillator 33 is abnormal and the clock frequency fl of the oscillator 33 is smaller than the lower limit frequency f3.

Since the voltage manually applied to the comparator 53 is smaller than the reference voltage VreN, the output is "1" and the inverted output is "0".

Since the voltage input to the comparator 55 is smaller than the reference voltage Vre['2, the output is "0" and the inverted output is "1".

That is, since "1" is input to the AND gate 47 from the comparator 53 and the comparator 55, the extracted clock is output.

Since "1" is input from the comparator 53 and "0" from the comparator 55 to the AND gate 51, the clock of the oscillator 33 is cut off.

Since "0" is input to the AND gate 49 from the comparators 53 and 55, the extraction clock is cut off.

Therefore, the clock extracted from the AND gate 47 is output from the OR gate 57.

That is, the output of the phase comparator 45 is
When the reference voltage of the oscillator 33 is lower than the reference voltage Vrer2 and when the reference voltage of the comparator 53 is higher than the reference voltage Vrer1, it is determined that the frequency accuracy of the oscillator 33 has deteriorated or that the oscillator 33 has failed, and the oscillator 3
The clock from 3 is cut off, and the selector 23 extracts the received data and outputs it.

FIG. 4 shows another oscillator, frequency abnormality detection section, and selector circuit.

Phase comparator 73, low pass filter 75 and voltage controlled crystal oscillator (VCXO, Voyage Contr
.

I X'tal 0scillator) 77 to P
An LL circuit 59 is configured.

In this embodiment, a VCXO 77 is used as an oscillator.

Since the oscillation frequency of the VCXO77 changes depending on its control voltage, by monitoring the control voltage of the VCXO77, the VC
An abnormality in XO77 is detected.

The extracted clock extracted from the received data is sent to the phase comparator 7.
3. Input to AND gate 67 and AND gate 69.

The clock output from the VCXO 77 is sent to the phase comparator 7.
3 and input to AND gate 65.

The phase comparator 73 compares the extracted clock frequency fO and VCX.
Replace the frequency difference of the frequency f1 of O77 with a phase difference, output a voltage according to the phase difference to the low-pass filter 75,
The signal is output from the low-pass filter 75 to the comparator 61 and the comparator 63.

The reference voltage of comparator 61 is Vrefl. When the voltage input to the comparator 61 is higher than the reference voltage vref'l, "0" is output to the AND gate 65 and the AND gate 67, and "1" is output to the AND gate 69. When the input voltage is smaller than the reference voltage Vref'l, "1" is output to AND gate 65 and AND gate 67, and "0" is output to AND gate 69.

The reference voltage of the comparator 63 is vref'2. When the voltage input to the comparator 63 is higher than the reference voltage Vrel' 2, "1" is output to the AND gates 65 and 69, and "0" is output to the AND gate 67. When the input voltage is smaller than the reference voltage Vrel'', 2, ``0'' is output to the AND gates 65 and 69, and ``1'' is output to the AND gate 7.

The AND gate 67 is configured so that the input from the comparator 61 is “
1", and when the input from the comparator 63 is "1", the extracted clock is output to the OR gate 71. If the human power from comparator 61 or comparator 63 is
0'', the extraction clock is cut off.

The AND gate 69 is configured so that the input from the comparator 61 is “
1", and when the input from the comparator 63 is "1", the extracted clock is output to the OR gate 71. The input from comparator 61 or comparator 63 is
0'', the extraction clock is cut off.

The AND gate 65 uses the human power from the comparator 61 as "
1", and when the input from the comparator 63 is "1", the clock of the VCXO 77 is output to the OR gate 71. When the input from comparator 61 or comparator 63 is "0", the clock of VCXO 77 is cut off.

OR gate 71 is AND gate 65, AND gate 6
7 and the output of the ant gate 69, and either the extracted clock or the clock of the VCXO 77 is selected and output as the transmission clock.

As shown in FIG. 3, the upper limit frequency of the allowable clock frequency f1 of the VCXO 77 relative to the extracted clock frequency fO is f2, and the lower limit frequency is f3. Furthermore, the output of the phase comparator 45 indicating the frequency f2 is Vrcfl
, the output of the phase comparator 45 indicating the frequency f3 is V ref
'2.

A case will be described in which the VCXO 77 is normal and the frequency fl of the clock of the VCXO 77 is between the upper limit frequency f2 and the lower limit frequency f3.

Since the voltage input to the comparator 61 is smaller than the reference voltage VreH, the output is "1" and the inverted output is "0".

Since the voltage input to the comparator 63 is higher than the reference voltage vrer2, the output is "1" and the inverted output is "0".

That is, since "1" is input to the AND gate 65 from the comparator 61 and the comparator 63, V
The clock of CXO77 is output.

Since "1" is input from the comparator 61 and rOJ is input from the comparator 63 to the AND gate 67, the extraction clock is cut off.

Since rOJ is manually input to the AND gate 69 from the comparator 61 and "1" is input from the comparator 63, the extraction clock is cut off.

Therefore, the clock of VCXO 77 from AND gate 65 is output from OR gate 71 .

A case will be described in which the VCXO 77 is abnormal and the frequency f1 of the clock of the VCXO 77 is higher than the upper limit frequency f2.

Since the voltage input to the comparator 61 is higher than the reference voltage Vref'l, the output is "0" and the inverted output is "1".

Since the voltage input to the comparator 63 is higher than the reference voltage Vref2, the output is "1" and the inverted output is "0".

That is, since "1" is manually inputted to the AND gate 69 from the comparator 61 and the comparator 63, the extracted clock is output.

Since "0" is manually input to the AND gate 67 from the comparator 61 and "0" from the comparator 63, the extraction clock is cut off.

Since "0" is input from the comparator 61 and "1" from the comparator 63 to the AND gate 65, the VC
The clock of XO77 is cut off.

Therefore, the clock extracted from the AND gate 69 is output from the OR gate 71.

A case in which the VCXO77 (7) has an abnormal tear and the frequency fl of the VCXO77 (7) clock is smaller than the lower limit frequency f3 will be described.

Since the voltage input to the comparator 61 is smaller than the reference voltage VreN, the output is "1" and the inverted output is "0".

Since the voltage input to the comparator 63 is smaller than the reference voltage Vref2, the output is rOJ and the inverted output is "1".

That is, since "1" is input to the AND gate 67 from the comparator 61 and the comparator 63, the extracted clock is output.

The AND gate 65 receives "1" from the comparator 61 and rOJ from the comparator 63, so the VC
The clock of XO77 is cut off.

Since "0" from the comparator 61 and rOJ from the comparator 63 are input to the AND gate 69, the extraction clock is cut off.

Therefore, the OR gate 71 outputs the extracted clock from the AND gate 67.

That is, when the output of the low-pass filter 75 is equal to or less than the reference voltage Vrer2 of the comparator 63 and when the reference voltage Vref'1 of the comparator 61
If this is the case, it is determined that the frequency accuracy of the VCXO 77 has deteriorated or that the VCXO 77 has failed, the clock from the VCXO 77 is cut off, and the OR gate 71 outputs a clock extracted from the received data.

FIG. 5 shows still another oscillator, frequency abnormality detection section, and selector circuit.

The circuit of this embodiment includes an AND gate 79, an inverter 8
1, a first selection circuit 83, a second selection circuit 85, an AND gate 87, an AND gate 89, and an OR gate 91.

The first selection circuit 83 and the second selection circuit 85
This is the same circuit as shown in the figure.

That is, the first selection circuit 83 includes the first oscillator 93,
Phase comparator 95, comparator 97, comparator 99
, an AND gate 101, an AND gate 103, an AND gate 105, and an OR gate 107.
The selection circuit 85 includes the second oscillator 109 and the phase comparator 1.
11, comparator 113, comparator 115, AND gate 117, AND gate 119, AND gate 1
21 and the OR gate 123.

The AND gate 79 outputs the extracted clock to the first selection circuit 83 when the clock disconnection detection signal is "1",
When the clock cutoff detection signal is "0", the extracted clock is cut off.

The inverter 81 outputs the inverted output of the clock l$I'r (No. 5) to the AND gate 89.

The first selection circuit 83, like the circuit shown in FIG. , selects the clock of the first oscillator 93, and selects the clock of the first oscillator 93.
When the oscillator 93 is abnormal, the extracted clock is selected and output to the AND gate 87.

Similar to the circuit shown in FIG. 3, the second selection circuit 85 compares the tarock of the first oscillator 93 and the clock of the second oscillator 109. 1
When the first oscillator 93 is abnormal, the clock of the second oscillator 109 is selected and output to the AND gate 89.

AND gate 87 outputs the output of OR gate 107 to OR gate 91 when the clock loss detection signal is "1", and cuts off the output of OR gate 107 when the clock 1 analysis detection signal is "0". .

When the output of the inverter 81 is "1", the AND gate 89 outputs the output of the OR gate 123 to the offer-) 91, and when the output of the inverter 81 is "0", cuts off the output of the OR gate 123. do.

OR gate 91 selects and outputs the output of AND gate 87 or AND gate 89.

Next, the operation of this circuit will be explained.

When there is an extracted clock, a clock interruption detection signal “1” is input to the AND gate 79, and the extracted clock is output from the AND gate 79 to the first selection circuit 83.

The first selection circuit 83 selects the clock of the first oscillator 93 when the first oscillator 93 is normal, and selects the extracted clock when the first oscillator 93 is abnormal. Output to. AND gate 87 outputs the output of OR gate 107 to OR gate 91 because the clock interruption detection signal is “1”.

The second selection circuit 85 selects the clock of the first oscillator 93 or the clock of the second oscillator 109 from the AND gate 8
Output to 9. However, the clock loss detection signal is
1", the output "0" of the inverter 81 is output to the AND gate 89, and the output of the second selection circuit 85 is cut off by the AND gate 89.

Therefore, from the OR gate 91, the first selection circuit 83
output is selected.

When the extracted clock is off, the clock off detection signal “0” is input to the AND gate 79, and the extracted clock is not output to the first selection circuit 83.

Therefore, from the first selection circuit 83, the first oscillator 9
The clock of the first oscillator 93 is output to the AND gate 87, but since the clock loss detection signal "0" is output to the AND gate 87, the clock of the first oscillator 93 is output to the AND gate 87.
It is blocked by

The second selection circuit 85 compares the clock of the first oscillator 93 or the clock of the second oscillator 109, and selects the clock of the first oscillator 93 when the first oscillator 93 is normal; When the first oscillator 93 is abnormal, the tarok of the second oscillator 109 is selected and output to the AND gate 89.

Since the clock disconnection detection signal is "0", inverter 8
Since the output "1" of 1 is output to the AND gate 89, the output of the second selection circuit 85 is output from the AND gate 89 to the OR gate 91.

Therefore, from the OR gate 91, the second selection circuit 85
output is selected.

Thus, when the extracted clock is not interrupted, the extracted clock selected by the first selection circuit 83 or the clock of the first oscillator 93 is used as the transmission clock, and when the extracted clock is interrupted, the second The first oscillator 93 or the second oscillator 109 selected by the selection circuit 85 of
clock is used as the transmit clock.

In this circuit, when the extracted clock is disconnected, the second selection circuit 85 selects the clock of the oscillator with the frequency closest to the extracted clock from among the clocks of the first oscillator 93 or the second oscillator 109. be able to. As a result, clocks on the transmission path with almost the same frequency accuracy can be used for the transmitting means.

Note that in Figure 5, the outputs of the phase comparators are compared using a comparator, but it is also possible to perform phase comparison digitally, detect the output with a counter, detect frequency abnormalities, and select a clock. can.

Further, when the clock is cut off, the tarocks of two oscillators are compared, but three or more oscillators may be compared and the oscillator with the least variation in frequency may be selected.

In these embodiments described above, the distributed clocking control section including the frequency anomaly detection section can also be implemented as a chip.

Furthermore, in these embodiments, if 100 to 200 bits of preamble 9 are inserted in advance into the frame format shown in FIG. 7, the oscillator clock of each station will have a frequency difference of about ±30 ppm from the extracted clock. However, even after 500 stations have passed, the preamble 9 changes by only about 100 bits. Therefore, the preamble 9 becomes 0 and no frame error occurs. That is, it becomes possible to connect more than 500 stations.

Furthermore, in the frame format shown in FIG.
If the time slots of the NT data section 13 are continued, even if the frame synchronization pattern is destroyed due to a transmission line error, synchronization can be achieved using other frame synchronization patterns. Furthermore, if n frame synchronization patterns are used (n is 3 or more) and frame synchronization is achieved when n or more or n-1 or more frame synchronization patterns match, then the probability of incorrect synchronization is very small and can be ignored. can.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a loop communication system in which frame jitter is suppressed and frame errors are less likely to occur.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of the distributed clocking control section of the station according to the embodiment of the present invention, FIG. 2 is a diagram showing the circuits of the oscillator, frequency abnormality detection section, and selector, and FIG. 4 is a diagram showing the circuit of another oscillator, frequency abnormality detection section and selector, FIG. 5 is a diagram showing the circuit of another oscillator, frequency abnormality detection section and selector, and FIG. 6 is a diagram showing the relationship. FIG. 7 is a diagram showing the configuration of the loop communication system, and FIG. 7 is a diagram showing the frame format. 15... Optical/electric conversion section, 21... Frequency abnormality detection section, 23... Selector, 33... Oscillator Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] In a loop communication system in which a plurality of stations are connected in a loop through a transmission path and each station communicates according to a predetermined clock, each station has the following steps: extracting a first clock from received data. a clock extraction means; an oscillator that outputs a second clock; an abnormality detection means that compares the first clock and the second clock to detect an abnormality in the oscillator; is selected, and when an abnormality in the oscillator is detected by the abnormality detection means, the first
1. A loop communication system comprising: selection means for selecting a clock.