CN104104559A - E1 bit-error tester system - Google Patents
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Abstract
The invention introduces an E1 bit-error tester system. A module and a method for achieving the function of an E1 bit-error tester are integrated into an E1 device, and a wed interface is used for displaying test result, setting working parameters of the bit-error tester and the like. In an uplink, an E1 signal generating module is mainly used for generating E1 signals and sending to an E1 signal interface. In a downlink, a local sequence synchronization module receives the E1 signals and performs synchronous detection on the E1 signals according to a frame header; a sequence comparison and bit-error statistic module performs bit-error and alarm detection on the synchronous E1 signals and the original E1 signals, displaying the detected bit-errors, alarm signals and the like on a webpage after being processed by an CPU and the web. The bit-error tester device achieved by the above method does not need peripheral hardware circuits, is reduced in complexity of design, and meanwhile can achieve improved work efficiency and reduced cost in engineering and bulk production.
Description
Technical field
The present invention relates to a kind of E1 Error Detector system, the module and the method that realize E1 Error Detector function are integrated in E1 equipment, by web interface display test result, and running parameter of Error Detector etc. is set.Be mainly used in the communications field.
Background technology
Be accompanied by developing rapidly of Internet, in next generation network, the mode of carrying out network data transmission and exchange taking packet as elementary cell will occupy dominant position.But the E1 circuit that the existing PDH network of serving the public voice communication service of PSTN provides also will long-term existence.
In the performance test of digital communication system, conventionally use E1 error analyzer to measure the error performance of E1.Although having, it is simple and easy to, error code testing visual result abundant with, content measurement, the advantage such as accurate,, E1 error analyzer is expensive, is difficult for and some system interface adaptation, conventionally need to separately add outer secondary and encourage line drive circuit.In the time that the equipment that contains E1 business is produced in enormous quantities, if directly use Error Detector, need to consume great amount of cost, waste resource, and in the time that engineering is used, carrying for a long time Error Detector also can be very inconvenient.The a large amount of kernel control chips of FPGA/ASIC as system that adopt in communication system at present, the function of the various protocol layer in physical layer is concentrated on to the inner realization of FPGA/ASIC, not only improve the integrated level of communication system, also reduced the design complexities of hardware and software simultaneously.
Summary of the invention
In order to address the above problem, the present invention is integrated in E1 error code testing function in E1 equipment, by web interface display test result, and running parameter of Error Detector etc. is set, without mounting software, conveniently check test result, reduce equipment investment cost, increase work efficiency.
The present invention proposes a kind of E1 Error Detector system.Fully use existing E1 device hardware resource, (main alarm type has LOF, AIS to realize the alarm type of E1, pattern step-out, OOF, error code and frame count) and Error detection, improve the operating efficiency of batch production and engineering, convenient while making engineering opening and investigation problem.
Realize technical scheme of the present invention as follows:
A kind of E1 Error Detector system, comprises FPGA, CPU, web and display module; Web and display module comprise the web module and the display module that link together; CPU is connected with FPGA, web module bi-directional data respectively; Described FPGA comprises E1 signal generation module, local sequence synchronization module, sequence comparison and Bit Error Code Statistics module; E1 signal generation module is connected by E1 signaling interface with local sequence synchronization module, and sequence comparison and Bit Error Code Statistics module are connected with local sequence synchronization module, CPU respectively; Web module: send control command to CPU, CPU receives after control command, sends to FPGA by bus, the each module in FPGA is carried out corresponding action according to the control command receiving;
E1 signal generation module: generate 256bitE1 signal, front 8bit is as E1 frame head, after 248bit by m sequence generation;
Local sequence synchronization module: carry out frame head and synchronously detect, each continuous detecting 3 frames of odd even frame head; After the frame sum of synchronous and step-out add up, be sent to CPU by bus, synchronous E1 signal afterwards outputed to sequence comparison and Bit Error Code Statistics module detects simultaneously;
Sequence comparison and Bit Error Code Statistics module: synchronous E1 signal and the original E1 signal of local sequence synchronization module input are compared, judge number and the alarm type of error code; Export the alarm error code detecting and the frame number of statistics to CPU by bus; CPU receives error code and alarm data by bus, then by the form of error code and alarm composition message frame, by sharing storage by Data Update, carries out real-time query for web and display module;
Display module: the value inquiring is shown on webpage, realizes web Presentation Function.
Described E1 signal generation module produces E1 signal at random by 15 grades of scramblers.
Described local sequence synchronization module, because E1 frame is alternately transmission of parity frame, when so conducting frame head detects, to carry out continuously kind of the synchronous regime monitoring of 6 frame detection-6, until all detect for 6 times and synchronously think that the E1 frame receiving is frame synchronization, otherwise be step-out, the detailed process of every frame being carried out to the synchronous detection of frame head is:
The synchronous detection of frame head is divided into 6 kinds of states and detects; Be all that the frame head of E1 is detected detecting while having or not error code, thereby judge for step-out or synchronous;
In A synchronous regime, detect whether synchronous, if detect have error code; think asynchronous, enter into B synchronous protection state, if detect without error code continue detect in A synchronous regime;
At B synchronous protection state, if detected without error code, think synchronous, enter A synchronous regime, proceed A synchronous regime and detect; Detecting that error code enters C synchronous protection state;
At C synchronous protection state, if detected without error code, think synchronous, proceed A synchronous regime and detect; If error code detected, jump to D desynchronizing state;
At D desynchronizing state, detect and verification, think step-out if any error code, be now judged as OOF; If in OOF state-detection to frame without error code; jump to E search test status;
At E search test status, if there is error code, send to D desynchronizing state, be judged to be OOF;
If detected without error code, enter F search test status;
At F search test status, if inspection has error code, send to D desynchronizing state, be judged to be OOF;
If inspection is without error code, is frame synchronization, enter A synchronous regime, be judged to be frame synchronization.
The detailed process that described E1 signal generation module generates E1 signal is:
According to the requirement of standard E1 signal, in multi-frame structure, there is dividing of odd even, first slot transmission frame swynchronization code of even frame, is " 10011011 "; Very first slot transmission of frame, to accusing code, is " 11111111 ", and first time slot that this module produces parity frame according to E1 standard signal is as frame head, and 248bit data division is afterwards by m sequence generation;
Utilize m sequence generation data, take out the data of odd even part; The clock using, for the clock of the 2.048M of phase-locked loop generation, starts to count in the time detecting that systematic reset signal is drawn high, and produces at first the frame head of even frame at counting, for generating the even frame part of E1 signal, produces the mark of even frame afterwards simultaneously; Being sent completely the frame head that even frame produces strange frame afterwards, is then to utilize the data that m sequence generates to send as the strange frame of E1 signal, produces the mark of strange frame simultaneously; Then by parity flag signal, data are alternately sent to E1 signaling interface with the form of parity frame.
The specific works process of described local sequence synchronization module comprises:
Receive E1 signal and clock that E1 signaling interface sends, adopt the clock of high power clock docking port signal to sample, E1 signal is write to FIFO, in E1 interface clock rising edge, produce writing of FIFO and enable; The enable pass of reading of FIFO is crossed the E1 signal number of storing in FIFO and is read empty mark generation, will after data output, go here and there and change; By go here and there and change after data by state machine, frame head is carried out to parity frame verification and produces parity flag simultaneously, the parity flag detecting is sent to sequence comparison and Bit Error Code Statistics module; The E1 data that receive are carried out to frame synchronization and step-out verification simultaneously; The synchronous frame number detecting is added up the frame number counting on is sent to bus to CPU; And record current and mark historical frames step-out and send to bus to CPU; Synchronous E1 signal is sent to sequence comparison and Bit Error Code Statistics module.
The specific works process of described sequence comparison and Bit Error Code Statistics module comprises:
Receive the E1 signal on synchronously of local sequence synchronization module, according to parity flag by the then sense data of address sort in rom table; The data of reading in rom table are compared with the E1 signal on synchronizeing, by relatively judging whether the alarm of error code, AIS, dropout, pattern step-out, current alarm signal is saved in history alarm, count on historical alarm; Then various alarms are outputed to CPU by bus interface module, CPU communicates by letter with web and display module by sharing storage, and web and display module show alarm with the form of webpage, checks that by webpage alarm and error code are history or current.
Compared with prior art, the present invention has the following advantages and has beneficial effect:
1, test aspect, does not need to build complicated test platform, only need to, in the time starting to test, click Error Detector switch can test from web interface;
2, production cost aspect, in the time producing in batches, does not need a large amount of traditional Error Detectors, and on every equipment, itself just carries Error Detector, thereby can be cost-saving, in the time carrying out error code testing, can save the production time;
3, engineering aspect, does not need to carry heavy Error Detector, and only need in the time of engineering opening, click Error Detector switch from web interface can verify whether engineering is opened successfully; While searching problem for engineering, do not need again to set for this platform yet;
4, in price, do not need again to develop hardware, only need to be by software upgrading on original hardware platform, and the shared resource of software logic code is few, development cost and greatly saved cost;
5, development technique aspect, demonstration and the order of carrying out result by web issue, and do not need complicated operation, and directly click can be checked.
Brief description of the drawings
Fig. 1 (a) is for using the system architecture diagram of conventional E1 code error tester; Fig. 1 (b) is system architecture diagram of the present invention.
Fig. 2 is system architecture block diagram of the present invention.
Fig. 3 is the framework that function of the present invention realizes.
Fig. 4 is 15 grades of scrambler schematic diagrams.
Fig. 5 is synchronous regime preamble detecting flow chart.
Fig. 6 is E1 signal generation module flow chart.
Fig. 7 is local sequence synchronization module flow chart.
Fig. 8 is sequence comparison and Bit Error Code Statistics module flow chart.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Accompanying drawing 1 is to use the system of conventional E1 code error tester and this programme to be connected block diagram.Be illustrated with PTN microwave (band E1 dish) equipment the simplicity that this programme brings whole system.
The system architecture of PTN microwave is to be mainly made up of IDU and ODU, and in IDU, modulation /demodulation dish is connected with ODU by medium frequency electric cable; ODU is to communicate by letter by antenna transmission signal with ODU; Then one end ODU is connected with modulation /demodulation dish in IDU in addition.
In the conventional E1 code error tester of use is tested, except the basic IDU of needs and ODU equipment, also need to use E1 code error tester and E1 keyset.First, E1 dish need to be connected on E1 keyset with E1 patchcord, then the input and output on E1 keyset are connected on E1 code error tester with BNC connecting line, on the E1 keyset of the IDU of opposite end mono-side, carry out loopback, so just complete building of E1 error code testing system.
And use this programme while testing, and only need basic IDU and an ODU just can complete whole test, on E1 dish, the switch opens of E1 error code device can be carried out to E1 error code testing.And need to investigate if there is problem in engineering opening, not needing to carry in addition E1 code error tester and BNC connecting line, only the E1 error code commissioning switch opens carrying in E1 dish can need to be tested and investigation problem easily.From test and engineering use, can find the advantage of this programme.
Accompanying drawing 2 is system architectures of this programme, is mainly by FPGA/ASIC, CPU and web(webpage) composition.FPGA/ASIC mainly realizes the function of E1 error code device, and the error code detecting and alarm signal are sent to CPU by bus.CPU, after receiving error code and alarm signal, sends to error code and alarm signal by sharing storage the process of web module, is then shown in real time on web page.When the parameter of Error Detector is set on web page, web module is obtained web interface information by web list, then passes through message queue transmitting order to lower levels to CPU, and CPU sends to FPGA/ASIC by command information by bus by the mark of message queue.Thereby form a complete Error Detector device.
Accompanying drawing 3 has illustrated the framework that E1 Error Detector function realizes.In up link, E1 signal generation module is mainly to generate E1 signal to send to E1 signaling interface, can be then to arrive outside to E1 interface by E1 chip at this, also can be the FPGA/ASIC the inside at E1 single-deck itself, directly send to E1 interface module in FPGA/ASIC inside without E1 chip and use.On down link, local sequence synchronization module, receives the E1 signal that E1 interface sends, and carries out frame synchronization detection, and the synchronous frame number detecting and step-out frames statistic are sent to CPU by SPI interface; Sequence comparison and Bit Error Code Statistics module, complete Bit Error Code Statistics and alarm detection, the error code of generation and warning information sent to CPU by SPI interface by bus simultaneously.
Accompanying drawing 4 is 15 grades of scrambler schematic diagrams, and so-called scrambler, its essence is before digital signal is sent to channel, digital signal is carried out in bit-level to randomization, thereby can reduce shake and intersymbol interference, facilitates the Clock Extraction of receiving terminal.The most frequently used method is the maximum length linear shift register sequence that superposes on band signal transmission, makes the statistical property of signal be suitable for transmitting in corresponding channel.And m sequence can be obtained simply by what linear feedback shift register.The primitive polynomial of 15 grades of scramblers is X
15+ X+1, period of state is 2
15-1, as seen from the figure, register is output as b
k=a
k⊕ b
k-1⊕ b
k-15, wherein, K representative element number; b
krepresent Output rusults; a
krepresent input signal; ⊕: represent XOR.Carry out thus to produce at random E1 signal.
Accompanying drawing 5 is for receiving the synchronous regime preamble detecting of E1 signal.In the time of synchronous regime preamble detecting, being divided into 6 kinds of states and detecting, is all that the frame head of E1 is detected detecting in having or not error code, thereby judges for step-out or synchronous.Be synchronous regime at state A, whether synchronously detect, there is error code if detected, think asynchronous to B synchronous protection state, if without error code, think that synchronously proceeding A synchronously detects, until all detect for 6 times and synchronously think that the E1 frame receiving is frame synchronization; State B and C are synchronous protection state; detecting that error code arrives synchronous protection state; if through twice synchronous protection state-detection still detected that error code jumps to that D desynchronizing state detects under desynchronizing state and verification if any error code; think step-out; now be judged as OOF; if in OOF state-detection to frame without error code; jump to E search test status; carry out twice search inspection E; F state; if twice search checked all without error code, still think for frame synchronization; if there is error code, send to desynchronizing state, be judged to be OOF.
Accompanying drawing 6 is the flow process of E1 signal generation module.The m sequence data that utilizes 15 grades of scramblers to produce, the data of taking-up odd even part.Clock is the clock of the 2.048M of phase-locked loop generation as used herein.In the time detecting that systematic reset signal is drawn high, start to count, produce at first the frame head of even frame at counting, for generating the even frame part of E1 signal, produce the mark of even frame afterwards simultaneously; Being sent completely the frame head that even frame produces strange frame afterwards, is then to utilize the data that m sequence generates to send as the strange frame of E1 signal, produces the mark of strange frame simultaneously.Then by parity flag signal, data are alternately sent to the interface module of E1 signal with the form of parity frame.
Accompanying drawing 7 is local sequence synchronization module flow chart, receives E1 signal and clock that E1 interface module sends, adopts high power clock to sample to the clock of E1 interface signal, and E1 signal is write to FIFO.In E1 interface clock rising edge, producing writing of FIFO enables; The enable pass of reading of FIFO is crossed the E1 signal number of storing in FIFO and is read sky mark and produces, and will after data output, go here and there and change.By go here and there and change after data by state machine, frame head is carried out to parity frame verification and produces parity flag simultaneously, the parity flag detecting is sent to sequence comparison and Bit Error Code Statistics module; To carry out frame synchronization and step-out verification to the E1 data that receive simultaneously.The synchronous frame number detecting is added up the frame number counting on is sent to bus to CPU; And record current and mark historical frames step-out and send to bus to CPU.Now also need synchronous E1 signal to be sent to sequence comparison and Bit Error Code Statistics module.
Accompanying drawing 8 is sequence comparison and Bit Error Code Statistics module flow chart, receives the E1 signal on synchronously of local sequence synchronization module, according to parity flag by the then sense data of address sort in rom table.The data of reading in rom table are compared with the E1 signal on synchronizeing, by relatively having judged whether error code, AIS, dropout, the alarms such as pattern step-out, are saved in current alarm signal in history alarm, can count on historical alarm.Then various alarms are outputed to CPU by bus interface module, CPU is by sharing storage and web module communication, and web module is shown to alarm etc. above webpage, can check that by webpage alarm and error code are history or current.
Above-mentioned example is preferably execution mode of the present invention; but embodiments of the present invention are not subject to the restriction of above-mentioned example; other is any does not run counter to change, the modification done under Spirit Essence of the present invention and principle, substitute, combination, simplify and all should be equivalent substitute mode, within being included in protection scope of the present invention.
Claims (6)
1. an E1 Error Detector system, is characterized in that: comprise FPGA, CPU, web and display module; Web and display module comprise web module and display module; CPU is connected with FPGA, web module bi-directional data respectively; Described FPGA comprises E1 signal generation module, local sequence synchronization module, sequence comparison and Bit Error Code Statistics module; E1 signal generation module is connected by E1 signaling interface with local sequence synchronization module, and sequence comparison and Bit Error Code Statistics module are connected with local sequence synchronization module, CPU respectively;
Web module: send control command to CPU, CPU receives after control command, sends to FPGA by bus, the each module in FPGA is carried out corresponding action according to the control command receiving;
E1 signal generation module: generate 256bitE1 signal, front 8bit is as E1 frame head, after 248bit by m sequence generation;
Local sequence synchronization module: carry out frame head and synchronously detect, each continuous detecting 3 frames of odd even frame head; After the frame sum of synchronous and step-out add up, be sent to CPU by bus, synchronous E1 signal afterwards outputed to sequence comparison and Bit Error Code Statistics module detects simultaneously;
Sequence comparison and Bit Error Code Statistics module: synchronous E1 signal and the original E1 signal of local sequence synchronization module input are compared, judge number and the alarm type of error code; Export the alarm error code detecting and the frame number of statistics to CPU by bus; CPU receives error code and alarm data by bus, then by the form of error code and alarm composition message frame, by sharing storage by Data Update, carries out real-time query for web and display module;
Display module: the value inquiring is shown on webpage, realizes web Presentation Function.
2. a kind of E1 Error Detector system according to claim 1, is characterized in that: described E1 signal generation module produces E1 signal at random by 15 grades of scramblers.
3. a kind of E1 Error Detector system according to claim 1, it is characterized in that: described local sequence synchronization module, because E1 frame is alternately transmission of parity frame, when so conducting frame head detects, will carry out continuously 6 frame detection-6 kind of synchronous regime detects, until all detect for 6 times and synchronously think that the E1 frame receiving is frame synchronization, otherwise be step-out, every frame is carried out to the synchronous detailed process detecting of frame head be:
The synchronous detection of frame head is divided into 6 kinds of states and detects; Be all that the frame head of E1 is detected detecting while having or not error code, thereby judge for step-out or synchronous;
In A synchronous regime, detect whether synchronous, if detect have error code; think asynchronous, enter into B synchronous protection state, if detect without error code continue detect in A synchronous regime;
At B synchronous protection state, if detected without error code, think synchronous, enter A synchronous regime, proceed A synchronous regime and detect; Detecting that error code enters C synchronous protection state;
At C synchronous protection state, if detected without error code, think synchronous, proceed A synchronous regime and detect; If error code detected, jump to D desynchronizing state;
At D desynchronizing state, detect and verification, think step-out if any error code, be now judged as OOF; If in OOF state-detection to frame without error code; jump to E search test status;
At E search test status, if there is error code, send to D desynchronizing state, be judged to be OOF;
If detected without error code, enter F search test status;
At F search test status, if inspection has error code, send to D desynchronizing state, be judged to be OOF;
If inspection is without error code, is frame synchronization, enter A synchronous regime, be judged to be frame synchronization.
4. a kind of E1 Error Detector system according to claim 1, is characterized in that: the detailed process that described E1 signal generation module generates E1 signal is:
According to the requirement of standard E1 signal, in multi-frame structure, there is dividing of odd even, first slot transmission frame swynchronization code of even frame, is " 10011011 "; Very first slot transmission of frame, to accusing code, is " 11111111 ", and first time slot that this module produces parity frame according to E1 standard signal is as frame head, and 248bit data division is afterwards by m sequence generation;
Utilize m sequence generation data, take out the data of odd even part; The clock using, for the clock of the 2.048M of phase-locked loop generation, starts to count in the time detecting that systematic reset signal is drawn high, and produces at first the frame head of even frame at counting, for generating the even frame part of E1 signal, produces the mark of even frame afterwards simultaneously; Being sent completely the frame head that even frame produces strange frame afterwards, is then to utilize the data that m sequence generates to send as the strange frame of E1 signal, produces the mark of strange frame simultaneously; Then by parity flag signal, data are alternately sent to E1 signaling interface with the form of parity frame.
5. a kind of E1 Error Detector system according to claim 1, is characterized in that: the specific works process of described local sequence synchronization module comprises:
Receive E1 signal and clock that E1 signaling interface sends, adopt the clock of high power clock docking port signal to sample, E1 signal is write to FIFO, in E1 interface clock rising edge, produce writing of FIFO and enable; The enable pass of reading of FIFO is crossed the E1 signal number of storing in FIFO and is read empty mark generation, will after data output, go here and there and change; By go here and there and change after data by state machine, frame head is carried out to parity frame verification and produces parity flag simultaneously, the parity flag detecting is sent to sequence comparison and Bit Error Code Statistics module; The E1 data that receive are carried out to frame synchronization and step-out verification simultaneously; The synchronous frame number detecting is added up the frame number counting on is sent to bus to CPU; And record current and mark historical frames step-out and send to bus to CPU; Synchronous E1 signal is sent to sequence comparison and Bit Error Code Statistics module.
6. a kind of E1 Error Detector system according to claim 1, is characterized in that: the specific works process of described sequence comparison and Bit Error Code Statistics module comprises:
Receive the E1 signal on synchronously of local sequence synchronization module, according to parity flag by the then sense data of address sort in rom table; The data of reading in rom table are compared with the E1 signal on synchronizeing, by relatively judging whether the alarm of error code, AIS, dropout, pattern step-out, current alarm signal is saved in history alarm, count on historical alarm; Then various alarms are outputed to CPU by bus interface module, CPU communicates by letter with web and display module by sharing storage, and web and display module show alarm with the form of webpage, checks that by webpage alarm and error code are history or current.
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| CN104579821A (en) * | 2014-12-04 | 2015-04-29 | 中国人民解放军91655部队 | Method and device for detecting frame structure form of data frame of E1 link |
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| CN114710423A (en) * | 2022-04-07 | 2022-07-05 | 四川灵通电讯有限公司 | Error code testing method of data chain system |
| CN116455530A (en) * | 2023-06-20 | 2023-07-18 | 中星联华科技（北京）有限公司 | Error code instrument, code pattern generation method and device, electronic equipment and medium |
| CN116455530B (en) * | 2023-06-20 | 2023-11-03 | 中星联华科技（北京）有限公司 | Error code instrument, code pattern generation method and device, electronic equipment and medium |
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| CN104104559B (en) | 2018-05-15 |
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