CN116455530A - Error code instrument, code pattern generation method and device, electronic equipment and medium - Google Patents

Error code instrument, code pattern generation method and device, electronic equipment and medium Download PDF

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CN116455530A
CN116455530A CN202310730892.XA CN202310730892A CN116455530A CN 116455530 A CN116455530 A CN 116455530A CN 202310730892 A CN202310730892 A CN 202310730892A CN 116455530 A CN116455530 A CN 116455530A
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data
code
bit width
splicing
pattern data
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CN116455530B (en
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王壮
尹项托
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Zhongxing Lianhua Technology Beijing Co ltd
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Zhongxing Lianhua Technology Beijing Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
    • H04L1/244—Testing correct operation by comparing a transmitted test signal with a locally generated replica test sequence generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a code error meter, a code pattern generation method, a code pattern generation device, electronic equipment and a medium, and belongs to the technical field of electronics. The error code instrument includes: DDR, FPGA and digital-to-analog converter, the FPGA includes the splice module; the DDR is used for caching first code type data, the first code type data is second code type data which are repeatedly written, the data length of the second code type data and the data bit width of the error code instrument are in a non-integer multiple relation, and the data length of the first code type data is an integer multiple of the splicing bit width; the FPGA is used for reading the first code pattern data and sending the first code pattern data to the splicing module for data splicing; the splicing module is used for carrying out data splicing on the first code type data to obtain third code type data, and the data length of the third code type data is an integer multiple of the data bit width. The error code meter provided by the invention can write code pattern data with any length without being limited by the bit width of the data, and can output effective code pattern data.

Description

Error code instrument, code pattern generation method and device, electronic equipment and medium
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a code error meter, a code pattern generating method, a device, an electronic apparatus, and a medium.
Background
The error code meter is one kind of digital signal quality measuring instrument and is used mainly in detecting and calculating error code rate in digital communication system. Besides the commonly used code patterns, the error code meter generally needs to use a custom code pattern for some special situations, or sometimes the error code meter version is older, the code pattern is not updated in time, and the custom code pattern is also needed to be used for transition. Because the Data bit width of Double Data Rate synchronous dynamic random access memory (DDR SDRAM) in the error code meter is relatively wide, there are 256 bits or 512 bits. The length of custom patterns is therefore typically specified to be an integer multiple of the DDR data bit width, limiting the data length of custom pattern data, resulting in some special patterns being unrealizable due to the data length.
Disclosure of Invention
The invention provides a code error meter, a code pattern generation method, a device, electronic equipment and a medium, which are used for solving the problem that the data length of a custom code pattern used by the code error meter in the prior art is limited.
The invention provides an error code instrument, comprising: DDR, FPGA and digital-to-analog converter, the FPGA includes the splice module;
the DDR is used for caching first code type data, the first code type data is second code type data which are repeatedly written, the data length of the second code type data and the data bit width of the error code instrument are in a non-integer multiple relation, the data length of the first code type data is an integer multiple of the splicing bit width, and the splicing bit width is determined based on the data bit width;
the FPGA is used for reading the first code type data from the DDR, and sending the first code type data to the splicing module for data splicing;
the splicing module is used for carrying out data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, and the data length of the third code type data is an integer multiple of the data bit width;
the digital-to-analog converter is used for outputting the third code type data.
In some embodiments, the FPGA further comprises: a first FIFO memory and a second FIFO memory;
the first FIFO memory is used for caching the first code type data and sending the first code type data to the splicing module for data splicing;
the second FIFO memory is configured to buffer the third code type data, and send the third code type data to the digital-to-analog converter.
The invention provides a code pattern generation method, which comprises the following steps:
repeatedly writing second code type data of an error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and based on the splicing bit width and the data bit width, carrying out data splicing on the first code type data to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
In some embodiments, the performing data splicing on the first pattern data based on the splicing bit width and the data bit width includes:
determining fourth code pattern data which can be written into the error code instrument according to the data bit width in the first code pattern data;
determining fifth code pattern data based on the fourth code pattern data, wherein the fifth code pattern data is the code pattern data except the fourth code pattern data in the first code pattern data;
determining the data length of the spliced code pattern data based on the data length of the fifth code pattern data and the spliced bit width;
and performing data splicing on the fifth code pattern data based on the data length of the spliced code pattern data.
In some embodiments, the data length of the fifth pattern data is greater than or equal to the splice bit width and less than the data bit width.
The invention also provides a code pattern generating device, which comprises:
the processing module is used for repeatedly writing the second code type data of the error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and the generation module is used for carrying out data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
In some embodiments, the generating module is specifically configured to:
determining fourth code pattern data which can be written into the error code instrument according to the data bit width in the first code pattern data;
determining fifth code pattern data based on the fourth code pattern data, wherein the fifth code pattern data is the code pattern data except the fourth code pattern data in the first code pattern data;
determining the data length of the spliced code pattern data based on the data length of the fifth code pattern data and the spliced bit width;
and performing data splicing on the fifth code pattern data based on the data length of the spliced code pattern data.
In some embodiments, the data length of the fifth pattern data is greater than or equal to the splice bit width and less than the data bit width.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the pattern generation method as described in any of the above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a pattern generation method as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements a pattern generation method as described in any one of the above.
According to the error code instrument, the code pattern generating method, the device, the electronic equipment and the medium, the first code pattern data is repeatedly written under the condition that the first code pattern data and the data bit width of the error code instrument have no integral multiple relation, the second code pattern data obtained after the repeated writing is cached to the DDR, the first code pattern data is subjected to data splicing through the splicing module based on the splicing bit width and the data bit width until the third code pattern data with the integral multiple data bit width is obtained, so that the limitation of the data bit width of the error code instrument on the code pattern data can be relieved, the code pattern data with any length can be written, the code pattern data meeting the data bit width requirement can be obtained through data splicing, and the code pattern data can be normally and effectively output.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an error detector according to the present invention;
FIG. 2 is a second schematic diagram of the error detector according to the present invention;
FIG. 3 is a schematic flow chart of a pattern generation method provided by the invention;
FIG. 4 is a schematic diagram of a pattern generating apparatus according to the present invention;
fig. 5 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The error code meter, the code pattern generating method, the device, the electronic equipment and the medium of the invention are described below with reference to fig. 1 to 5.
Fig. 1 is a schematic structural diagram of an error code device provided by the invention. Referring to fig. 1, the error code apparatus provided by the present invention includes: DDR110, FPGA120 and digital to analog converter 130, FPGA120 includes a stitching module 1201;
DDR110 is used for caching first code type data, the first code type data is second code type data which are repeatedly written, the data length of the second code type data and the data bit width of the error code instrument are in a non-integer multiple relation, the data length of the first code type data is integer multiple of the splicing bit width, and the splicing bit width is determined based on the data bit width;
the FPGA120 is configured to read the first pattern data from the DDR110, and send the first pattern data to the splicing module 1201 for data splicing;
the splicing module 1201 is configured to perform data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, where the data length of the third code type data is an integer multiple of the data bit width;
a Digital-to-Analog Converter (DAC) 130 is used to output the third pattern data.
In the related art, the working principle of the error code meter is to detect the error code in the signal and calculate the error code rate by connecting with a digital signal source (such as a generator). The bit error rate is the ratio of the number of bit errors that occur in a signal to the total number of bits transmitted during transmission of the signal.
Error detectors are typically characterized by high accuracy and high speed and are capable of processing a variety of different types of digital signals, including high speed serial digital signals, optical signals in fiber optic communications, and the like. The error code meter is widely applied to the research and development, test and maintenance processes of a digital communication system, for example, in the aspects of communication system design and debugging, communication link quality evaluation, fault detection and the like.
A typical implementation architecture for a code error meter is shown in fig. 2.
Referring to fig. 2, since the field programmable gate array (Field Programmable Gate Array, FPGA) has a limited storage space, a Double Data Rate SDRAM (DDR SDRAM) is generally used to externally implement caching of custom pattern Data, and after the custom pattern Data is put into the DDR through the FPGA by the upper computer (Personal Computer, PC), the FPGA reads the custom pattern Data from the DDR and plays the custom pattern Data through the DAC. The custom code data can be normally cached only when the data length of the custom code data is an integer multiple of the data bit width of the DDR interface, and the problem of this is that the data length of the custom code data is limited. For custom pattern data which cannot be of any data length, DDR (double data rate) usually only writes pattern data which meets the integral multiple of the data bit width, and does not write pattern data which does not meet the integral multiple of the data bit width, so that normal use of certain special patterns cannot be realized due to the data length. When DDR writes code pattern data, the code pattern data is ensured to be valid, so that the length of data read by DDR meets the integral multiple of the data bit width, and the read code pattern data is ensured to be valid as well.
The error code meter can utilize a method for splicing data, adopts relatively small workload, realizes effective use of small-granularity custom code pattern data, and can even reach 1bit in precision.
It should be noted that, the smaller the bit width, the longer the data length of the user-defined code data that can be cached under the same hardware configuration, but the larger the splicing workload; the larger the bit width is, the smaller the data length of the user-defined code data which can be cached under the same hardware configuration is, but the smaller the splicing workload is.
The following description will take an example of a data bit width of 512 bits of the error code apparatus. It is understood that the data bit width of the error detector refers to the data bit width of the DDR110 interface.
In practical implementation, the upper computer may read the custom code pattern data file, that is, read the second code pattern data, and analyze the data length of the second code pattern data.
In the case of determining that the data length of the second pattern data and the data bit width of the DDR110 interface in the error detector are non-integer multiples, selecting an appropriate splice bit width, for example: and selecting the splicing bit width as 32 bits, 64 bits or 128 bits or performing data splicing. The data bit width is an integer multiple of the splice bit width, and the data bit width is greater than the splice bit width.
The splice bit width may be adjusted according to the DDR110 capacity and workload, and is not specifically limited herein.
For the second code type data with the data length of not 512 bits, for example, the data length of the second code type data is 513 bits or 514 bits, the upper computer can repeatedly write the second code type data end to obtain the first code type data, and the total data length of the first code type data is an integer multiple of the splicing bit width. The first pattern data may then be buffered to DDR110.
It is understood that the number of times the second pattern data is written repeatedly may be equal to a common multiple of the second pattern data and the splice bit width.
The FPGA120 takes out the first pattern data from the DDR110, splices the first pattern data by using the splicing module 1201 to obtain spliced third pattern data, and plays the third pattern data through the DAC 130.
In actual implementation, the splicing module 1201 may determine, based on the data bit width and the splicing bit width, a data length of the spliced code pattern data required for the first code pattern data, and splice the spliced third code pattern data to the first code pattern data according to the spliced code pattern data, so that the spliced third code pattern data is an integer multiple of the data bit width.
As shown in fig. 1, in some embodiments, FPGA120 further comprises: a first FIFO memory 1202 and a second FIFO memory 1203.
The first FIFO memory 1202 is configured to buffer the first pattern data, and send the first pattern data to the splicing module 1201 for data splicing;
the second FIFO memory 1203 is configured to buffer the third pattern data and send the third pattern data to the digital-to-analog converter.
In actual implementation, after the upper computer completes writing of the first code type data, the upper computer puts the first code type data into the DDR110 for buffering through the FPGA 120.
The FPGA120 can record a data length of pattern data that can be written in accordance with the data bit width based on the first pattern data. For example: assuming that the data length of the second code pattern data is 513 bits, the splice bit width is 64 bits, and the data length of the first code pattern data obtained after repeated writing is 513 bits×64.
As is clear from 513bit×64=512 bit×64+64bit, the data length of the code pattern data written with 512bit width is 512bit×64, that is, the data length of the code pattern data of the 65 th row is 64bit, and the total data line in the DDR110 is 65 rows.
The FPGA120 reads the first pattern data from the DDR110, buffers the first pattern data into a first-in-first-out (First Input First Output, FIFO) memory 1202, and the first FIFO memory 1202 sends the first pattern data to the splice module 1201 for data splicing. The data splicing refers to that based on the splicing bit width, after the code pattern data to be spliced is written, the code pattern data is written continuously, so that the bit width is equal to the data bit width.
In the present invention, the splicing module 1201 can normally input 64 lines of 512bit pattern data in the first pattern data, and since the last line of 64bit pattern data in the first pattern data, the required data length of the spliced pattern data is 512 bits-64 bits=448 bits, and 7 64bit spliced bit width pattern data is required.
It is understood that the first pattern data is automatically repeatedly written to the error detector. Thus, the first and second substrates are bonded together,
448bit splice pattern data may be obtained from the first row 512bit pattern data of 512bit x 64+64bit of the first pattern data of the next round of re-start writing. And performing data splicing on 448bit spliced code pattern data and 64bit code pattern data to change the data length of the last line of 64bit code pattern data in the first code pattern data input by the first round into 512 bits, thereby completing data splicing. The spliced first code pattern data is the third code pattern data.
The second FIFO memory 1203 may buffer the third pattern data and send the third pattern data to the DAC130, and then the DAC130 may normally play 65 lines of pattern data satisfying the data bit width. For example: in the process of reading the first code pattern data with the data length of 512bit×64+64bit, the code pattern data with the data length of 448bit is spliced, and then the data length of the third code pattern data is 512bit×64+64bit+448 bit=512 bit×65.
According to the error code meter provided by the invention, under the condition that the first code pattern data and the data bit width of the error code meter have no integer multiple relation, the first code pattern data is repeatedly written, the second code pattern data obtained after the repeated writing is cached to the DDR, the first code pattern data is spliced by the splicing module based on the splicing bit width until the third code pattern data with the integer multiple data bit width is obtained, so that the limitation of the data bit width of the error code meter on the code pattern data can be relieved, the code pattern data with any length can be written, the code pattern data meeting the data bit width requirement can be obtained through the data splicing, and the code pattern data can be normally and effectively output.
Fig. 3 is a flow chart of a pattern generation method provided by the invention. Referring to fig. 3, the code pattern generating method provided by the present invention may be applied to the error code meter in the foregoing embodiment, and the method may include: step 310 and step 320.
Step 310, repeatedly writing second code pattern data to obtain first code pattern data under the condition that the data length of the second code pattern data written into the error code meter and the data bit width of the error code meter are in a non-integer multiple relation, wherein the data length of the first code pattern data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code pattern data in the first code pattern data are sequentially connected end to end;
and 320, performing data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
The execution subject of the pattern generation method provided by the invention can be an electronic device, a component in the electronic device, an integrated circuit, or a chip. The electronic device may be a mobile electronic device or a non-mobile electronic device. By way of example, the mobile electronic device may be a cell phone, tablet computer, notebook computer, palm computer, vehicle mounted electronic device, wearable device, ultra-mobile personal computer (ultra-mobile personal computer, UMPC), netbook or personal digital assistant (personal digital assistant, PDA), etc., and the non-mobile electronic device may be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., without limitation of the present invention.
The following describes in detail the technical scheme of the present invention by taking an electronic device as an error code device to execute the code pattern generating method provided by the present invention as an example with reference to fig. 1.
In actual implementation, the second pattern data is the pattern data written in the error code meter, and the data length of the second pattern data is analyzed.
And under the condition that the upper computer determines that the data length of the second code type data and the data bit width of the error code instrument are in a non-integer multiple relation, repeatedly writing the second code type data into the error code instrument end to obtain the first code type data, and determining the splicing bit width corresponding to the second code type data. DDR110 caches the first pattern data through FPGA 120.
The data length of the first code type data is an integer multiple of the splicing bit width, the data bit width is an integer multiple of the splicing bit width, and the data bit width is larger than the splicing bit width.
For example: the data bit width is 512 bits, the data length of the second code type data is 513 bits, the selectable splicing bit width is 64 bits, and the data length of the first code type data is 513 bits multiplied by 64.
After the FPGA120 reads the first pattern data from the DDR110, the read first pattern data is subjected to data splicing by the splicing module 1201.
In actual implementation, the splicing module 1201 may determine, based on the data bit width and the splicing bit width, a data length of the spliced code pattern data required for the first code pattern data, and splice the spliced third code pattern data to the first code pattern data according to the spliced code pattern data, so that the spliced third code pattern data is an integer multiple of the data bit width.
For example: assuming that the data length of the second pattern data is 513 bits, the data length of the first pattern data obtained after the repeated writing is 513 bits×64.
As is known from 513 bits×64=512 bits×64+64 bits, the data length of the code pattern data written with 512 bits of data bit width is 512 bits×64, i.e., the first code pattern data has 64 lines of code pattern data satisfying the data bit width, and the data length of the code pattern data of the remaining lines is 64 bits. Since the last row of the first code pattern data is 64bit code pattern data, the data length of the required spliced code pattern data is 512bit-64 bit=448 bit, and 7 code pattern data with 64bit spliced bit width are required.
It is understood that the first pattern data is automatically repeatedly written to the error detector. Thus, the first and second substrates are bonded together,
448 bits of spliced pattern data may be obtained from 512bit x 64+64bit first row 512bit pattern data of the first pattern data of the next round of re-start writing. And performing data splicing on 448bit code pattern data and 64bit code pattern data to change the data length of the last line of 64bit code pattern data in the first code pattern data input by the first round into 512 bits, thereby completing data splicing. The spliced first code pattern data is the third code pattern data.
It can be understood that, in the process of reading the first code pattern data with the data length of 512 bits×64+64 bits, the splicing module 1201 splices the code pattern data with the data length of 448 bits, and then the data length of the third code pattern data is 512 bits×64+64 bits+448bit=512 bits×65.
DAC130 may play the third pattern data based on the data bit width.
In some embodiments, step 320 may include:
determining fourth code type data which can be written into the error code instrument according to the data bit width in the first code type data;
determining fifth pattern data based on the fourth pattern data, the fifth pattern data being pattern data other than the fourth pattern data in the first pattern data;
determining the data length of the spliced code pattern data based on the data length and the spliced bit width of the fifth code pattern data;
and performing data splicing on the fifth code pattern data based on the data length of the spliced code pattern data.
In actual implementation, FPGA120 may determine that the fourth pattern data of the error-coding apparatus can be written according to the data bit width in the first pattern data.
For example: assuming that the data bit width is 512 bits, the data length of the second code pattern data is 513 bits, the splice bit width is 64 bits, and the data length of the first code pattern data is 513 bits×64=512 bits×64+64 bits. The fourth code pattern data is 512bit code pattern data of the first 64 lines in the first code pattern data, and the fifth code pattern data is 64bit code pattern data of the 65 th lines.
The splicing module 1201 can normally input 64 lines of 512bit pattern data in the first code pattern data, and since the last line of the first code pattern data is 64bit fifth code pattern data, the data length of the spliced code pattern data required by the 64bit fifth code pattern data is 512bit-64 bit=448 bit, and 7 spliced code pattern data with 64bit splicing bit widths are required.
It is understood that the first pattern data is automatically repeatedly written to the error detector. Thus, the first and second substrates are bonded together,
448bit splice pattern data may be obtained from the first row 512bit pattern data of the first pattern data from which writing is resumed for the next round. And performing data splicing on 448-bit spliced code pattern data and 64-bit fifth code pattern data to change the data length of the last line of 64-bit fifth code pattern data in the first code pattern data input by the first round into 512 bits, thereby completing data splicing. And splicing the fifth code pattern data to obtain spliced first code pattern data, namely third code pattern data.
In actual implementation, the FPGA120 records the written total data line number of 512-bit width as d_w512cnt, and the data line number of 64-bit width d_w64cnt greater than or equal to 64-bit and smaller than 512-bit width. Therefore, the data length of the first pattern data=512 bit× (d_w512 cnt-1) +64bit×d_w64cnt.
In some embodiments, the data length of the fifth pattern data is greater than or equal to the splice bit width and less than the data bit width. For example: 64bit is less than or equal to 64bit and less than 512bit, and D_W64cnt is less than or equal to 1 and less than 8.
After the upper computer finishes writing the first code type data, the FPGA120 reads the first code type data from the DDR110 and caches the first code type data in the first FIFO memory 1202, and monitors the data amount in the first FIFO memory 1202, and marks the data amount as fifo_1_cnt, and the 512-bit-wide data line read by the FPGA120 from the DDR110 is d_ddroutcnt, where the maximum value of d_ddroutcnt should be d_w512cnt+1.
Since the bandwidth of reading the pattern data by the DDR110 is not equal to the playing data bandwidth of the DAC with a large probability, and the read data is discontinuous due to the need of refreshing the DDR110, the amount of data in the first FIFO memory 1202 and the second FIFO memory 1203 needs to be considered when splicing the data.
The spell module 120 starts the spell data based on three values of D_W512cnt, D_W64cnt, and D_DDROUTcnt. Let the initial input data of one round be G0, the initial data of each round be D0, set d_w512 cnt=64, d_w64cn=1, i.e. the total data of each round is 512 bits×64+64 bits, the output data is o_g0d0, o_g0d …, o_g0d63, o_g0d64, o_g1d0, o_g1d1 … …, the splicing process is:
the first round of data input, the first group of data total is 512bit×64+64bit.
Note that [511:0] represents 512bit pattern data, wherein 511 represents 512 th bit and 0 represents 1 st bit; [63:0] represents 64-bit pattern data, wherein 63 represents the 512 th bit and 0 represents the 1 st bit.
O_g0d0=g0d0; (indicating that line 1 inputs 512bit pattern data and outputs 512bit pattern data)
O_g0d1=g0d1; (indicating that line 2 inputs 512bit pattern data and outputs 512bit pattern data)
……
O_g0d63=g0d63; (indicating that line 64 inputs 512bit pattern data and outputs 512bit pattern data)
O_G0D64= { G0D64[511:448], G1D0[511:64] }; (indicating that the line 65 inputs 512bit-448 bit=64 bit pattern data, splices 512bit-64 bit=448 bit pattern data, and outputs 512bit pattern data)
And the second round of data input, wherein the total amount of the second group of data is 512 bits multiplied by 64+64 bits.
O_G1D0= { G1D0[63:0], G1D1[511:64] }; (indicating that the line 1 is input with 64bit pattern data, 512bit-64 bit=448 bit pattern data are spliced, and 512bit pattern data are output)
……
O_G1D63= { G1D63[63:0], G1D64[63:0], G2D0[511:128] }; (indicating that 64bit pattern data and 64bit pattern data are input in line 64, 512bit-128 bit=384 bit pattern data are spliced, and 512bit pattern data are output
O_g1d64= { G2D0[127:0], G2D1[511:128] }; (indicating that line 65 inputs 128bit pattern data, concatenates 512bit-128 bit=384 bit pattern data, and outputs 512bit pattern data)
And the third data input is performed, and the total amount of the third group data is 512 bits multiplied by 64+64 bits.
O_G2D0= { G2D1[127:0], G2D2[511:128] }; (representing line 1 inputting 128bit pattern data, splicing 512bit-128 bit=384 bit pattern data, outputting 512bit pattern data)
……
O_G2D63= { G2D63[127:0], G2D64[63:0], G3D0[511:192] }; (indicating that the 64 th line is input with 128bit code pattern data and 64bit code pattern data, and the 512bit-128bit-64 bit=320 bit code pattern data is spliced, and the output is 512bit code pattern data
……
The latter data can be analogized, and attention is paid to the flow control of the data, and the total data of each round is taken as an example.
After 8 rounds of data are input, the total data is ((512 bit×64) +64) ×8=512 bit×512+512 bit=512 bit x513. The input beats are (64+1) x8=65×8=520 beats, and the beats fed to the second FIFO memory 1203 are (512 x 513)/512=513 beats, so not every splice data is a valid receipt, and at the same time, since DDR110 granularity needs to be regularly refreshed, and the interface does not work when DDR110 is refreshed, which causes discontinuous read data, so that data between DDR110 and DAC130 needs to be streamed.
Meanwhile, as the splicing positions are different when each group is crossed, if the data is cut off at the moment, the splicing situation to be considered is complex, so that the time of flow control is required to be controlled. From the aspect of the splicing situation, one output data may be spliced by different data bits of three data in turn. Therefore, every time when the end of each group of data is read, i.e., d_ddroutcnt= (d_w512 cnt+1) -3, it is necessary to determine whether the data amount fifo_1_cnt in the first FIFO memory 1202 is greater than or equal to 3, so as to ensure that the data is valid data when the splice data position is changed, if not greater than or equal to 3, it is necessary to continue waiting, and not to read the data, and wait for the data amount in the first FIFO memory 1202 to be greater than or equal to 3; if the amount of data in the first FIFO memory 1202 is 3 or more, three data are continuously read from the first FIFO memory 1202 for concatenation of data; here 3 can also be adjusted according to the actual situation.
According to the code pattern generation method provided by the invention, under the condition that the first code pattern data and the data bit width of the error code instrument have no integer multiple relation, the second code pattern data is obtained by repeatedly writing the first code pattern data, and based on the spliced bit width and the data bit width, the second code pattern data is subjected to data splicing until the third code pattern data with the integer multiple data bit width is obtained, so that the limitation of the data bit width of the error code instrument on the code pattern data can be relieved, the code pattern data with any length can be written, the code pattern data meeting the data bit width requirement can be obtained through data splicing, and the code pattern data can be normally and effectively output.
The pattern generating device provided by the invention is described below, and the pattern generating device described below and the pattern generating method described above can be referred to correspondingly.
Fig. 4 is a schematic structural diagram of a pattern generating device provided by the present invention. Referring to fig. 4, the pattern generation apparatus provided by the present invention includes: a processing module 410 and a generating module 420.
The processing module 410 is configured to repeatedly write second pattern data of the error code device when the data length of the second pattern data is in a non-integer multiple relation with the data bit width of the error code device, so as to obtain first pattern data, where the data length of the first pattern data is an integer multiple of a splicing bit width, the splicing bit width is determined based on the data bit width, and the second pattern data in the first pattern data are sequentially connected end to end;
and the generating module 420 is configured to perform data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, where a data length of the third code type data is an integer multiple of the data bit width.
In some embodiments, the generating module 420 is specifically configured to:
determining fourth code pattern data which can be written into the error code instrument according to the data bit width in the first code pattern data;
determining fifth code pattern data based on the fourth code pattern data, wherein the fifth code pattern data is the code pattern data except the fourth code pattern data in the first code pattern data;
determining the data length of the spliced code pattern data based on the data length of the fifth code pattern data and the spliced bit width;
and performing data splicing on the fifth code pattern data based on the data length of the spliced code pattern data.
In some embodiments, the data length of the fifth pattern data is greater than or equal to the splice bit width and less than the data bit width.
According to the code pattern generating device, under the condition that the first code pattern data and the data bit width of the error code instrument do not have an integer multiple relationship, the second code pattern data is obtained by repeatedly writing the first code pattern data, and based on the spliced bit width and the data bit width, the second code pattern data is subjected to data splicing until the third code pattern data with the integer multiple data bit width is obtained, so that the limitation of the data bit width of the error code instrument on the code pattern data can be relieved, the code pattern data with any length can be written, the code pattern data meeting the data bit width requirement can be obtained through data splicing, and the code pattern data can be normally and effectively output.
Fig. 5 illustrates a physical schematic diagram of an electronic device, as shown in fig. 5, which may include: processor 510, communication interface (Communications Interface) 520, memory 530, and communication bus 540, wherein processor 510, communication interface 520, memory 530 complete communication with each other through communication bus 540. Processor 510 may invoke logic instructions in memory 530 to perform a pattern generation method comprising:
repeatedly writing second code type data of an error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and based on the splicing bit width and the data bit width, carrying out data splicing on the first code type data to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
Further, the logic instructions in the memory 530 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, the computer program product comprising a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of executing the pattern generation method provided by the above methods, the method comprising:
repeatedly writing second code type data of an error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and based on the splicing bit width and the data bit width, carrying out data splicing on the first code type data to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the pattern generation method provided by the above methods, the method comprising:
repeatedly writing second code type data of an error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and based on the splicing bit width and the data bit width, carrying out data splicing on the first code type data to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. An error detector, comprising: DDR, FPGA and digital-to-analog converter, the FPGA includes the splice module;
the DDR is used for caching first code type data, the first code type data is second code type data which are repeatedly written, the data length of the second code type data and the data bit width of the error code instrument are in a non-integer multiple relation, the data length of the first code type data is an integer multiple of the splicing bit width, and the splicing bit width is determined based on the data bit width;
the FPGA is used for reading the first code type data from the DDR, and sending the first code type data to the splicing module for data splicing;
the splicing module is used for carrying out data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, and the data length of the third code type data is an integer multiple of the data bit width;
the digital-to-analog converter is used for outputting the third code type data.
2. The code error meter of claim 1, wherein the FPGA further comprises: a first FIFO memory and a second FIFO memory;
the first FIFO memory is used for caching the first code type data and sending the first code type data to the splicing module for data splicing;
the second FIFO memory is configured to buffer the third code type data, and send the third code type data to the digital-to-analog converter.
3. A pattern generation method, comprising:
repeatedly writing second code type data of an error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and based on the splicing bit width and the data bit width, carrying out data splicing on the first code type data to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
4. The pattern generation method according to claim 3, wherein the data splicing of the first pattern data based on the splice bit width and the data bit width comprises:
determining fourth code pattern data which can be written into the error code instrument according to the data bit width in the first code pattern data;
determining fifth code pattern data based on the fourth code pattern data, wherein the fifth code pattern data is the code pattern data except the fourth code pattern data in the first code pattern data;
determining the data length of the spliced code pattern data based on the data length of the fifth code pattern data and the spliced bit width;
and performing data splicing on the fifth code pattern data based on the data length of the spliced code pattern data.
5. The pattern generation method according to claim 4, wherein a data length of the fifth pattern data is equal to or greater than the splice bit width and less than the data bit width.
6. A pattern generation apparatus comprising:
the processing module is used for repeatedly writing the second code type data of the error code instrument under the condition that the data length of the second code type data of the error code instrument is in a non-integer multiple relation with the data bit width of the error code instrument, so as to obtain first code type data, wherein the data length of the first code type data is an integer multiple of the splicing bit width, the splicing bit width is determined based on the data bit width, and the second code type data in the first code type data are sequentially connected end to end;
and the generation module is used for carrying out data splicing on the first code type data based on the splicing bit width and the data bit width to obtain third code type data, wherein the data length of the third code type data is an integer multiple of the data bit width.
7. The code pattern generating device according to claim 6, wherein the generating module is specifically configured to:
determining fourth code pattern data which can be written into the error code instrument according to the data bit width in the first code pattern data;
determining fifth code pattern data based on the fourth code pattern data, wherein the fifth code pattern data is the code pattern data except the fourth code pattern data in the first code pattern data;
determining the data length of the spliced code pattern data based on the data length of the fifth code pattern data and the spliced bit width;
and performing data splicing on the fifth code pattern data based on the data length of the spliced code pattern data.
8. The pattern generation apparatus according to claim 7, wherein a data length of the fifth pattern data is equal to or greater than the splice bit width and less than the data bit width.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the pattern generation method of any of claims 3 to 5 when the program is executed by the processor.
10. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the pattern generation method according to any of claims 3 to 5.
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