CN115567368A - SerDes problem detection method, device and medium - Google Patents
SerDes problem detection method, device and medium Download PDFInfo
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Abstract
The application relates to the technical field of data processing, and discloses a method, a device and a medium for detecting SerDes problems, wherein a detection instruction is sent to a target chip when detecting that the SerDes link state meets a preset condition; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error. By adopting the technical scheme, when the SerDes has a problem, the processor sends the test instruction to the target chip, so that the target chip performs internal detection according to the instruction, and after internal error information is detected, the processor realizes positioning of a point where the problem is located by reading an error alarm. And if the problem is not the problem in the chip, judging whether the problem is the SerDes problem caused by the connection error of the physical link, thereby realizing the positioning of the problem.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method, an apparatus, and a medium for detecting SerDes problems.
Background
SerDes is an acronym for SERializer/DESerializer. It is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, at the transmitting end, the multi-path low-speed parallel signals are converted into high-speed serial signals, and finally, at the receiving end, the high-speed serial signals are converted into low-speed parallel signals again through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing the communication cost.
The speed of the SerDes single lane can reach 30Gbps, and in ordinary application, the speed of the SerDes is instantiated to be in a Giga level generally, so that the working stability of the SerDes is very important, and when a certain link has a problem, error codes can be caused in data transmission. When the SerDes has a problem in the working state, the problem point should be found quickly and accurately, and in order to enable the system to operate normally, when the SerDes has a problem, the problem point should be automatically diagnosed and the problem should be self-healed.
Therefore, how to realize detection of SerDes problem is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method, a device and a medium for detecting a SerDes problem, so as to realize detection of the SerDes problem, avoid data transmission errors and ensure the reliability of link operation and the timeliness of error processing.
In order to solve the above technical problems, the present application provides a method for detecting SerDes problems, comprising:
sending a detection instruction to a target chip under the condition that the SerDes link state is detected to meet a preset condition;
judging whether an error alarm is read from the target chip;
if yes, positioning the point of the problem according to the error alarm;
if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
Preferably, the error alarm comprises a clock alarm and an internal error information alarm.
Preferably, the clock alarm includes: a clock loss alarm and a clock frequency offset alarm;
correspondingly, the clock loss alarm is as follows: the target chip uses a preset clock to perform sampling detection on the SerDes reference clock;
if the level change is not detected within the preset time, a clock loss alarm is sent out;
correspondingly, the clock frequency offset alarm is as follows: down-clocking the SerDes reference clock by a preset multiple;
sampling the SerDes reference clock using the preset clock;
counting high level sampling points in a sampled clock;
calculating the SerDes reference clock frequency according to the magnitude relation between the sampling clock and the preset clock;
and if the SerDes reference clock frequency is not accordant with the standard frequency, sending a clock frequency deviation alarm.
Preferably, the internal error information alarm includes: the target chip judges whether the internal error information alarm is a false alarm or not;
if yes, the internal error information alarm is not reported;
if not, the internal error information alarm is subjected to clock domain synchronization and then reported.
Preferably, the determining whether the SerDes physical link has a problem includes:
switching a data transmission link to a self-packet link;
adding PRBS codes to the sent messages;
judging whether PRBS codes in the sent and received messages are consistent;
if not, then a problem with the SerDes physical link is identified.
Preferably, in the case of reading the clock alarm, the method further includes:
resetting a clock chip on the target chip and resetting and restarting the SerDes;
judging whether a clock alarm is read again;
and if so, positioning the point of the problem according to the error alarm.
Preferably, also comprises
If the point of the problem of alarm positioning according to the internal error information is that the CDR is unlocked, resetting the CDR;
and if the point of the problem of the alarm positioning according to the internal error information is buffer overflow, resetting the SerDes.
In order to solve the above technical problem, the present application further provides a SerDes problem detection device, comprising:
the sending module is used for sending a detection instruction to a target chip under the condition that the SerDes link state is detected to meet a preset condition;
the processing module is used for judging whether an error alarm is read from the target chip; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
In order to solve the above technical problem, the present application further provides another SerDes problem detection apparatus, including a memory for storing a computer program;
a processor for implementing the steps of the SerDes problem detection method as described above when executing the computer program.
To solve the above technical problem, the present application further provides a computer-readable storage medium having a computer program stored thereon, where the computer program, when executed by a processor, implements the steps of the SerDes problem detection method as described above.
According to the SerDes problem detection method, when the condition that the SerDes link state meets the preset condition is detected, a detection instruction is sent to a target chip; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error. By adopting the technical scheme, when the SerDes has a problem, the processor sends the test instruction to the target chip, so that the target chip performs internal detection according to the instruction, and after internal error information is detected, the processor realizes positioning of a point where the problem is located by reading an error alarm. And if the problem is not the problem in the chip, judging whether the problem is the SerDes problem caused by the connection error of the physical link. By adopting the technical scheme provided by the application, when the processor detects the occurrence of the SerDes problem, the problem is detected in the target chip, and if the problem does not exist in the target chip, the problem of a physical connection link is detected, so that the SerDes problem is detected, and data output errors are avoided.
The SerDes problem detection device and medium provided by the present application correspond to the above-described SerDes problem detection method, and the effects are the same as described above.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a diagram of a SerDes architecture;
FIG. 2 is a flow chart of a method for SerDes problem detection as provided by an embodiment of the present application;
fig. 3 is an overall architecture diagram of a SerDes application according to an embodiment of the present disclosure;
fig. 4 is a structural diagram of a SerDes problem detection apparatus according to an embodiment of the present disclosure;
fig. 5 is a structural diagram of another SerDes problem detection apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
There are two ways to increase the transmission bandwidth of the interface, one is to increase the clock frequency, and the other is to increase the data bit width. As the data bit width increases with increasing frequency, synchronous Switching Noise (SSN) becomes a major bottleneck in increasing transmission bandwidth. One solution to SSN is to use differential signals instead of single-ended signals, which can solve SSN problems well at the cost of more chip pins. The problem of data clock skew still cannot be solved by using differential signals, and the parallel interface is challenged by the differential signals with large bit width and strict timing limitation.
The clock frequency of the source synchronous interface has already met the bottleneck, because of the non-ideal characteristic of the channel, and then continue to raise the frequency, the signal will be seriously damaged, need to adopt techniques such as equalization and data clock phase detection. This is the technique employed by SerDes.
Fig. 1 is a diagram of a SerDes architecture, as shown in fig. 1, serDes is an abbreviation for SERializer/DESerializer. The Serializer (Serializer) is also called SerDes transmitter TX (Deserializer) and receiver RX. SerDes is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, at the transmitting end, the multi-path low-speed parallel signals are converted into high-speed serial signals, and finally, at the receiving end, the high-speed serial signals are converted into low-speed parallel signals again through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing the communication cost. The SerDes does not transmit a Clock signal, which is the most specific place for SerDes, and integrates a CDR (Clock Data Recovery) circuit at the receiving end, extracts a Clock from edge information of Data using the CDR, and finds an optimal sampling position.
The speed of the SerDes single lane can reach 30Gbps, in ordinary application, the speed of the SerDes is instantiated to be in a Giga level normally, so that the working stability of the SerDes is very important, and when a certain link has a problem, error codes can be caused in data transmission. When the SerDes has a problem in the working state, the problem point should be found quickly and accurately, and in order to enable the system to operate normally, when the SerDes has a problem, the problem point should be automatically diagnosed and the problem should be self-healed.
Therefore, how to realize detection of SerDes problem is an urgent problem to be solved by those skilled in the art.
The core of the application is to provide a method, a device and a medium for detecting the SerDes problem, so as to realize the detection of the SerDes problem, avoid data transmission errors and ensure the reliability of link operation and the timeliness of error processing.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
Fig. 2 is a flowchart of a SerDes problem detection method according to an embodiment of the present disclosure, and as shown in fig. 1, the method includes:
s10: and sending a detection instruction to the target chip under the condition that the SerDes link state is detected to meet the preset condition.
S11: judging whether an error alarm is read from the target chip or not; if yes, go to step S12; if not, the process proceeds to step S13.
S12: and positioning the point of the problem according to the error alarm.
S13: and judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
It should be noted that, in the present embodiment, the execution main body of the SerDes problem detection method may be a SerDes problem detection device, or may be a Central Processing Unit (CPU), which implements operations and control, information processing, and program operations of the entire system. For convenience of understanding, the following description is made with reference to a specific SerDes usage, and fig. 3 is an overall architecture diagram of SerDes application provided in the embodiment of the present application, as shown in fig. 3, in the system, a path between a target chip a and a chip B and a SerDes path are controlled by a CPU through localbus, and information inside the target chip a is also reported to the CPU through localbus. The Local Bus is also called a CPU Bus, and can be divided into a Motorola CPU Bus and an Intel CPU Bus according to the difference of the high and low bit address line order.
The preset condition in this embodiment refers to a situation that a SerDes link may be in false alarm or the link may be directly changed from link to down. In specific implementation, when the SerDes has a problem, a wrong report can occur on the SerDes link or the link is directly changed from link to down, the CPU sends a detection instruction to the target chip A when detecting the situation, the target chip A can carry out internal detection according to the instruction, a corresponding error alarm can be reported to the hreg module after detecting the internal problem, and the CPU realizes the positioning of the point of the problem by reading the alarm in the hreg module. If the problem is not the problem in the chip, whether the SerDes physical link has the problem needs to be detected, and whether the physical link connection between the chip A and the chip B is wrong or not needs to be judged.
In this embodiment, the target chip a includes clock detection and internal error information detection when detecting the internal problem, and correspondingly, the error alarm includes a clock alarm and an internal error information alarm. Specifically, as shown in fig. 3, the target chip a includes a CLK _ DET module and a Buffer _ DET module. The CLK _ DET module is a clock detection module, which is used to detect the reference clock of the SerDes. The method mainly comprises two functions, wherein the first part is used for detecting whether a reference clock exists or not, and the second part is used for qualitatively detecting the frequency of the reference clock. The loss of the reference clock and the excessive frequency deviation of the reference clock are both reasons of the abnormal operation of the SerDes. Correspondingly, the clock alarm comprises: a clock loss alarm and a clock frequency offset alarm; correspondingly, the clock loss alarm is: the target chip uses a preset clock to perform sampling detection on the SerDes reference clock; and if the level change is not detected within the preset time, sending a clock loss alarm.
The clock frequency offset alarm is as follows: reducing the frequency of the SerDes reference clock by a preset multiple; sampling a SerDes reference clock by using a preset clock; counting high level sampling points in a sampled clock; calculating the SerDes reference clock frequency according to the magnitude relation between the sampling clock and the preset clock; and if the SerDes reference clock frequency does not accord with the standard frequency, sending a clock frequency deviation alarm.
The module uses a single 100M reference clock, when the SerDes reference clock is detected, the 100M clock is used for sampling detection on the SerDes reference clock, and if level change is detected in the sampling detection within 100ms, the SerDes reference clock is considered to exist. When the SerDes reference clock is subjected to frequency offset test, the reference clock is divided firstly, the frequency of the reference clock is reduced by 100 times, then the clock after frequency reduction is sampled by using the 100M clock, and the high-level sampling points of the clock after frequency reduction are counted, so that the approximate relation between the clock after frequency reduction and the 100M clock can be calculated, the clock frequency after frequency reduction is qualitatively calculated according to the relation, and then the frequency is multiplied by 100, so that the reference clock frequency is obtained, and further the detection of the clock frequency offset is realized.
The Buffer _ det module is mainly used for processing and reporting an alarm generated inside the SerDes. Another cause of SerDes operation anomaly is internal FIFO overflow, or CDR loss of lock, which when it occurs, generates a corresponding alarm. The Buffer _ det module processes the alarm sent by the SerDes. When the module is used for processing, firstly, the reported alarm is subjected to false detection screening, and if the alarm is a false alarm, the alarm is not reported; then, the alarm signal is subjected to clock domain synchronization and reported to the hreg module. And the CPU reads the alarm information in the hreg through localBus. Namely, the internal error information alarm comprises: the target chip judges whether the internal error information alarm is a false alarm; if yes, not reporting internal error information alarm; if not, the internal error information alarm is reported after clock domain synchronization.
Correspondingly, if the point of the problem of alarm positioning according to the internal error information is that the CDR is unlocked, resetting the CDR; and if the point of the problem of alarm positioning according to the internal error information is buffer overflow, resetting the SerDes.
According to the SerDes problem detection method provided by the embodiment of the application, under the condition that the SerDes link state is detected to meet the preset condition, a detection instruction is sent to a target chip; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error. By adopting the technical scheme, when the SerDes has a problem, the processor sends the test instruction to the target chip, so that the target chip performs internal detection according to the instruction, and after internal error information is detected, the processor realizes positioning of a point where the problem is located by reading an error alarm. And if the problem is not the problem in the chip, judging whether the problem is the SerDes problem caused by the connection error of the physical link. By adopting the technical scheme provided by the application, when the processor detects the occurrence of the SerDes problem, the problem is detected in the target chip, and if the problem does not exist in the processor, the problem of the physical connection link is detected, so that the SerDes problem is detected, data output errors are avoided, and the reliability of link operation and the timeliness of error processing are ensured.
The target chip A also comprises a Pkt _ gen module which is a sub-packet sending module. The function is to generate the required message according to the distribution configuration. In a specific implementation, the number of generated messages and the message length can be configured by the CPU. Meanwhile, the module can also be matched with a chip loop to send out and recycle the message, and whether the link has a problem is judged by comparing whether the sent message is consistent with the received message.
In addition, the module may be configured to transmit a PRBS code to specifically test SerDes links. The verification of a Pseudo-Random Binary Sequence (PRBS) is the reverse process of the generation of the PRBS, and the specific method is that a Transceiver receiving end firstly registers received data for one beat (parallel data), PRBS coding is carried out on the registered data, the coded data is compared with the latest received data, and if the coded data is consistent with the latest received data, the PRBS verification is indicated to be correct.
Specifically, determining whether there is a problem with the SerDes physical link includes: switching a data transmission link to a spontaneous packet link; adding PRBS codes to the sent messages; judging whether PRBS codes in the sent and received messages are consistent; if not, a problem is identified with the SerDes physical link. In addition, the CPU can also print a physical link error alarm to remind maintenance personnel to manually check whether a physical error occurs in a connection path.
It will be appreciated that in the implementation, normal Data processing is in the Data _ proc module, and that Pkt _ gen and Data _ proc are alternatives on the Data path, and when a problem occurs, the Data path is switched to the Pkt _ gen module, so that the link connection test is performed.
In the embodiment, after the SerDes has a problem, a CPU senses that a link is in error report or directly changes from link to down, a CLK _ det module is started, a SerDes clock is detected, if clock loss or overlarge clock frequency offset is detected, a clock chip on a board is reset, the SerDes is reset 200ms after the clock chip is reset, and meanwhile, a reference clock fault error log is recorded; if the clock is normal, the next detection is carried out. The CPU reads the SerDes internal error information reported by the Buffer _ det, and if the CDR is unlocked, the CDR is reset; if buffer overflow is found, the Serdes is reset and the SerDes fault is recorded to an error log. If neither the reference clock nor the buffer _ det report errors exist, the CPU switches the data link from normal data processing to a self-packet module, an outer ring of an opposite-end chip is configured, the self-packet module prints a PRBS code on the link, if the PRBS detects errors, the CPU prints a physical link error alarm, and maintenance personnel are required to manually check whether a physical error occurs in a connection path.
In the above embodiments, the SerDes problem detection method is described in detail, and the present application also provides embodiments corresponding to the SerDes problem detection apparatus. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.
Fig. 4 is a structural diagram of a SerDes problem detection apparatus according to an embodiment of the present application, and as shown in fig. 4, the apparatus includes:
the sending module 10 is configured to send a detection instruction to a target chip when detecting that the SerDes link state satisfies a preset condition;
the processing module 11 is used for judging whether an error alarm is read from the target chip; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
It should be noted that the structure shown in fig. 4 does not constitute a limitation to the SerDes problem detection apparatus, and in other embodiments, the SerDes problem detection apparatus may further include more or fewer modules, for example, a configuration module may also be included to configure the number of messages generated by the target chip a and the message length.
The SerDes problem detection device provided by the embodiment of the application sends a detection instruction to a target chip when detecting that the SerDes link state meets the preset condition; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error. By adopting the technical scheme, when the SerDes has a problem, the processor sends the test instruction to the target chip, so that the target chip performs internal detection according to the instruction, and after internal error information is detected, the processor realizes positioning of a point where the problem is located by reading an error alarm. And if the problem is not the problem in the chip, judging whether the problem is the SerDes problem caused by the connection error of the physical link. By adopting the technical scheme provided by the application, when the processor detects the occurrence of the SerDes problem, the problem is detected in the target chip, and if the problem does not exist in the processor, the problem of a physical connection link is detected, so that the SerDes problem is detected, and data output errors are avoided.
Fig. 5 is a block diagram of another SerDes problem detection apparatus according to an embodiment of the present application, and as shown in fig. 5, the apparatus includes: a memory 20 for storing a computer program;
a processor 21 for implementing the steps of the SerDes problem detection method as described above in the embodiments when executing the computer program.
The SerDes problem detection apparatus provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The Processor 21 may be implemented in at least one hardware form of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in a wake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computing operations related to machine learning.
The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, wherein after being loaded and executed by the processor 21, the computer program can implement the relevant steps of the SerDes problem detection method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among others, windows, unix, linux, and the like. Data 203 may include, but is not limited to, error alerts, and the like.
In some embodiments, the SerDes problem detection apparatus may further include a display 22, an input-output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the configuration shown in fig. 5 does not constitute a limitation of SerDes problem detection devices and may include more or fewer components than those shown.
The SerDes problem detection device provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the following method can be realized: sending a detection instruction to a target chip under the condition that the SerDes link state is detected to meet a preset condition; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
The SerDes problem detection device provided by the embodiment of the application sends a detection instruction to a target chip when detecting that the SerDes link state meets the preset condition; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error. By adopting the technical scheme, when the SerDes has a problem, the processor sends the test instruction to the target chip, so that the target chip performs internal detection according to the instruction, and after internal error information is detected, the processor realizes positioning of a point where the problem is located by reading an error alarm. And if the problem is not the problem in the chip, judging whether the problem is the SerDes problem caused by the connection error of the physical link. By adopting the technical scheme provided by the application, when the processor detects the occurrence of the SerDes problem, the problem is detected in the target chip, and if the problem does not exist in the target chip, the problem of a physical connection link is detected, so that the SerDes problem is detected, and data output errors are avoided.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The computer-readable storage medium provided by the embodiment of the application sends a detection instruction to a target chip when detecting that the SerDes link state meets a preset condition; judging whether an error alarm is read from the target chip or not; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error. By adopting the technical scheme, when the SerDes has a problem, the processor sends the test instruction to the target chip, so that the target chip performs internal detection according to the instruction, and after internal error information is detected, the processor realizes positioning of a point where the problem is located by reading an error alarm. And if the problem is not the problem in the chip, judging whether the problem is the SerDes problem caused by the connection error of the physical link. By adopting the technical scheme provided by the application, when the processor detects the occurrence of the SerDes problem, the problem is detected in the target chip, and if the problem does not exist in the target chip, the problem of a physical connection link is detected, so that the SerDes problem is detected, and data output errors are avoided.
The SerDes problem detection method, apparatus, and medium provided by the present application are described in detail above. The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method of SerDes problem detection, comprising:
sending a detection instruction to a target chip under the condition that the SerDes link state is detected to meet a preset condition;
judging whether an error alarm is read from the target chip;
if yes, positioning the point of the problem according to the error alarm;
if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
2. The SerDes problem detection method of claim 1, wherein the error alarm comprises a clock alarm and an internal error information alarm.
3. The SerDes problem detection method according to claim 2, wherein the clock alert comprises: a clock loss alarm and a clock frequency offset alarm;
correspondingly, the clock loss alarm is as follows: the target chip uses a preset clock to perform sampling detection on the SerDes reference clock;
if the level change is not detected within the preset time, a clock loss alarm is sent out;
correspondingly, the clock frequency offset alarm is as follows: reducing the frequency of the SerDes reference clock by a preset multiple;
sampling the SerDes reference clock using the preset clock;
counting high level sampling points in a sampled clock;
calculating the SerDes reference clock frequency according to the magnitude relation between the sampling clock and the preset clock;
and if the SerDes reference clock frequency is not in accordance with the standard frequency, sending a clock frequency deviation alarm.
4. The SerDes problem detection method of claim 2, wherein said internal error information alert comprises:
the target chip judges whether the internal error information alarm is a false alarm;
if yes, the internal error information alarm is not reported;
if not, the internal error information alarm is subjected to clock domain synchronization and then reported.
5. The SerDes problem detection method of claim 1, wherein said determining whether a problem exists with the SerDes physical link comprises:
switching a data transmission link to a self-packet link;
adding PRBS code on the transmitted message;
judging whether PRBS codes in the sent and received messages are consistent or not;
and if the two are not consistent, confirming that the SerDes physical link has a problem.
6. The SerDes problem detection method of claim 2, further comprising, in the event of a read clock alarm:
resetting a clock chip on the target chip and resetting and restarting the SerDes;
judging whether a clock alarm is read again;
and if so, positioning the point of the problem according to the error alarm.
7. The SerDes problem detection method of claim 2, further comprising
If the point of the problem of alarm positioning according to the internal error information is that the CDR is unlocked, resetting the CDR;
and if the point of the problem of the alarm positioning according to the internal error information is buffer overflow, resetting the SerDes.
8. A SerDes problem detection apparatus, comprising:
the sending module is used for sending a detection instruction to a target chip under the condition that the SerDes link state is detected to meet a preset condition;
the processing module is used for judging whether an error alarm is read from the target chip; if yes, positioning the point of the problem according to the error alarm; if not, judging whether the SerDes physical link has a problem, and if so, determining that the point of the problem is a physical link connection error.
9. A SerDes problem detection apparatus, comprising a memory for storing a computer program;
a processor for implementing the steps of the SerDes problem detection method of any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, having a computer program stored thereon, which, when executed by a processor, performs the steps of the SerDes problem detection method of any of claims 1-7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116501564A (en) * | 2023-06-27 | 2023-07-28 | 苏州浪潮智能科技有限公司 | Chip verification method, field programmable gate array chip and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116501564A (en) * | 2023-06-27 | 2023-07-28 | 苏州浪潮智能科技有限公司 | Chip verification method, field programmable gate array chip and device |
| CN116501564B (en) * | 2023-06-27 | 2023-11-03 | 苏州浪潮智能科技有限公司 | Chip verification method, field programmable gate array chip and device |
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