CN109871344B - Communication system, interface circuit and signal transmission method thereof - Google Patents
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Abstract
The invention relates to a communication system, an interface circuit and a method for transmitting signals, wherein the interface circuit comprises: the detection module is used for respectively carrying out characteristic detection on the signals on the two connecting lines and identifying the signal types of the two connecting lines according to the characteristic information of the two connecting lines; the address acquisition module is used for acquiring an address corresponding to the identification result according to the corresponding relation between the pre-stored signal type and the address; the adjusting module is used for adjusting the line sequence of the two connecting lines according to the identification result; and the protocol analysis module is used for analyzing the signals on the two connecting lines after the line sequence is adjusted, adding the acquired address into the analyzed signals and outputting the signals to two post-stage devices. By implementing the technical scheme of the invention, different post-stage equipment can be controlled by changing the connection mode of the interface circuit and the pre-stage host, and the cost of the post-stage equipment does not need to be increased.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a communication system, an interface circuit, and a method for transmitting signals.
Background
Among the communication interfaces between Integrated Circuits (ICs), I2C (Inter-Integrated Circuit) is a bus system that is widely used, and I2C is a serial bus developed by PHLIPS corporation, which is a high-performance serial bus including bus arbitration and high/low speed device synchronization functions required by multi-host systems.
The I2C bus has only two bidirectional signal lines. One is the SDA data line, the other is the SCL clock line, is used for connecting singlechip and peripheral equipment, for example, as shown in figure 1, singlechip A, B connects SARM, E2PROM, A/D, D/A, calendar clock, or other peripheral equipment through I2C bus respectively.
The process sequence of I2C bus sending data is shown in fig. 2A, and the whole process includes the following communication states:
idle: the SDA data line and the SCL clock line are both high. After the receiving device receives a complete data byte, it may need to complete some other work, such as processing internal interrupt service, etc., and may not be able to receive the next byte immediately. Until the receiving device is ready to receive the next byte, the SCL line is released high again so that the data transfer can continue.
Starting: as shown in fig. 2B, during the period when the SCL clock line is at high level, the SDA data line changes from high level to low level to represent the start signal;
stopping: as shown in fig. 2C, during the period when the SCL clock line is at high level, the SDA data line changes from low level to high level to represent a termination signal;
and (3) data transmission: it should be noted that the level signal on the SDA data line is kept stable during the read of a level signal transition on the SCL clock line, as shown by the transfer logic "0" in fig. 2D and the transfer logic "1" in fig. 2E.
In a communication system including a preceding host and a plurality of subsequent devices, the preceding host needs to know an address of each subsequent device in advance in order to control the subsequent device. However, when another previous host is newly added to the communication system and the previous host needs to control the subsequent device, it is necessary to configure different addresses for the same subsequent device, and the current methods generally include the following steps:
1. the chip of the latter device has an additional Pin, and a specific connection is made on the PCB of the latter device, so that the system is configured with different addresses, but the hardware cost is increased;
2. different firmware is built in the post-stage equipment, a protocol analyzer is configured in the system by the firmware, and the different firmware brings about management cost, but the problem of difficult software management is brought;
3. the inside of the post-stage device uses the circuit with hardware cost such as Efuse to burn the differentiated address, but this will bring the cost of inventory management to increase.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a communication system, an interface circuit and a method for transmitting signals thereof, which do not increase the cost, aiming at the above-mentioned high cost defect in the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: an interface circuit is constructed to be connected with a front-stage host and two back-stage devices, comprising:
the detection module is used for respectively carrying out characteristic detection on signals on the two connecting lines and identifying the signal types of the two connecting lines according to the characteristic information of the two connecting lines;
the address acquisition module is used for acquiring an address corresponding to the identification result according to the corresponding relation between the pre-stored signal type and the address;
the adjusting module is used for adjusting the line sequence of the two connecting lines according to the identification result;
and the protocol analysis module is used for analyzing the signals on the two connecting lines after the line sequence is adjusted, adding the acquired address into the analyzed signals and outputting the signals to two post-stage devices.
Preferably, the detection module comprises:
the first counter is used for counting the number of edges of the level signal on one connecting line within preset time;
the second counter is used for counting the number of edges of the level signal on the other connecting line within preset time;
and the identification unit is used for identifying the two connecting lines as the SDA data line or the SCL clock line according to the number of the edges of the two connecting lines.
Preferably, the number of the edges is the number of rising edges, and the input end of the first counter is connected to the one connection line, and the input end of the second counter is connected to the other connection line.
Preferably, the number of edges is the number of falling edges, and the detecting module further includes a first not gate and a second not gate, an input terminal of the first not gate is connected to the one of the connecting lines, and an output terminal of the first not gate is connected to an input terminal of the first counter; and the input end of the second NOT gate is connected with the other connecting line, and the output end of the second NOT gate is connected with the input end of the second counter.
Preferably, the number of the edges is the sum of the number of rising edges and the number of falling edges, and the detecting module further includes a first delay unit, a second delay unit, a first xor gate and a second xor gate, wherein an input terminal of the first delay unit is connected to the one of the connection lines, two input terminals of the first xor gate are respectively connected to the one of the connection lines and an output terminal of the first delay unit, and an output terminal of the first xor gate is connected to an input terminal of the first counter; the input end of the second delay unit is connected with the other connecting wire, two input ends of the second exclusive-or gate are respectively connected with the other connecting wire and the output end of the second delay unit, and the output end of the second exclusive-or gate is connected with the input end of the second counter.
Preferably, the identification unit is a comparator or a divider.
Preferably, the adjusting module includes a first switch and a second switch, wherein a first fixed contact of the first switch and a second fixed contact of the second switch are respectively connected to the one connection line, a second fixed contact of the first switch and a first fixed contact of the second switch are respectively connected to the other connection line, a moving contact of the first switch and a moving contact of the second switch are respectively connected to the SCL clock line and the SDA data line of the protocol parsing module, and a control end of the first switch and a control end of the second switch are respectively connected to the detecting module.
The invention also constructs a communication system, which comprises a front-stage host and two back-stage devices, and is characterized by also comprising an interface circuit connected between the front-stage host and the back-stage devices, wherein the interface circuit is the interface circuit.
The invention also constructs a method for transmitting signal by interface circuit, the interface circuit connects front host and two back devices, which comprises:
s10, respectively carrying out characteristic detection on signals on two connecting lines, and identifying the signal types of the two connecting lines according to the characteristic information of the two connecting lines;
s20, acquiring an address corresponding to the identification result according to a pre-stored corresponding relation between the signal type and the address;
s30, adjusting the line sequence of the two connecting lines according to the recognition result;
and S40, analyzing the signals on the two connecting wires after the line sequence is adjusted, adding the acquired address into the analyzed signals, and outputting the signals to two subsequent devices.
Preferably, the step S10 includes:
s11, counting the number of edges of the level signals on the two connecting wires within preset time;
and S12, identifying the two connecting lines as an SDA data line or an SCL clock line according to the number of edges of the two connecting lines.
By implementing the technical scheme of the invention, when the front-stage host controls the two rear-stage devices, the addresses of the two rear-stage devices do not need to be known in advance, the control of different rear-stage devices can be realized only by changing the connection mode of the interface circuit and the front-stage host, and the rear-stage devices do not need to be processed differently on any other hardware and can realize the same model stock management, so the cost of the rear-stage devices does not need to be increased.
Drawings
In order to illustrate the embodiments of the invention more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of a single chip microcomputer and peripheral devices connected through an I2C bus;
FIG. 2A is a timing diagram of the I2C bus;
FIG. 2B is a timing diagram of the start state of the I2C bus;
FIG. 2C is a timing diagram of the stall state of the I2C bus;
FIG. 2D is a timing diagram of the I2C bus transferring a logic 0 state;
FIG. 2E is a timing diagram of the I2C bus transferring a logic 1 state;
FIG. 3 is a logical block diagram of a first embodiment of a communication system according to the present invention;
FIG. 4 is a logic diagram of a first embodiment of the detection module of FIG. 3;
FIG. 5 is a logical block diagram of a first embodiment of the adjustment module of FIG. 3;
FIG. 6 is a flowchart illustrating a first embodiment of a method for transmitting signals by the interface circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 3 is a logical structure diagram of a communication system according to a first embodiment of the present invention, where the communication system includes a front-stage host 20, an interface circuit 10, and two back- stage devices 31 and 32, where the interface circuit 10 includes a detection module 11, an address obtaining module 12, an adjustment module 13, and a protocol analysis module 14. In addition, front host 20 has two ports C, D, interface circuit 10 has two ports A, B, and port A, B may be connected to port C, D by a connecting wire. In this embodiment, the detecting module 11 is configured to perform feature detection on signals on two connection lines respectively, and identify signal types of the two connection lines according to feature information of the two connection lines; the address obtaining module 12 is configured to obtain an address corresponding to the identification result according to a pre-stored correspondence between the signal type and the address; the adjusting module 13 is configured to adjust the line sequences of the two connection lines according to the recognition result; the protocol analyzing module 14 is configured to analyze the signals on the two connection lines after the line sequence adjustment, add the acquired address to the analyzed signals, and output the signals to the two subsequent devices 31 and 32.
The working principle of the communication system is explained as follows:
for example, in the address acquisition module 12, it is previously set: if the port A, C is connected and the port B, D is connected, the address corresponds to the address of the subsequent device 31; if the port A, D is connected and the port B, C is connected, the address of the succeeding device 32 is corresponded.
When the front-stage host 20 needs to send an instruction to the rear-stage device 31, the ports A, C and B, D may be connected, as shown in the figure, at this time, the detection module 11 may identify the signal type of the port A, B through feature detection, so that the address acquisition module 12 may determine the address of the rear-stage device 31, the protocol analysis module 14 may analyze the signal on the connection line after the sequence adjustment, add the address to the analyzed signal, and output the signal to the two rear- stage devices 31 and 32, and for the rear-stage device 31, after receiving the signal sent by the interface circuit 10, determine that the signal is sent to itself according to the address therein, and may perform corresponding processing; and for the subsequent device 32, after receiving the signal sent by the interface circuit 10, it judges that the signal is not sent to itself according to the address therein, and discards it without processing.
When the front-stage host 20 needs to send an instruction to the rear-stage device 32, the ports A, D and B, C may be connected (not shown in the figure), at this time, the detection module 11 may identify the signal type of the port A, B through feature detection, so that the address acquisition module 12 may determine the address of the rear-stage device 32, the protocol analysis module 14 may analyze the signal on the connection line after the sequence adjustment, add the address to the analyzed signal, and output the signal to the two rear- stage devices 31 and 32, and for the rear-stage device 32, after receiving the signal sent by the interface circuit 10, determine that the signal is sent to itself according to the address therein, and may perform corresponding processing; and for the subsequent device 31, after receiving the signal sent by the interface circuit 10, it judges that the signal is not sent to itself according to the address in the signal, and discards the signal without processing.
As described above, when the front host 20 controls the two rear devices 31 and 32, it is not necessary to know the addresses of the two rear devices 31 and 32 in advance, and the two ports of the interface circuit 10 and the two ports of the front host 10 are connected in the forward direction or in the reverse direction, whereby the different rear devices 31 and 32 can be controlled.
In a specific embodiment, the interfaces between the devices in the communication system are I2C interfaces, wherein one of the connection lines is an SCL clock line for transmitting clock signals; the other connection line is an SDA data line which mainly transmits data or addresses. The I2C bus has several communication states: idle, start, stop, transmission of logical '0' and '1'. For example, the bus address width is 7 bits, and in conjunction with fig. 2D and 2E, the SCL clock line has more edge transitions than the SDA data line, and at least more than twice the SDA data line. Therefore, which connection line is the SCL clock line and which connection line is the SDA data line can be identified according to the frequency of edge transitions of the level signals on the SCL clock line and the SDA data line.
In this embodiment, the detecting module 10 includes a first counter, a second counter and an identifying unit, where the first counter is used for counting the number of edges of the level signal on one of the connection lines within a preset time; the second counter is used for counting the number of edges of the level signal on the other connecting line within preset time; the identification unit is used for identifying the two connecting lines as the SDA data line or the SCL clock line according to the number of edges of the two connecting lines. Preferably, the identification unit is, for example, a comparator or a divider, and in the case of the comparator, the comparator compares the number of edges of the two connection lines, and determines that the connection line with the larger number of edges is an SCL clock line and the connection line with the smaller number of edges is an SDA clock line; in the case of the divider, the comparator divides the number of edges of the first connection line by the number of edges of the second connection line, and if the result is greater than or equal to 2, the first connection line is considered to be an SCL connection line and the second connection line is considered to be an SDA data line, or vice versa.
In one specific application, the characteristic information is the number of rising edges. In addition, the detection module comprises a first counter, a second counter and an identification unit, wherein the input end of the first counter is connected with one of the connecting lines, the input end of the second counter is connected with the other connecting line, and the output ends of the first counter and the second counter are respectively connected with the identification unit. In this embodiment, for example, after a reset at a certain time, the first counter counts the rising edge on the first connection line, the second counter counts the rising edge on the second connection line, and then the comparator compares the count values of the two counters, and when the first count value is behind a certain value (for example, 8 is a threshold value) from the second count value, it may indicate that the second connection line is corresponding to SCL. Since the slave needs to reply ACK after the master sends a signal to the slave, the slave can obtain enough difference in counter value before reliable identification is not established.
In another specific application, the characteristic information is the number of falling edges. In addition, the detection module comprises a first NOT gate, a second NOT gate, a first counter, a second counter and an identification unit, wherein the input end of the first NOT gate is connected with one of the connecting lines, and the output end of the first NOT gate is connected with the input end of the first counter; the input end of the second NOT gate is connected with the other connecting wire, the output end of the second NOT gate is connected with the input end of the second counter, and the output ends of the first counter and the second counter are respectively connected with the identification unit. The working principle of this embodiment is similar to the previous embodiment, except that the falling edges of the level signal on each connection line are counted.
In yet another specific application, the characteristic information is the sum of the number of rising edges and the number of falling edges. In addition, referring to fig. 4, the detecting module includes a first delay unit 114, a second delay unit 115, a first xor gate 116, a second xor gate 117, a first counter 111, a second counter 112, and an identifying unit 113, wherein an input end of the first delay unit 114 is connected to one of the connection lines, two input ends of the first xor gate 116 are respectively connected to one of the connection lines and an output end of the first delay unit 114, and an output end of the first xor gate 116 is connected to an input end of the first counter 111; the input end of the second delay unit 115 is connected to another connection line, two input ends of the second xor gate 117 are respectively connected to another connection line and the output end of the second delay unit 115, the output end of the second xor gate 117 is connected to the input end of the second counter 112, and the output ends of the first counter 111 and the second counter 112 are respectively connected to the identification unit. The working principle of this embodiment is similar to the first two embodiments, except that the counters of the first two embodiments are triggered by a single edge, and the counters of this embodiment are triggered by a double edge, that is, the sum of the rising edge and the falling edge of the level signal on the connection line is counted.
Fig. 5 is a logic structure diagram of a first embodiment of the adjustment module in fig. 3, where the adjustment module in this embodiment includes a first switch K1 and a second switch K2, a first fixed contact of the first switch K1 and a second fixed contact of the second switch K2 are respectively connected to one of the connection lines, a second fixed contact of the first switch K1 and a first fixed contact of the second switch K2 are respectively connected to the other connection line, a movable contact of the first switch K1 and a movable contact of the second switch K2 are respectively connected to an SCL clock line and an SDA data line of the protocol analysis module, and a control end of the first switch K1 and a control end of the second switch K2 are respectively connected to the detection module. For example, as shown in fig. 5, when the port a of the interface circuit 10 is connected to the clock port (SCL) of the front host 20 and the port B is connected to the data port (SDA) of the front host 20, the moving contacts of the two switches K1 and K2 are controlled to be respectively connected to the first fixed contacts thereof, that is, no cross processing is performed at this time; when the port a of the interface circuit 10 is connected to the data port (SDA) of the front host 20 and the port B is connected to the clock port (SCL) of the front host 20, the moving contacts of the two switches K1 and K2 are controlled to be connected to the second fixed contacts thereof, that is, cross processing is performed at this time.
Furthermore, the adjusting module may further include a control unit, the detection result of the detecting module is sent to the control unit, and the control unit may further delay a specific time to control the actions of the two switches K1 and K2 after receiving the detection result, so as to prevent jitter. Further, the control unit can also control the start and stop states of the two counters, for example, when adaptive adjustment is not performed, an enable signal is sent to the two counters to start the counters to start counting; after adaptive adjustment, the two counters can be controlled to stop counting. Of course, the counter may be controlled by a later stage circuit, or the counter may be enabled in an active state all the time.
Fig. 6 is a flowchart of a first embodiment of a method for transmitting signals by an interface circuit according to the present invention, where the method for transmitting signals includes the following steps:
s10, respectively carrying out characteristic detection on signals on two connecting lines, and identifying the signal types of the two connecting lines according to the characteristic information of the two connecting lines;
s20, acquiring an address corresponding to the identification result according to a pre-stored corresponding relation between the signal type and the address;
s30, adjusting the line sequence of the two connecting lines according to the recognition result;
and S40, analyzing the signals on the two connecting wires after the line sequence is adjusted, adding the acquired address into the analyzed signals, and outputting the signals to two subsequent devices.
In one embodiment, the interface between the front host and the interface circuit is an I2C interface, and the two connection lines are an SCL clock line and an SDA data line, respectively, where the step S10 includes:
s11, counting the number of edges of the level signals on the two connecting lines within a preset time, wherein the number of the edges can be the number of rising edges, the number of falling edges or the sum of the numbers of the rising edges and the falling edges;
and S12, identifying the two connecting lines as an SDA data line or an SCL clock line according to the number of edges of the two connecting lines.
Of course, in other embodiments, when identifying the two connection lines of I2C, it may be preset that only one of the connection lines transmits a specific feature code, so that when detecting the level signals on the two connection lines, it is only necessary to detect which of the connection lines has the feature code to identify the connection line.
In another embodiment, the signals on the two connection lines are carrier signals, and in this case, the step S10 may include:
s13, respectively detecting the frequencies of carrier signals on the two connecting wires;
and S14, identifying the two connecting lines according to the frequencies of the carrier signals on the two connecting lines.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (10)
1. An interface circuit, link to each other with preceding stage host computer and two back stage equipment, its characterized in that includes:
the detection module is used for respectively carrying out characteristic detection on signals on the two connecting lines and identifying the signal types of the two connecting lines according to the characteristic information of the two connecting lines;
the address acquisition module is used for acquiring an address corresponding to the identification result according to the corresponding relation between the pre-stored signal type and the address;
the adjusting module is used for adjusting the line sequence of the two connecting lines through the selector switch according to the identification result;
the protocol analysis module is used for analyzing the signals on the two connecting lines after the line sequence is adjusted, adding the acquired address into the analyzed signals and outputting the signals to two post-stage devices;
and the two ports of the interface circuit are in positive connection or reverse connection with the two ports of the front-stage host so as to realize that the front-stage host controls the two rear-stage devices.
2. The interface circuit of claim 1, wherein the detecting module comprises:
the first counter is used for counting the number of edges of the level signal on one connecting line within preset time;
the second counter is used for counting the number of edges of the level signal on the other connecting line within preset time;
and the identification unit is used for identifying the two connecting lines as the SDA data line or the SCL clock line according to the number of the edges of the two connecting lines.
3. The interface circuit according to claim 2, wherein the number of edges is a number of rising edges, and wherein the input terminal of the first counter is connected to the one connection line and the input terminal of the second counter is connected to the other connection line.
4. The interface circuit of claim 2, wherein the number of edges is the number of falling edges, and the detection module further comprises a first not gate and a second not gate, an input terminal of the first not gate is connected to the one of the connection lines, and an output terminal of the first not gate is connected to the input terminal of the first counter; and the input end of the second NOT gate is connected with the other connecting line, and the output end of the second NOT gate is connected with the input end of the second counter.
5. The interface circuit according to claim 2, wherein the number of edges is a sum of a number of rising edges and a number of falling edges, and the detecting module further comprises a first delay unit, a second delay unit, a first xor gate and a second xor gate, wherein an input terminal of the first delay unit is connected to the one connection line, two input terminals of the first xor gate are respectively connected to the one connection line and an output terminal of the first delay unit, and an output terminal of the first xor gate is connected to an input terminal of the first counter; the input end of the second delay unit is connected with the other connecting wire, two input ends of the second exclusive-or gate are respectively connected with the other connecting wire and the output end of the second delay unit, and the output end of the second exclusive-or gate is connected with the input end of the second counter.
6. Interface circuit according to any of claims 2-5, wherein the identification unit is a comparator or a divider.
7. The interface circuit according to claim 1, wherein the switch includes a first switch and a second switch, wherein a first fixed contact of the first switch and a second fixed contact of the second switch are respectively connected to the one connection line, a second fixed contact of the first switch and a first fixed contact of the second switch are respectively connected to another connection line, a moving contact of the first switch and a moving contact of the second switch are respectively connected to an SCL clock line and an SDA data line of the protocol analysis module, and a control terminal of the first switch and a control terminal of the second switch are respectively connected to the detection module.
8. A communication system comprising a front-end host and two back-end devices, further comprising an interface circuit connected between said front-end host and said back-end devices, said interface circuit being as claimed in any one of claims 1 to 7.
9. A method for transmitting signals by an interface circuit, wherein the interface circuit is connected with a front-stage host and two back-stage devices, is characterized by comprising the following steps:
s10, respectively carrying out characteristic detection on signals on two connecting lines, and identifying the signal types of the two connecting lines according to the characteristic information of the two connecting lines;
s20, acquiring an address corresponding to the identification result according to a pre-stored corresponding relation between the signal type and the address;
s30, adjusting the line sequence of the two connecting lines through a selector switch according to the identification result;
s40, analyzing the signals on the two connecting wires after the line sequence is adjusted, adding the acquired address into the analyzed signals, and outputting the signals to two post-stage devices;
and the two ports of the interface circuit are in positive connection or reverse connection with the two ports of the front-stage host so as to realize that the front-stage host controls the two rear-stage devices.
10. The method according to claim 9, wherein the step S10 includes:
s11, counting the number of edges of the level signals on the two connecting wires within preset time;
and S12, identifying the two connecting lines as an SDA data line or an SCL clock line according to the number of edges of the two connecting lines.
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| CN111737177B (en) * | 2020-05-18 | 2022-03-18 | 大唐微电子技术有限公司 | Method and device for identifying communication interface of chip in BOOT state |
| CN111897549B (en) * | 2020-07-28 | 2024-02-20 | 北京创元成业科技有限公司 | Program burning auxiliary system, control method, electronic equipment and storage medium |
| CN114528237B (en) * | 2022-02-18 | 2023-12-12 | 南昌华勤电子科技有限公司 | Interface converter, circuit board and electronic equipment |
| CN114676078B (en) * | 2022-03-25 | 2024-08-13 | 惠州高盛达智显科技有限公司 | Automatic identification method based on UART interface signals |
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| CN201087862Y (en) * | 2006-12-29 | 2008-07-16 | 青岛海信电器股份有限公司 | IC bus commutation circuit for convergence regulation |
| CN101231628A (en) * | 2007-01-23 | 2008-07-30 | 三星电子株式会社 | Method and apparatus for controlling timing of state transition of serial data line in 12c controller |
| CN102253914A (en) * | 2011-06-02 | 2011-11-23 | 福建星网锐捷网络有限公司 | Data transmitting and processing method and device and equipment interface |
| CN103095855A (en) * | 2011-10-27 | 2013-05-08 | 无锡力芯微电子股份有限公司 | I2C communication interface unit |
| CN105446837A (en) * | 2015-04-02 | 2016-03-30 | 北京天诚盛业科技有限公司 | Method, device and system for detecting whether IIC (inter-integrated circuit) interface device is connected |
| CN105635184A (en) * | 2016-03-22 | 2016-06-01 | 青岛海信宽带多媒体技术有限公司 | Communication protocol conversion method, device and system |
| CN106126465A (en) * | 2016-06-21 | 2016-11-16 | 广东欧珀移动通信有限公司 | A kind of data transmission method and device |
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| CN109871344A (en) | 2019-06-11 |
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