CN115878523A - Network card adapting circuit, network card adapting method and related device - Google Patents
Network card adapting circuit, network card adapting method and related device Download PDFInfo
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Abstract
The network card adapting circuit is used for meeting the requirement of a flexible IO slot position on mixed insertion of a standard OCP network card and a NIC network card managed by a CPU. The method specifically comprises the following steps: the network card detection circuit, the CPLD, the switch and the CPU; the network card detection circuit is connected with the first management pin and the second pin of the CPLD; the sixth pin and the seventh pin of the CPLD are switched with the pin of the CPU by using a switch; the network card detection circuit multiplexes signals indicated by a first pin and a second pin of the CPLD into a network card detection signal, and indicates the network card inserted into the interface as a first network card managed by the CPU or a second network card under an OCP3.0 protocol according to the network card detection signal; when the network card inserted into the interface is determined to be the first network card, the third pin, the fourth pin and the fifth pin in the CPLD indicate signals corresponding to the first network card, and the switch gates the CPU, so that the CPU manages the signals corresponding to the first network card; and when the network card inserted into the interface is determined to be the first network card, the switch gates the sixth pin and the seventh pin of the CPLD, so that the pins of the CPLD indicate signals corresponding to the second network card.
Description
Technical Field
The present application relates to the field of computers, and in particular, to a network card adapting circuit, a network card adapting method, and a related apparatus.
Background
The rear window of the current Kunpeng rack server supports two input/output (IO) slots, which may be respectively used to insert an Open Computer Project (OCP) 3.0 network card and a Network Interface Card (NIC) managed by a Central Processing Unit (CPU).
The OCP3.0 network card and the NIC network card managed by the CPU have the same morphological structure in physical design, but the interface design is different due to the difference of network card management parties, so that the two network cards cannot be mixed and inserted into the IO slot position on the rear window of the server. For example, taking S920X05 server as an example, the back window supports two flexible IO slot positions 1 and 2, where the flexible IO slot position 1 only supports a standard OCP network card, and the flexible IO slot position 2 only supports an NIC network card managed by the CPU, and the two flexible IO slot positions cannot be inserted in a mixed manner.
Therefore, the configuration requirements of the client on the external network card are limited, and the requirements of two standard OCP network cards or two NIC network cards managed by the CPU cannot be met.
Disclosure of Invention
The embodiment of the application provides a network card adapting circuit, a network card adapting method and a related device, which are used for realizing the requirement of mixed insertion of a standard OCP network card and a NIC network card managed by a CPU by a flexible IO slot position.
In a first aspect, an embodiment of the present application provides a network card adapting circuit, which includes:
a network card detection circuit, a Complex Programmable Logic Device (CPLD), a switch and a CPU; the CPLD comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin and a seventh pin; the network card detection circuit is connected with the first management pin and the second management pin of the CPLD; the sixth pin and the seventh pin of the CPLD are connected with the switch; the CPU is connected with the switch; the network card detection circuit multiplexes signals indicated by the first pin and the second pin of the CPLD into a network card detection signal, and indicates the network card inserted into an interface to be a first network card managed by the CPU or a second network card under an open computing item OCP3.0 protocol according to the network card detection signal; when the network card detection signal indicates that the network card inserted into the interface is the first network card, a third pin, a fourth pin and a fifth pin in the CPLD indicate signals corresponding to the first network card, and the switch gates the CPU, so that the CPU manages the signals corresponding to the first network card; when the network card detection signal indicates that the network card inserted into the interface is the first network card, the switch gates the sixth pin and the seventh pin of the CPLD, so that the third pin, the fourth pin, the fifth pin, the sixth pin and the seventh pin in the CPLD indicate signals corresponding to the second network card.
In this embodiment, the network card adapting circuit uses the network card detecting circuit and multiplexes signals under the original OCP3.0 protocol to detect the type of the network card inserted into the interface, and uses the switch to switch the control circuit of the standard OCP network card and the control circuit of the NIC card managed by the CPU, and multiplexes related signals on the control circuit of the original OCP network card. Therefore, the network adapting circuit can multiplex the standard OCP network card and the NIC card managed by the CPU, and the requirement of the flexible IO slot position on the mixed insertion of the standard OCP network card and the NIC card managed by the CPU is met.
Optionally, the network card detection circuit includes a first branch and a second branch connected in parallel, where the first branch and the second branch are connected in parallel, and the first branch and the second branch are connected in series with the first network card detection branch and the second network card detection branch; wherein the first branch comprises a first power supply, a first resistor and a second resistor; the first resistor is connected with the second resistor in parallel; the first resistor is connected with the first pin, and the second resistor is connected with the first power supply; the second branch circuit comprises a second power supply, a third resistor, a fourth resistor and an MOS (metal oxide semiconductor) tube; the third resistor, the fourth resistor and the MOS tube are all connected in parallel; the third resistor is connected with the second pin, and the fourth resistor is connected with the second power supply; the D pole of the MOS tube is connected with the second pin through the third resistor, and the S pole of the MOS tube is grounded; the first network card detection branch comprises a fifth resistor, and the other end of the fifth resistor is grounded; the second network card detection branch comprises a sixth resistor and a seventh resistor which are connected in parallel, and the sixth resistor is connected with a third power supply; the seventh resistor is grounded; when the first network card detection branch is communicated with the first branch and the second branch, the second pin inputs a high level; and when the second network card detection branch is communicated with the first branch and the second branch, the second pin inputs a low level.
Based on the above scheme, the design of each resistor and power supply in the network card detection circuit can be as follows: the first power supply, the second power supply and the third power supply are all set to be 3v3 power supplies, the first resistor, the third resistor and the fifth resistor are all set to be 33 ohms, and the second resistor, the fourth resistor, the sixth resistor and the seventh resistor are all set to be 1000 ohms. It can be understood that, this embodiment only provides one possible design scheme of the resistor and the power supply, but the design of the resistor and the power supply is not limited, as long as it is satisfied that when the first network card detection branch is communicated with the first branch and the second branch, the second pin inputs a high level; when the second network card detection branch is communicated with the first branch and the second branch, the second pin inputs a low level condition.
Optionally, in a case of signal multiplexing between each pin of the CPLD and the CPU pin, the following may be specifically used:
the first pin is a PERST0# signal defined by an OCP3.0 protocol, and the PERST0# signal and the second pin are multiplexed into the network card detection signal;
when the network card detection signal indicates that the network card inserted into the interface is the first network card, the switch gates the CPU; the third pin and the fourth pin are used for outputting an interrupt signal; the fourth management pin is used for outputting an indication signal of a management state indicator lamp; a pin of the CPU outputs a first signal for managing an optical module and a clock data recovery chip and a second signal for managing a physical layer (PHY) chip;
when the network card detection signal indicates that the network card inserted into the interface is the second network card, the switch gates a sixth pin and a seventh pin of the CPLD; the third pin is used for outputting a PERST1# signal defined by an OCP3.0 protocol, the fourth pin is used for outputting a BIF2# signal defined by the OCP3.0 protocol, the fifth pin is used for outputting a BIF [ 1.
In a second aspect, the present application provides a network card adapting method, which is mainly applied to a computer device configured with the network adapting circuit of the first aspect, and specifically includes the following steps:
the network card detection circuit multiplexes signals indicated by a first pin and a second pin of the CPLD into a network card detection signal, and indicates the type of a network card inserted into an interface according to the network card detection signal, wherein the type of the network card is a first network card managed by a CPU or a second network card under an OCP protocol; determining a signal corresponding to the network card according to the type of the network card; and managing the network card by utilizing the signal.
In this embodiment, the network card adapting circuit uses the network card detecting circuit and multiplexes signals under the original OCP3.0 protocol to detect the type of the network card inserted into the interface, and uses the switch to switch the control circuit of the standard OCP network card and the control circuit of the NIC card managed by the CPU, and multiplexes related signals on the control circuit of the original OCP network card. Therefore, the network adapting circuit can multiplex the standard OCP network card and the NIC card managed by the CPU, and the requirement of the flexible IO slot position on the mixed insertion of the standard OCP network card and the NIC card managed by the CPU is met.
Optionally, the indicating, according to the network card detection signal, a network card type of a network card inserted into the interface includes:
when the network card detection signal indicates that the second pin of the CPLD inputs a high level, the network card type of the network card is the first network card; and when the network card detection signal indicates that the second pin of the CPLD inputs a low level, the network card type of the network card is the second network card.
Optionally, determining the signal corresponding to the network card according to the network card type includes:
when the network card type of the network card is the first network card, the switch gates the CPU; the third pin and the fourth pin are used for outputting an interrupt signal; the fourth management pin is used for outputting an indication signal of the management state indicator lamp; a pin of the CPU outputs a first signal for managing an optical module and a clock data recovery chip and a second signal for managing a physical layer (PHY) chip;
when the network card type of the network card is the second network card, the switch gates the sixth pin and the seventh pin of the CPLD; the third pin is used for outputting a PERST1# signal defined by an OCP3.0 protocol, the fourth pin is used for outputting a BIF2# signal defined by the OCP3.0 protocol, the fifth pin is used for outputting a BIF [ 1.
In a third aspect, the present application provides a computer device, where the computer device configures the network card adaptation circuit described in the first aspect.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer instructions for executing the method according to the second aspect.
In a fifth aspect, embodiments of the present application provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the second aspect.
In a sixth aspect, the present application provides a chip system, which includes a processor for supporting a network card adapting circuit to implement the functions referred to in the above aspects, such as generating or processing data and/or information referred to in the above methods. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the network card adaptation circuit to implement the functions of any one of the above aspects. The chip system may be formed by a chip, and may also include a chip and other discrete devices.
Drawings
Fig. 1 is a schematic diagram of an embodiment of a network card adapting circuit in an embodiment of the present application;
FIG. 2 is a schematic diagram of a network card detecting circuit in the embodiment of the present application;
FIG. 3 is another schematic diagram of a network card detecting circuit in an embodiment of the present application;
fig. 4 is a signal diagram of a network card adapting circuit in the embodiment of the present application;
fig. 5 is another signal diagram of the network card adapting circuit in the embodiment of the present application;
fig. 6 is a schematic diagram of an embodiment of a network card adapting method in the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application are described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. As can be known to those skilled in the art, with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be implemented in other sequences than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus. The naming or numbering of the steps appearing in the present application does not mean that the steps in the method flow have to be executed in the chronological/logical order indicated by the naming or numbering, and the named or numbered process steps may be executed in a modified order depending on the technical purpose to be achieved, as long as the same or similar technical effects are achieved. The division of the units presented in this application is a logical division, and in practical applications, there may be another division, for example, multiple units may be combined or integrated in another system, or some features may be omitted, or not executed, and in addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, and the indirect coupling or communication connection between the units may be in an electrical or other similar form, which is not limited in this application. Furthermore, the units or sub-units described as the separate parts may or may not be physically separate, may or may not be physical units, or may be distributed in a plurality of circuit units, and some or all of the units may be selected according to actual needs to achieve the purpose of the present disclosure.
The current rear window of the Kunpeng rack server supports two input/output (IO) slots, which can be respectively used for inserting an OCP3.0 network card and an NIC card managed by a CPU. The OCP3.0 network card and the NIC network card managed by the CPU have the same morphological structure in physical design, but the interface design is different due to the difference of network card management parties, so that the two network cards cannot be mixed and inserted into the IO slot position on the rear window of the server. For example, taking S920X05 server as an example, the rear window supports two flexible IO slot positions 1 and 2, where the flexible IO slot position 1 only supports a standard OCP network card, and the flexible IO slot position 2 only supports an NIC network card managed by the CPU, and the two slots cannot be inserted in a mixed manner. Therefore, the configuration requirements of the client on the external network card are limited, and the requirements of two standard OCP network cards or two NIC network cards managed by the CPU cannot be met.
In order to solve the problem, the present application provides a network card adapting circuit, which specifically includes: the system comprises a network card detection circuit, a CPLD, a switch and a CPU; the CPLD comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin and a seventh pin; the network card detection circuit is connected with the first management pin and the second management pin of the CPLD; the sixth pin and the seventh pin of the CPLD are connected with the switch; the CPU is connected with the switch; the network card detection circuit multiplexes signals indicated by the first pin and the second pin of the CPLD to be a network card detection signal, and indicates a network card inserted into an interface to be a first network card managed by the CPU or a second network card under an open computing project OCP3.0 protocol according to the network card detection signal; when the network card detection signal indicates that the network card inserted into the interface is the first network card, a third pin, a fourth pin and a fifth pin in the CPLD indicate signals corresponding to the first network card, and the switch gates the CPU, so that the CPU manages the signals corresponding to the first network card; when the network card detection signal indicates that the network card inserted into the interface is the first network card, the switch gates the sixth pin and the seventh pin of the CPLD, so that the third pin, the fourth pin, the fifth pin, the sixth pin and the seventh pin in the CPLD indicate signals corresponding to the second network card.
The network card adapting circuit in the embodiment of the present application is described below with reference to fig. 1, and as shown in fig. 1, the network card adapting circuit 100 includes a network card detecting circuit 101, a CPLD102, a switch 103, and a CPU104. The CPLD102 includes a first pin 1021, a second pin 1022, a third pin 1023, a fourth pin 1024, a fifth pin 1025, a sixth pin 1026, and a seventh pin 1027; the network card detecting circuit 101 includes the first pin 1021 and the second pin 1022 of the CPLD102, and the switch 103 is used for switching between the sixth pin 1026 and the seventh pin 1027 of the CPLD102 and the pin of the CPU104. The network card detection circuit multiplexes signals indicated by a first pin and a second pin of the CPLD to be network card detection signals, and indicates a network card inserted into an interface to be a first network card managed by the CPU or a second network card under an open computing project OCP3.0 protocol according to the network card detection signals; when the network card detection signal indicates that the network card inserted into the interface is the first network card, the third pin, the fourth pin and the fifth pin in the CPLD indicate signals corresponding to the first network card, and the switch gates the CPU, so that the CPU manages the signals corresponding to the first network card; when the network card detection signal indicates that the network card inserted into the interface is the first network card, the switch gates the sixth pin and the seventh pin of the CPLD, so that the third pin, the fourth pin, the fifth pin, the sixth pin and the seventh pin in the CPLD indicate signals corresponding to the second network card. In this embodiment, the network card adapting circuit uses the network card detecting circuit and multiplexes signals under the original OCP3.0 protocol to detect the type of the network card inserted into the interface, and uses the switch to switch the control circuit of the standard OCP network card and the control circuit of the NIC card managed by the CPU, and multiplexes related signals on the control circuit of the original OCP network card. Therefore, the network adapting circuit can multiplex the standard OCP network card and the NIC card managed by the CPU, and the requirement of the flexible IO slot position on the mixed insertion of the standard OCP network card and the NIC card managed by the CPU is met.
Under this architecture, signals output by the first pin 1021 and the second pin 1022 of the CPLD102 under the OCP3.0 protocol are multiplexed into a network card detection signal of the network card detection circuit 101, and the CPLD102 can indicate, according to the network card detection signal, that the network card inserted into the interface is the first network card directly managed by the CPU or the second network card under the standard OCP3.0 protocol. One possible implementation of the network card detecting circuit 101 may be as shown in fig. 2:
the network card detection circuit 101 comprises a first branch and a second branch which are connected in parallel, wherein the first network card detection branch and the second network card detection branch which are connected in parallel are connected in series with the first network card detection branch and the second network card detection branch which are connected in parallel; wherein the first branch comprises a first power supply, a first resistor and a second resistor; the first resistor is connected with the second resistor in parallel; the first resistor is connected with the first pin 1021, and the second resistor is connected with the first power supply; the second branch circuit comprises a second power supply, a third resistor, a fourth resistor and an MOS (metal oxide semiconductor) tube; the third resistor, the fourth resistor and the MOS tube are all connected in parallel; the third resistor is connected to the second pin 1022, and the fourth resistor is connected to the second power supply; the D pole of the MOS tube is connected with the second pin through the third resistor, and the S pole of the MOS tube is grounded; the first network card detection branch comprises a fifth resistor, and the other end of the fifth resistor is grounded; the second network card detection branch comprises a sixth resistor and a seventh resistor which are connected in parallel, and the sixth resistor is connected with a third power supply; the seventh resistor is grounded.
In the network card detecting circuit 101, one possible implementation manner of the network card detecting signal may be as follows: when the first network card detection branch is communicated with the first branch and the second branch (i.e. when the network card of the plug-in interface is the first network card under the management of the CPU), the second pin inputs a high level; when the second network card detection branch is communicated with the first branch and the second branch (i.e. the network card of the plug-in interface is the second network card under the standard OCP3.0 protocol), the second pin inputs a low level.
In the foregoing implementation manner, the specific implementation of the network card detecting circuit 101 may be as shown in fig. 3: the first power supply, the second power supply and the third power supply are all set to be 3v3 power supplies, the first resistor, the third resistor and the fifth resistor are all set to be 33 ohms, and the second resistor, the fourth resistor, the sixth resistor and the seventh resistor are all set to be 1000 ohms. Under the design scheme of the resistor and the power supply, when the network card inserted into the interface is the first network card, the partial pressure of 1000 ohm pull-up and 33 ohm pull-down is not enough to turn on the MOS tube, and the second pin receives high level, that is, the network card inserted into the interface is judged to be the first network card. When the network card inserted into the interface is the second network card, no matter the signal on the second network card is weakly pulled down, suspended or pulled up, the MOS transistor can be ensured to be turned on, and the second pin receives a low level, that is, the network card inserted into the interface is determined to be the second network card.
Although only one possible implementation manner of the network card detecting circuit 101 is provided above, the first network card and the second network card may be distinguished by different network card detecting signals, and the specific implementation manner is not limited herein.
In this embodiment, the specific implementation of the CPLD and the CPU multiplexing signal can be as shown in fig. 4 and 5:
in fig. 4, the network card inserted into the interface is the first network card managed by the CPU, and at this time, the switch gates the pin of the CPU; the third pin and the fourth pin of the CPLD output interrupt signals, the signal on the third pin may be defined as INT _ NIC _ CPLD0, and the signal on the fourth pin may be defined as INT _ NIC _ CPLD1. The fifth pin outputs an indication signal for managing a status indicator lamp, wherein the indication signal may be defined as CPLD _ NIC _ I2C. The sixth pin and the seventh pin are switched to a pin of the CPU, so that the pin of the CPU outputs a first signal for managing an optical module and a clock data recovery chip and a second signal for managing a Physical layer (PHY) chip, wherein the first signal may be defined as CPU _ NIC _ I2C, and the second signal may be defined as CPU _ NIC _ MDIO.
In fig. 5, the network card inserted into the interface is the second network card under the OCP3.0 protocol, and at this time, the switch gates the sixth pin and the seventh pin of the CPLD; the third pin is used for outputting a PERST1# signal defined by the OCP3.0 protocol, the fourth pin is used for outputting a BIF2# signal defined by the OCP3.0 protocol, the fifth pin is used for outputting a BIF [ 1.
An embodiment of the present application further provides a network card adapting method, which is mainly applied to a computer device including the network card adapting circuit described in any one of fig. 1 to 5, and specifically referring to fig. 6, the network card adapting method in the embodiment of the present application includes:
601. and acquiring the network card type of the network card inserted into the interface by using a network card detection circuit, wherein the network card type is a first network card managed by the CPU or a second network card under an OCP protocol.
After the network card is inserted into the interface, the computer equipment acquires a network card detection signal according to the network card detection circuit, and determines the type of the network card according to the network card detection signal. In one possible implementation manner, when the network card detection signal indicates that the second pin of the CPLD inputs a high level, the network card type of the network card is the first network card;
and when the network card detection signal indicates that the second pin of the CPLD inputs a low level, the network card type of the network card is the second network card.
602. And determining a signal corresponding to the network card according to the network card type.
When the network card inserted into the interface is determined to be the first network card managed by the CPU according to the network card detection signal, a switch in the network card adapting circuit gates a pin of the CPU; the third pin and the fourth pin of the CPLD output interrupt signals, the signal on the third pin may be defined as INT _ NIC _ CPLD0, and the signal on the fourth pin may be defined as INT _ NIC _ CPLD1. The fifth pin outputs an indication signal for managing a status indicator lamp, wherein the indication signal may be defined as CPU _ NIC _ I2C. The sixth pin and the seventh pin are switched to a pin of the CPU, so that the pin of the CPU outputs a first signal for managing an optical module and a clock data recovery chip and a second signal for managing a Physical layer (PHY) chip, wherein the first signal may be defined as CPU _ NIC _ I2C, and the second signal may be defined as CPU _ NIC _ MDIO.
When the network card inserted into the interface is determined to be the second network card according to the network card detection signal, a switch in the network card adapting circuit gates the sixth pin and the seventh pin of the CPLD; the third pin is used for outputting a PERST1# signal defined by the OCP3.0 protocol, the fourth pin is used for outputting a BIF2# signal defined by the OCP3.0 protocol, the fifth pin is used for outputting a BIF [ 1.
603. And managing the network card by utilizing the signal.
In this embodiment, the network card adapting circuit uses the network card detecting circuit and multiplexes signals under the original OCP3.0 protocol to detect the type of the network card inserted into the interface, and uses the switch to switch the control circuit of the standard OCP network card and the control circuit of the NIC card managed by the CPU, and multiplexes related signals on the control circuit of the original OCP network card. Therefore, the network adapting circuit can multiplex the standard OCP network card and the NIC card managed by the CPU, and the requirement of the flexible IO slot position on the mixed insertion of the standard OCP network card and the NIC card managed by the CPU is met.
An embodiment of the present application further provides a computer device, where the computer device includes the network card adapting circuit described in any one of fig. 1 to fig. 5.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware or in software instructions executed by a processor. The software instructions may consist of corresponding software modules that may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. In addition, the ASIC may reside in a terminal. Of course, the processor and the storage medium may reside as discrete components in the first communication device.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Claims (8)
1. A network card adapter circuit, comprising:
the device comprises a network card detection circuit, a complex programmable logic device CPLD, a switch and a central processing unit CPU;
the CPLD comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin and a seventh pin;
the network card detection circuit is connected with the first management pin and the second management pin of the CPLD;
the sixth pin and the seventh pin of the CPLD are connected with the switch;
the CPU is connected with the switch;
the network card detection circuit multiplexes signals indicated by the first pin and the second pin of the CPLD into a network card detection signal, and indicates the network card inserted into an interface to be a first network card managed by the CPU or a second network card under an open computing item OCP3.0 protocol according to the network card detection signal;
when the network card detection signal indicates that the network card inserted into the interface is the first network card, a third pin, a fourth pin and a fifth pin in the CPLD indicate signals corresponding to the first network card, and the switch gates the CPU, so that the CPU manages the signals corresponding to the first network card;
when the network card detection signal indicates that the network card inserted into the interface is the first network card, the switch gates the sixth pin and the seventh pin of the CPLD, so that the third pin, the fourth pin, the fifth pin, the sixth pin and the seventh pin in the CPLD indicate signals corresponding to the second network card.
2. The network card adapting circuit according to claim 1, wherein the network card detecting circuit comprises a first branch and a second branch connected in parallel, the first network card detecting branch and the second network card detecting branch connected in parallel, the first branch and the second branch connected in parallel are connected in series with the first network card detecting branch and the second network card detecting branch connected in parallel;
wherein the first branch comprises a first power supply, a first resistor and a second resistor; the first resistor is connected with the second resistor in parallel; the first resistor is connected with the first pin, and the second resistor is connected with the first power supply;
the second branch circuit comprises a second power supply, a third resistor, a fourth resistor and an MOS (metal oxide semiconductor) tube; the third resistor, the fourth resistor and the MOS tube are all connected in parallel; the third resistor is connected with the second pin, and the fourth resistor is connected with the second power supply; the D pole of the MOS tube is connected with the second pin through the third resistor, and the S pole of the MOS tube is grounded;
the first network card detection branch comprises a fifth resistor, and the other end of the fifth resistor is grounded;
the second network card detection branch comprises a sixth resistor and a seventh resistor which are connected in parallel, and the sixth resistor is connected with a third power supply; the seventh resistor is grounded;
when the first network card detection branch is communicated with the first branch and the second branch, the second pin inputs a high level;
and when the second network card detection branch is communicated with the first branch and the second branch, the second pin inputs a low level.
3. The network card adapter circuit of claim 2, wherein the first power supply, the second power supply, and the third power supply are all set to a 3v3 power supply, the first resistor, the third resistor, and the fifth resistor are all set to 33 ohms, and the second resistor, the fourth resistor, the sixth resistor, and the seventh resistor are all set to 1000 ohms.
4. The network card adapter circuit of any one of claims 1-3, wherein the first pin is a PERST0# signal defined by OCP3.0 protocol, and the PERST0# signal and the second pin are multiplexed into the network card detection signal;
when the network card detection signal indicates that the network card inserted into the interface is the first network card, the switch gates the CPU; the third pin and the fourth pin are used for outputting an interrupt signal; the fourth management pin is used for outputting an indication signal of a management state indicator lamp; a pin of the CPU outputs a first signal for managing an optical module and a clock data recovery chip and a second signal for managing a physical layer (PHY) chip;
when the network card detection signal indicates that the network card inserted into the interface is the second network card, the switch gates a sixth pin and a seventh pin of the CPLD; the third pin is used for outputting a PERST1# signal defined by an OCP3.0 protocol, the fourth pin is used for outputting a BIF2# signal defined by the OCP3.0 protocol, the fifth pin is used for outputting a BIF [ 1.
5. A computer device, characterized in that it is equipped with a network card adaptation circuit according to any one of claims 1 to 4.
6. A network card adapting method applied to a computer device including the network card adapting circuit according to any one of claims 1 to 4, comprising:
acquiring the network card type of a network card inserted into an interface by using a network card detection circuit, wherein the network card type is a first network card managed by a CPU (central processing unit) or a second network card under an OCP (optical communications protocol) protocol;
determining a signal corresponding to the network card according to the type of the network card;
and managing the network card by utilizing the signal.
7. The method of claim 6, wherein the detecting, by the network card detection circuit, the network card type of the network card inserted into the interface comprises:
acquiring a network card detection signal corresponding to the network card;
when the network card detection signal indicates that the second pin of the CPLD inputs a high level, the network card type of the network card is the first network card;
and when the network card detection signal indicates that the second pin of the CPLD inputs a low level, the network card type of the network card is the second network card.
8. The method according to claim 6 or 7, wherein determining the signal corresponding to the network card according to the network card type comprises:
when the network card type of the network card is the first network card, the switch gates the CPU; the third pin and the fourth pin are used for outputting an interrupt signal; the fourth management pin is used for outputting an indication signal of the management state indicator lamp; a pin of the CPU outputs a first signal for managing an optical module and a clock data recovery chip and a second signal for managing a physical layer PHY chip;
when the network card type of the network card is the second network card, the switch gates a sixth pin and a seventh pin of the CPLD; the third pin is used for outputting a PERST1# signal defined by the OCP3.0 protocol, the fourth pin is used for outputting a BIF2# signal defined by the OCP3.0 protocol, the fifth pin is used for outputting a BIF [ 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111129484.6A CN115878523A (en) | 2021-09-26 | 2021-09-26 | Network card adapting circuit, network card adapting method and related device |
| PCT/CN2022/096162 WO2023045389A1 (en) | 2021-09-26 | 2022-05-31 | Network card adaptation circuit, network card adaptation method, and related apparatus |
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| CN202111129484.6A CN115878523A (en) | 2021-09-26 | 2021-09-26 | Network card adapting circuit, network card adapting method and related device |
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| CN115878523A true CN115878523A (en) | 2023-03-31 |
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| CN202111129484.6A Pending CN115878523A (en) | 2021-09-26 | 2021-09-26 | Network card adapting circuit, network card adapting method and related device |
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| WO (1) | WO2023045389A1 (en) |
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| CN108347351B (en) * | 2018-01-26 | 2022-02-22 | 广州视源电子科技股份有限公司 | Method, device and system for compatibility of dual Ethernet cards of equipment |
| CN111901164B (en) * | 2020-07-17 | 2023-04-28 | 浪潮电子信息产业股份有限公司 | Adaptive control method, device, equipment and system of OCP NIC network card |
| CN112068784B (en) * | 2020-09-14 | 2024-03-12 | 上海商米科技集团股份有限公司 | Method for automatically switching multiple network cards of cloud printing equipment and cloud printing equipment |
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