CN116860672B - Digital processing SMBus communication system and method - Google Patents
Digital processing SMBus communication system and method Download PDFInfo
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- CN116860672B CN116860672B CN202310811954.XA CN202310811954A CN116860672B CN 116860672 B CN116860672 B CN 116860672B CN 202310811954 A CN202310811954 A CN 202310811954A CN 116860672 B CN116860672 B CN 116860672B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention provides a digital processing SMBus communication system, which comprises a host computer and a slave computer which are connected through a bidirectional SMBclk interface and a SMBdat interface; when signals are input, the SMBdat interface is sequentially connected with the first synchronization module, the first filtering module and the input delay module, and SMBdat input signals are input into the control module of the SMBus slave after synchronization, filtering and delay processing; the SMBclk interface is sequentially connected with a second synchronization module and a second filtering module, and SMBclk input signals are input into a control module of the slave machine after synchronization and filtering treatment; when the signal is output, the SMBdat interface output signal of the slave is input to the host after being delayed by the output delay module. The invention can filter burrs of bus input signals and delay the input signals, and can effectively avoid the error judgment of start or stop information of the SMBus slave.
Description
Technical Field
The invention relates to the field of SMBus communication, in particular to a digital processing SMBus communication system and a digital processing SMBus communication method.
Background
SMBus is used for low rate communications in mobile PC and desktop PC systems. It is mainly desirable to control the devices on the motherboard and collect the corresponding information via an inexpensive and powerful bus (consisting of two wires). The SMBus provides a control bus for such tasks as system and power management, and the system using the SMBus can save the pin count of the device by using the SMBus to send and receive messages between the devices instead of using separate control lines.
The SMBus protocol has two interfaces, SMBclk and SMBdat respectively, which are both bi-directional interfaces. At 400KHz, the protocol specifies ① that they have a spike (spike) of up to 50ns, and that the falling edge of ② SMBclk may coincide with the arrival of the changing edge (up and down edge) of SMBdat at the chip pins, and that both the rising and falling edge durations of ③ SMBclk and SMBdat may be up to 300ns. The impact of these three factors needs to be considered when designing an SMBus communication interface. Existing solutions are not fully considered.
Disclosure of Invention
Aiming at the problems in the prior art, the system and the method for digitally processing the SMBus communication are provided, and the transmission errors caused by the factors mentioned in the background art can be effectively avoided by digitally processing the input and output signals.
The first aspect of the invention provides a digital processing SMBus communication system, which comprises an SMBus host and an SMBus slave which are connected through a bidirectional SMBclk interface and a SMBdat interface;
When signals are input, the SMBdat interface is sequentially connected with the first synchronization module, the first filtering module and the input delay module, and SMBdat input signals are input into the control module of the SMBus slave after synchronization, filtering and delay processing; the SMBclk interface is sequentially connected with a second synchronization module and a second filtering module, and SMBclk input signals are input into a control module of the SMBus slave machine after synchronization and filtering treatment;
when the signal is output, the SMBdat interface output signal of the SMBus slave is input to the SMBus host after being delayed by the output delay module.
As a preferable scheme, the first synchronization module and the second synchronization module are the same, and two-stage synchronization is realized.
As a preferred solution, the first filtering module is the same as the second filtering module, and includes: register DFF1, exclusive or gate, counting module, register DFF2; the clock signal hclk is input to the register DFF1, the counting module and the CK end of the register DFF2 at the same time, the input signals are input to the D end of the register DFF1 and the first input end of the exclusive-or gate respectively, the output end Q of the register DFF1 is connected to the second input end of the exclusive-or gate and the D end of the register DFF2, the output end of the exclusive-or gate is connected to the counting module, and the output end of the counting module is connected to the enabling end of the register DFF2; when the output end of the exclusive-or gate is at a high level, the counting module clears the count; when the exclusive or gate output terminal is at a low level, 1 is added every hclk cycles, and an enable signal is output when the count reaches a set value, allowing the register DFF2 to output a Q terminal signal of the register DFF1 from a Q terminal of the register DFF 2.
As a preferable scheme, the counter comprises a first 2-1-choice data selector, a second 2-1-choice data selector, a counter count, an adder and a judging module, wherein the selection end of the first 2-1-choice data selector is connected to the output end of the exclusive-OR gate, the output end of the first 2-1-choice data selector is connected to the input end of the counter count, the output end of the counter count is respectively connected to the second input end of the second 2-1-choice data selector, the adder is added by 1 and then connected to the first input end of the second 2-1-choice data selector, and the output end of the second 2-1-choice data selector is connected to the first input end of the first 2-1-choice data selector; the second input end of the first 2-selected 1 data selector is connected with 0; the output end of the judging module is respectively connected to the selection end of the second 2-choice-1 data selector and the enabling end of the register DFF2, and the judging module is used for judging whether the input value is equal to the set value or not and outputting the set value when the input value is equal to the set value.
As a preferred solution, the input delay module includes 8 cascaded D flip-flops and 8-to-1 data selectors, the same clock signal hclk is respectively connected to CK ends of the 8D flip-flops, and output ends of the 8D flip-flops are respectively connected to 8 input ends of the 8-to-1 data selectors; the data selecting end of the 8-select 1 data selector is provided with input from the outside, and signals are output through the output end after the time of the required delay is selected.
As a preferred solution, the output delay module includes 64 cascaded D flip-flops and 64 select 1 data selectors, the same clock signal hclk is respectively connected to CK ends of the 64D flip-flops, and output ends of the 64D flip-flops are respectively connected to 64 input ends of the 64 select 1 data selectors; the data selection terminal of the 64-select 1 data selector is externally provided with an input, and signals are output through the output terminal after the time of the required delay is selected.
In the second aspect of the invention, a digital processing SMBus communication method is provided, when signals are input, SMBclk input signals are input into an SMBus control module after two-stage synchronization and then filtered, SMBdat input signals are input into the SMBus control module after two-stage synchronization and then filtered and then delayed; when outputting the signal, the SMBdat signal is delayed and then output.
As a preferred scheme, the filtering process is as follows: comparing the input signal with the Q end signal of the register DFF1 by using an exclusive OR gate by beating the input signal SMBclk, SMBdat by using the register DFF1, outputting a high level if the input signal is inconsistent with the Q end signal of the register DFF1, and resetting the counter; if the signals are consistent, a low level is output, 1 is added to each clock period of the counter until the time reaches 50ns, the counter is kept, and a Q-terminal signal of the register terminal DFF1 is output to finish filtering.
As a preferred solution, the delay processing is implemented by using a plurality of cascaded D flip-flops and a data selector.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows:
(1) The method can filter burrs of the SMBus bus input signals and avoid the error judgment of start or stop information of the SMBus slave.
(2) The SMBdat input signal may be delayed to avoid the slave device misjudging the start or stop information in the case SMBclk, SMBdat arrives at the slave device pin at the same time.
(3) The slave device may delay driving SMBdat the output signal after SMBclk falling edges to avoid misjudging start or stop information due to SMBdat arriving in advance if the other slave devices sample the SMBclk falling edge with a lower threshold.
Drawings
Fig. 1 is a schematic diagram of a conventional SMBus device connection.
Fig. 2 is a schematic diagram of SMBus input signal processing in the present invention.
Fig. 3 is a schematic diagram illustrating a filter module according to an embodiment of the invention.
FIG. 4 is a schematic diagram of an input delay module according to an embodiment of the invention.
FIG. 5 is a schematic diagram of an output delay module according to an embodiment of the invention.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar modules or modules having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. On the contrary, the embodiments of the application include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.
As illustrated in the SMBus device connection schematic of fig. 1, the SMBus master (master) and SMBus slave (slave) connections may access the SMBus slave through bi-directional interfaces SMBclk, SMBdat, the SMBus master, and the SMBus slave may also control other slaves through SMBclk, SMBdat, or the master. The invention provides a digital processing SMBus communication system based on the realization of the system, which comprises the following specific schemes:
When signals are input, the SMBdat interface is sequentially connected with the first synchronization module, the first filtering module and the input delay module, and SMBdat input signals are input into the control module of the SMBus slave after synchronization, filtering and delay processing; the SMBclk interface is sequentially connected with a second synchronization module and a second filtering module, and SMBclk input signals are input into a control module of the SMBus slave machine after synchronization and filtering treatment;
when the signal is output, the SMBdat interface output signal of the SMBus slave is input to the SMBus host after being delayed by the output delay module.
For the input portion design, as shown in fig. 2, the SMBus bus signal SMBclk, SMBdat is two-stage synchronized by the synchronization module sync and then passes through the filter module filter. And SMBdat inputs signals, and the signals are processed by an input delay module delay in, and then enter a control module smbus control, and the module finishes analysis and driving of SMBbus signals.
The first synchronization module and the second synchronization module through which SMBclk, SMBdat input signals pass have the same functions, and two-stage synchronization is realized.
Similarly, in this embodiment, the first filtering module is the same as the second filtering module, please refer to fig. 3, which proposes an implementation manner of the filtering module, where the filtering module includes a register DFF1, an exclusive or gate xor, a counting module, and a register DFF2; the clock signal hclk is input to the register DFF1, the counting module and the CK end of the register DFF2 at the same time, the input signals are input to the D end of the register DFF1 and the first input end of the exclusive-or gate respectively, the output end Q of the register DFF1 is connected to the second input end of the exclusive-or gate and the D end of the register DFF2, the output end of the exclusive-or gate is connected to the counting module, and the output end of the counting module is connected to the enabling end of the register DFF 2.
The exclusive or gate xor is used for comparing the input signal with the signal of the register Q end of the DFF1, if the input signal is inconsistent, it indicates that the input signal has a rising edge or a falling edge, and the edge signal output by the exclusive or gate will generate a high level pulse with hclk cycles, the pulse clears the counting module, and if the input signal does not generate a rising edge or a falling edge, the edge output by the exclusive or gate is kept at a low level, in this case, the counting module will automatically increment 1 every hclk cycles, and when the count reaches the set value, an enable signal is output, and the register DFF2 is allowed to output the Q end signal of the register DFF1 from the Q end of the register DFF 2.
Further, for the counting module, a preferred implementation manner is provided in this embodiment, the counting module includes a first 2-1-choice data selector, a second 2-1-choice data selector, a counter count, an adder and a judging module, where the selection end of the first 2-1-choice data selector is connected to the output end of the exclusive-OR gate, the output end of the first 2-1-choice data selector is connected to the input end of the counter count, the output end of the counter count is respectively connected to the second input end (1 end of mux2 in fig. 3) of the second 2-1-choice data selector, the added 1 is connected to the first input end (0 end of mux2 in fig. 3) of the second 2-1-choice data selector, and the output end of the second 2-1-choice data selector is connected to the first input end (0 end of mux1 in fig. 3) of the first 2-1-choice data selector; the second input end (1 end of mux1 in fig. 3) of the first 2-selected 1 data selector is connected with 0; the output end of the judging module is respectively connected to the selection end of the second 2-choice-1 data selector and the enabling end of the register DFF2, and the judging module is used for judging whether the input value is equal to the set value or not and outputting the set value when the input value is equal to the set value. Wherein the counter count may be implemented using a register.
The maximum spike time specified in the SMBus spec document is tSPIKE equal to 50ns, so 50ns is filtered, so the counter remains unchanged after timing to 50ns, and an enable signal is output to the register DFF2 enable. In this embodiment, assuming hclk is 200mhz, i.e., a period of 5ns, a counter count of 10 is required to remove 50ns burrs, and thus a 4bit counter count is required. If the count has not counted to 10, a new rising or falling edge occurs in the input signal, then the edge generates a new high pulse signal, then the count is cleared and then counted again. If count reaches 10, register DFF2 will signal the Q terminal of register DFF 1.
It should be noted that, in practical applications, the setting value of the counter may be configured by filter_sel [3:0] to adapt to hclk of different frequencies.
Since the SMBus standard protocol specifies that the SMBclk falling edge and the SMBdat rising and falling edges issued by the host may reach the device chip pins at the same time, if the path of the SMBdat input signal propagating in the slave device chip is relatively short, the start/stop information will be misjudged, so that the SMBdat input signal needs to be delayed in the digital module to avoid misjudgment, in this embodiment, please refer to fig. 4, an input delay module is provided, where the input delay module includes 8 cascaded D flip-flops and 8-select 1 data selectors, the same clock signal hclk is respectively connected to CK ends of the 8D flip-flops, and output ends of the 8D flip-flops are respectively connected to 8 input ends of the 8-select 1 data selector; the data selecting end of the 8-select 1 data selector is provided with input from the outside, and signals are output through the output end after the time of the required delay is selected.
In practical applications, the data selection end of the smbdai _delay_sel [2:0] to 8-1 data selector can be configured, and the SMBdat signal is sent to the smbus control control unit after 1-8 hclk cycles of selection delay.
While at output, since the slope of the falling edge of SMBclk may be small, the time to fall from high to low may reach 300ns at maximum, different SMBus devices may not sample the falling edge for a threshold level, and since SMBdat is driven at SMBclk falling edge when the SMBus slave device is replying to an ACK/NACK signal, or feeding back read data to the SMBus master device, if we set a falling edge threshold level higher than the thresholds set by other SMBus devices, and we do not delay SMBdat output, then we may detect SMBdat signal we output just before other SMBus devices check SMBclk falling edge, and if SMBdat signal is flipped, then other SMBus devices may misjudge start/stop information.
Therefore, in this embodiment, as shown in fig. 5, an output delay module is provided, where the output delay module includes 64 cascaded D flip-flops and 64 select 1 data selectors, the same clock signal hclk is respectively connected to CK ends of the 64D flip-flops, and output ends of the 64D flip-flops are respectively connected to 64 input ends of the 64 select 1 data selectors correspondingly; the data selection terminal of the 64-select 1 data selector is externally provided with an input, and signals are output through the output terminal after the time of the required delay is selected.
In practical application, the data selection end of the smbdao _delay_sel [5:0] to 64 select 1 data selector can be configured, and after 1-64 hclk periods are delayed, SMBdat output signals are sent to the chip pins of the slave device.
The invention has the following advantages:
1. Burrs of the SMBus bus input signal can be filtered, and the error judgment of start or stop information by the SMBus slave is avoided.
2. The SMBdat input signal may be delayed to avoid the slave device misjudging the start or stop information in the case SMBclk, SMBdat arrives at the slave device pin at the same time.
The slave device may delay driving SMBdat the output signal after SMBclk falling edges to avoid misjudging start or stop information due to SMBdat arriving in advance if the other slave devices sample the SMBclk falling edge with a lower threshold.
Example 1
The embodiment provides a digital processing SMBus communication system, which comprises an SMBus host and an SMBus slave which are connected through a bidirectional SMBclk interface and a SMBdat interface;
When signals are input, the SMBdat interface is sequentially connected with the first synchronization module, the first filtering module and the input delay module, and SMBdat input signals are input into the control module of the SMBus slave after synchronization, filtering and delay processing; the SMBclk interface is sequentially connected with a second synchronization module and a second filtering module, and SMBclk input signals are input into a control module of the SMBus slave machine after synchronization and filtering treatment;
when the signal is output, the SMBdat interface output signal of the SMBus slave is input to the SMBus host after being delayed by the output delay module.
Example 2
Based on embodiment 1, in this embodiment, the first synchronization module and the second synchronization module are the same, and two-stage synchronization is implemented.
Example 3
On the basis of embodiment 1, in this embodiment, the first filtering module is the same as the second filtering module, and includes: register DFF1, exclusive or gate, counting module, register DFF2; the clock signal hclk is input to the register DFF1, the counting module and the CK end of the register DFF2 at the same time, the input signals are input to the D end of the register DFF1 and the first input end of the exclusive-or gate respectively, the output end Q of the register DFF1 is connected to the second input end of the exclusive-or gate and the D end of the register DFF2, the output end of the exclusive-or gate is connected to the counting module, and the output end of the counting module is connected to the enabling end of the register DFF2; when the output end of the exclusive-OR gate is at a high level, the counter is cleared; when the exclusive or gate output terminal is at a low level, 1 is added every hclk cycles, and an enable signal is output when the count reaches a set value, so that the register DFF2 is allowed to output a Q terminal signal of the register DFF1 from a Q terminal of the register DFF 2.
Example 4
Based on embodiment 3, the counter in this embodiment includes a first 2-1-out-of-2 data selector, a second 2-1-out-of-2 data selector, a counter count, an adder, and a judgment module, where the selection end of the first 2-1-out-of-2 data selector is connected to the output end of the exclusive-OR gate, the output end of the first 2-1-out-of-2 data selector is connected to the input end of the counter count, the output end of the counter count is connected to the second input end of the second 2-1-out-of-2 data selector, and after adding 1, is connected to the first input end of the second 2-1-out-of-2 data selector, and is connected to the judgment module, and the output end of the second 2-1-out-of-2 data selector is connected to the first input end of the first 2-1-out-of-2 data selector; the second input end of the first 2-selected 1 data selector is connected with 0; the output end of the judging module is respectively connected to the selection end of the second 2-choice-1 data selector and the enabling end of the register DFF2, and the judging module is used for judging whether the input value is equal to the set value or not and outputting the set value when the input value is equal to the set value.
Example 5
Based on embodiment 1, the input delay module in this embodiment includes 8 cascaded D flip-flops and 8-by-1 data selectors, the same clock signal hclk is respectively connected to CK ends of the 8D flip-flops, and output ends of the 8D flip-flops are respectively connected to 8 input ends of the 8-by-1 data selectors; the data selecting end of the 8-select 1 data selector is provided with input from the outside, and signals are output through the output end after the time of the required delay is selected.
Example 6
Based on embodiment 1, the output delay module in this embodiment includes 64 cascaded D flip-flops and 64 select 1 data selectors, the same clock signal hclk is respectively connected to CK ends of the 64D flip-flops, and output ends of the 64D flip-flops are respectively connected to 64 input ends of the 64 select 1 data selectors; the data selection terminal of the 64-select 1 data selector is externally provided with an input, and signals are output through the output terminal after the time of the required delay is selected.
Example 7
The embodiment provides a digital processing SMBus communication method, when signals are input, SMBclk input signals are input into an SMBus control module after two-stage synchronization and then filtered, SMBdat input signals are input into the SMBus control module after two-stage synchronization and then filtered and then delayed; when outputting the signal, the SMBdat signal is delayed and then output.
Example 8
On the basis of embodiment 7, the filtering process in this embodiment is: comparing the input signal with the Q end signal of the register DFF1 by using an exclusive OR gate by beating the input signal SMBclk, SMBdat by using the register DFF1, outputting a high level if the input signal is inconsistent with the Q end signal of the register DFF1, and resetting the counter; if the signals are consistent, a low level is output, 1 is added to each clock period of the counter until the time reaches 50ns, the counter is kept, and a Q-terminal signal of the register terminal DFF1 is output to finish filtering.
Example 9
Based on embodiment 7, the delay processing in this embodiment is implemented by using a plurality of cascaded D flip-flops and a data selector.
The present invention can be preferably realized by examples 1 to 9.
It should be noted that, in the description of the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention will be understood in detail by those skilled in the art; the accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (7)
1. A digital processing SMBus communication system, which is characterized by comprising an SMBus host and an SMBus slave which are connected through a bidirectional SMBclk interface and a SMBdat interface;
When signals are input, the SMBdat interface is sequentially connected with the first synchronization module, the first filtering module and the input delay module, and SMBdat input signals are input into the control module of the SMBus slave after synchronization, filtering and delay processing; the SMBclk interface is sequentially connected with a second synchronization module and a second filtering module, and SMBclk input signals are input into a control module of the SMBus slave machine after synchronization and filtering treatment;
when the signal is output, the SMBdat interface output signal of the SMBus slave machine is output to the SMBus host machine after being delayed by the output delay module;
The first filtering module is the same as the second filtering module, and comprises: register DFF1, exclusive or gate, counting module, register DFF2; the clock signal hclk is input to the register DFF1, the counting module and the CK end of the register DFF2 at the same time, the input signals are input to the D end of the register DFF1 and the first input end of the exclusive-or gate respectively, the output end Q of the register DFF1 is connected to the second input end of the exclusive-or gate and the D end of the register DFF2, the output end of the exclusive-or gate is connected to the counting module, and the output end of the counting module is connected to the enabling end of the register DFF2; when the output end of the exclusive-or gate is at a high level, the counting module clears the count; when the exclusive or gate output terminal is at a low level, 1 is added every hclk cycles, an enable signal is output when the count reaches a set value, the register DFF2 is allowed to output a Q terminal signal of the register DFF1 from a Q terminal of the register DFF2, and the counter holds the current count value DFF.
2. The digital processing SMBus communication system according to claim 1, wherein said first synchronization module and said second synchronization module are identical to each other and each achieve two-stage synchronization.
3. The digital processing SMBus communication system according to claim 2, wherein said counter comprises a first 2-1 data selector, a second 2-1 data selector, a counter count, an adder, and a judgment module, said first 2-1 data selector having its selection end connected to an exclusive or gate output, said first 2-1 data selector having its output end connected to an input of the counter count, said counter count output end connected to a second input of the second 2-1 data selector, to a first input of the second 2-1 data selector after adding 1 via the adder, and to the judgment module, said second 2-1 data selector having its output end connected to the first input of the first 2-1 data selector; the second input end of the first 2-selected 1 data selector is connected with 0; the output end of the judging module is respectively connected to the selection end of the second 2-choice-1 data selector and the enabling end of the register DFF2, and the judging module is used for judging whether the input value is equal to the set value or not and outputting the set value when the input value is equal to the set value.
4. The digital processing SMBus communication system according to claim 1, wherein said input delay module comprises 8 cascaded D flip-flops and a 1-from-8 data selector, the same clock signal hclk being respectively connected to CK terminals of the 8D flip-flops, and output terminals of the 8D flip-flops being respectively connected to 8 input terminals of the 1-from-8 data selector; the data selecting end of the 8-select 1 data selector is provided with input from the outside, and signals are output through the output end after the time of the required delay is selected.
5. The digital processing SMBus communication system according to claim 1, wherein said output delay module comprises a plurality of cascaded D flip-flops and a plurality of data selector 1, wherein the same clock signal hclk is respectively connected to CK terminals of the plurality of D flip-flops, and output terminals of the plurality of D flip-flops are respectively connected to 64 input terminals of the data selector 1; the data selection terminal of the 64-select 1 data selector is externally provided with an input, and signals are output through the output terminal after the time of the required delay is selected.
6. A digital processing SMBus communication method is characterized in that when signals are input, SMBclk input signals are input into an SMBus control module after two-stage synchronization and filtering, SMBdat input signals are input into the SMBus control module after two-stage synchronization, filtered and delayed; when outputting signals, carrying out delay processing on SMBdat signals and then outputting the signals; the filtering process is as follows: comparing the input signal with the Q end signal of the register DFF1 by using an exclusive OR gate by beating the input signal SMBclk, SMBdat by using the register DFF1, outputting a high level if the input signal is inconsistent with the Q end signal of the register DFF1, and resetting the counter; if the signals are consistent, a low level is output, 1 is added to each clock period of the counter until the time reaches 50ns, the counter is kept, and a Q-terminal signal of the register terminal DFF1 is output to finish filtering.
7. The digital processing SMBus communication method as in claim 6, wherein said delay processing is implemented using a plurality of cascaded D flip-flops and data selectors.
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