CN105790873B - Keep the clockwork and method of clock - Google Patents
Keep the clockwork and method of clock Download PDFInfo
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- CN105790873B CN105790873B CN201410837161.6A CN201410837161A CN105790873B CN 105790873 B CN105790873 B CN 105790873B CN 201410837161 A CN201410837161 A CN 201410837161A CN 105790873 B CN105790873 B CN 105790873B
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- clock
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- chain circuit
- clockwork
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Abstract
The invention discloses a kind of clockworks for keeping clock, the clockwork includes: clock interface module and clock processing module, wherein, the clock interface module, for monitoring received clock chain circuit signal, when judging the clock chain circuit abnormal signal, the clock output of the clock interface module is closed；The clock processing module, for when the clock output for detecting the clock interface module is in close state, into clock hold mode, output system clock.The invention also discloses a kind of clock keeping methods of clockwork.The present invention shortens to greatest extent from clock interface module and detects that clock chain circuit abnormal signal enters to clock processing module the time of clock hold mode, to greatly reduce the frequency hopping of clock processing module output system clock, and control within 1ppb, to meet the retention property that clockwork should have.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of clockworks and method for keeping clock.
Background technique
At present in terms of synchronous digital system clock transmission, the clock tranmission techniques based on Ethernet have obtained increasingly wider
General application, output clock performance have been able to satisfy International Telecommunication Union's telecommunication standardsization tissue (ITU-T for substantially
ITU Telecommunication Standardization Sector) defined clock characteristic.But due to application scenarios
Changeful, application mode is also all kinds of, and clock performance need to be improved under some application scenarios.For example, when upstream
When clock equipment transmits clock to downstream clockwork by Ethernet, if link is broken suddenly or clock suddenly disappears, ITU-T
Standard requirements downstream clockwork can enter holding mode i.e. clock hold mode, and precision is kept to meet as defined in standard
Performance requirement.
Existing common mode is downstream clock interface equipment after detecting the clock losing lock in link, then sends not
After downstream clock processing equipment, downstream clock processing equipment being given to receive the DNU information with clock quality class information DNU,
It needs to parse the DNU information, holding mode can be just entered after being parsed.In this way, in downstream clock interface equipment
Detect that the clock losing lock in link needs to believe by DNU during downstream clock processing equipment enters holding mode
The operating processes such as the forwarding and parsing of breath, meanwhile, the locking source of downstream clock processing equipment becomes this from original link clock
Ground crystal oscillator, so that output clock jumps, system clock also jumps therewith.It finds after tested, in downstream clock interface equipment
Detect the clock losing lock in link, the forwarding and parsing operation by DNU information are entered until downstream clock processing equipment
The time that the process of holding mode needs to spend is ms (millisecond) grade, so that system clock generates ppm grades of frequency hopping, it can not
Meet the retention property that the downstream clockwork of ITU-T standard requirement should have.
Above content is only used to facilitate the understanding of the technical scheme, and is not represented and is recognized that above content is existing skill
Art.
Summary of the invention
The main purpose of the present invention is to provide a kind of clockworks and method for keeping clock, are set with solving existing clock
The technical issues of standby middle system clock jump spends overlong time.
To achieve the above object, a kind of clockwork keeping clock provided by the invention, when the clockwork includes:
Clock interface module and clock processing module, wherein
The clock interface module, for monitoring received clock chain circuit signal, when judging that the clock chain circuit signal is different
Chang Shi closes the clock output of the clock interface module；
The clock processing module, for being in close state when the clock output for detecting the clock interface module
When, into clock hold mode, output system clock.
Preferably, the clock interface module includes: detection unit, clock driver cell, wherein
The detection unit, for receiving and detecting the clock chain circuit signal of upstream clock equipment transmission, described in judgement
When the abnormal state of clock chain circuit signal, switch control signal is sent to the clock driver cell；
The clock driver cell, the clock for closing the clock interface module according to the switch control signal are defeated
Out.
Preferably, the clock interface module further include:
Filter unit, for being judged as that the abnormal clock chain circuit signal carries out noise filtering to through the detection unit
Processing, and to through noise filtering, treated that the clock chain circuit signal detects.
Preferably, the clock processing module is specifically used for:
When detecting that the clock interface module is without clock output within a preset time using phase-locked loop circuit, when entrance
Clock hold mode, output system clock.
Preferably, the clock chain circuit signal is ethernet signal or second pulse signal.
In addition, to achieve the above object, the present invention also provides a kind of clock keeping method of clockwork, the clock is set
Standby includes: clock interface module and clock processing module, be the described method comprises the following steps:
The received clock chain circuit signal of clock interface module monitors, when judging the clock chain circuit abnormal signal,
Close the clock output of the clock interface module；
The clock processing module enters when the clock output for detecting the clock interface module is in close state
Clock hold mode, output system clock.
Preferably, the received clock chain circuit signal of the clock interface module monitors, when judging the clock chain circuit signal
When abnormal, the step of closing the clock output of the clock interface module, includes:
The clock interface module receives and detects the clock chain circuit signal of upstream clock equipment transmission, when judging described
When the abnormal state of clock link signal, switch control signal is generated, and the clock is closed according to the switch control signal and is connect
The clock output of mouth mold block.
Preferably, the received clock chain circuit signal of the clock interface module monitors, when judging the clock chain circuit signal
When abnormal, the step of closing the clock output of the clock interface module further include:
Noise filtering processing is carried out to the clock chain circuit signal for being judged as abnormal, and to treated through noise filtering
The clock chain circuit signal is detected.
Preferably, the clock processing module, which is worked as, detects that the clock output of the clock interface module is in close state
When, into clock hold mode, the step of output system clock, is specifically included:
When detecting that the clock interface module is without clock output within a preset time using phase-locked loop circuit, when entrance
Clock hold mode, output system clock.
Preferably, the clock chain circuit signal is ethernet signal or second pulse signal.
A kind of clockwork and method keeping clock proposed by the present invention, passes through the clock interface module in clockwork
When the clock chain circuit signal for detecting that upstream clock equipment is sent occurs abnormal, the clock for closing the clock interface module is defeated
Out；In this way, the clock processing module in clockwork is in the clock output for detecting the clock interface module and closes shape
When state, you can learn that clock chain circuit abnormal signal, then immediately enter clock hold mode, output system clock, without clock
For interface module when detecting clock chain circuit abnormal signal, Xiang Shizhong processing module sends DNU information, and clock processing module is right again
DNU information can just enter clock hold mode after being parsed, and reduce the cumbersome behaviour such as forwarding and parsing of DNU information
Make, enable the clock processing module in clockwork to quickly enter clock hold mode, shorten to greatest extent from when
Clock interface module detects that clock chain circuit abnormal signal enters the time of clock hold mode to clock processing module, thus significantly
Reduce the frequency hopping of clock processing module output system clock, and control within 1ppb, should have to meet clockwork
Standby retention property.
Detailed description of the invention
Fig. 1 is the functional block diagram for the clockwork first embodiment that the present invention keeps clock；
Fig. 2 is the refinement the functional block diagram of clock interface module 01 in Fig. 1；
Fig. 3 is the refinement functional module that the present invention keeps clock interface module 01 in the clockwork second embodiment of clock
Schematic diagram；
Fig. 4 is the flow diagram of one embodiment of clock keeping method of clockwork of the present invention.
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
The present invention provides a kind of clockwork for keeping clock.
Referring to Fig.1, Fig. 1 is the functional block diagram for the clockwork first embodiment that the present invention keeps clock.
In the first embodiment, which includes: clock interface module 01 and clock processing module 02, wherein
The clock interface module 01, for monitoring received clock chain circuit signal, when judging the clock chain circuit signal
When abnormal, the clock output of the clock interface module 01 is closed；
The clock processing module 02, for closing shape when the clock output for detecting the clock interface module 01 is in
When state, into clock hold mode, output system clock.
The present embodiment detects the clock chain that upstream clock equipment is sent by the clock interface module 01 in clockwork
When road signal occurs abnormal, the clock output of the clock interface module 01 is closed；In this way, the clock in clockwork handles mould
Block 02 is when the clock output for detecting the clock interface module 01 is in close state, you can learn that clock chain circuit signal is different
Often, then clock hold mode is immediately entered, output system clock is detecting clock chain circuit letter without clock interface module 01
When number exception, Xiang Shizhong processing module 02 sends DNU information, clock processing module 02 DNU information is parsed again after
It can enter clock hold mode, reduce the troublesome operations such as forwarding and the parsing of DNU information, so that the clock in clockwork
Processing module 02 can quickly enter clock hold mode, shortened to greatest extent from clock interface module 01 and detect clock
Link signal arrives the time that clock processing module 02 enters clock hold mode extremely, to greatly reduce clock processing module
The frequency hopping of 02 output system clock, and control within 1ppb, to meet the retention property that clockwork should have.
Further, as shown in Fig. 2, above-mentioned clock interface module 01 includes: detection unit 03, clock driver cell 04,
Wherein,
The detection unit 03, for receiving and detecting the clock chain circuit signal of upstream clock equipment transmission, when judging
When stating the abnormal state of clock chain circuit signal, switch control signal is sent to the clock driver cell 04；
The clock driver cell 04, for according to the switch control signal close the clock interface module 01 when
Clock output.
The clock chain circuit signal that 03 real-time monitoring upstream clock equipment of detection unit is sent, and received clock chain circuit is believed
Number state detected, upon this detection when the abnormal state of clock link signal, illustrate that data link occurs disconnecting or clock
Situations such as link signal is lost, then clock interface module 01 loses the clock source of upstream clock equipment input, when can not recover
Clock in clock link signal is automatically locked on local crystal oscillator, but clock interface module 01 can't export at this time at this time
Local crystal oscillator, that is, local oscillator clock of locking, but switch control signal is sent to the clock driver cell by detection unit 03
04；Clock driver cell 04 controlled according to the switch control signal that detection unit 03 is sent the clock interface module 01 when
Clock output sends switch control to clock driver cell 04 when detection unit 03 detects the abnormal state of clock chain circuit signal
Signal processed, clock driver cell 04 can close the clock output of the clock interface module 01 according to the switch control signal,
In this way, the output clock of the clock interface module 01 becomes high-impedance state.
Further, above-mentioned clock processing module 02 is specifically used for:
When detecting that the clock interface module 01 is without clock output within a preset time using phase-locked loop circuit, enter
Clock hold mode, output system clock.
When the clock output of the clock interface module 01 be in close state namely the clock interface module 01 it is defeated
When clock becomes high-impedance state out, phase-locked loop circuit is can be used to be detected in clock processing module 02.Since clock handles mould
Block 02 locks the clock that normal clock chain circuit signal restores using phase-locked loop circuit or enters clock hold mode, and
It, can also be when phaselocked loop electricity when phase-locked loop circuit enters clock hold mode other than can be by way of distribution configuration command
When road detects that clock source is lost, automatically into clock hold mode is arrived, this is one that most phase-locked loop chips all have
Kind basic function, and the phase-locked loop circuit used in the clockwork of synchronous digital system must have this function.
Therefore, in the present embodiment the clock processing module 02 of clockwork can be used phase-locked loop circuit come to clock interface module 01 when
Clock output state is detected, when the phase-locked loop circuit in clock processing module 02 detects that the clock connects within a preset time
When mouth mold block 01 is without clock output, you can learn that exception occurs in clock chain circuit signal, clock source is lost, then clock processing module 02
Immediately enter clock hold mode, output system clock.It should be noted that being examined within a preset time when using phase-locked loop circuit
It surveys before the clock output state of the clock interface module 01, which can be configured, will can be somebody's turn to do as needed
Lower such as 1 to 2 period is arranged to obtain in preset time, in this way, when detecting described within 1 to 2 period using phase-locked loop circuit
When clock interface module 01 is without clock output, clock processing module 02 can immediately enter clock hold mode, reduce detection flower
The time taken can make clock processing module 02 enter clock hold mode faster, to reduce the frequency of output system clock
Jump.
Clock processing module 02 is detected within a preset time using this hardware means of phase-locked loop circuit in the present embodiment
The clock output state of the clock interface module 01, and when detecting the clock interface module 01 without clock output, from
Dynamic to enter clock hold mode, output system clock shortens clock processing module 02 as far as possible and enters clock hold mode
Time, without clock interface module 01 when detecting clock chain circuit abnormal signal, Xiang Shizhong processing module 02 send DNU
Information, clock processing module 02 can just enter clock hold mode after being parsed again to DNU information, reduce DNU letter
The troublesome operations such as the forwarding and parsing of breath enable the clock processing module 02 in clockwork to quickly enter clock holding shape
State shortens to greatest extent from clock interface module 01 and detects that clock chain circuit abnormal signal enters to clock processing module 02
The time of clock hold mode to greatly reduce the frequency hopping of 02 output system clock of clock processing module, and controls
Within 1ppb, to meet the retention property that clockwork should have.
Further, as shown in figure 3, second embodiment of the invention proposes a kind of clockwork for keeping clock, above-mentioned
On the basis of first embodiment, the clock interface module 01 further include:
Filter unit 05, for being judged as that the abnormal clock chain circuit signal carries out noise to through the detection unit 03
Filtering processing, and to through noise filtering, treated that the clock chain circuit signal detects.
In the present embodiment, when detection unit 03 detects the abnormal state of clock chain circuit signal, filter unit is first passed through
05 pair is judged as that the abnormal clock chain circuit signal carries out noise filtering processing through the detection unit 03, and continues to through making an uproar
The clock chain circuit signal after sound filtering processing is detected, if still detecting the abnormal state of the clock chain circuit signal,
Switch control signal is just sent to the clock driver cell 04, so that clock driver cell 04 is according to the switch control signal
Close the clock output of the clock interface module 01.In this way, only through detection unit 03 and filter unit in the present embodiment
05 when all detecting the abnormal state of the clock chain circuit signal, can just send switch control signal to the clock driver cell
04, caused by efficiently avoiding because of the clock transfer link of upstream clock equipment unstable in short-term or environmental disturbances that may be present
The case where detection unit 03 is judged by accident, the clock chain circuit signal condition that can more accurately send to upstream clock equipment are sentenced
It is disconnected, and then when confirming clock chain circuit signal is the abnormalities such as dropout, when clock driver cell 04 just being made to close described
The clock output of clock interface module 01, clock processing module 02 enters the possibility of clock hold mode caused by reducing because of erroneous judgement
Property, enhance the stability of clockwork.
Further, the clock chain circuit signal that upstream clock equipment is sent can be ethernet signal or pulse per second (PPS) (1PPS)
Signal.
The interface type that clock transmitting based on Ethernet generallys use is Ethernet optical port and Ethernet power port, works as clock
When interface module 01 receives the synchronous ethernet signal that upstream clock equipment is transmitted by optical fiber, since optical module itself can be with
Dropout LOS indication signal is generated, and will do it noise filtering processing inside optical module, i.e., optical module itself can be to signal
It loses and carries out the processing such as noise filtering, loss detection, therefore, if the detection unit 03 of clock interface module 01 in practical applications
When obtaining the LOS indication signal in synchronous ethernet signal, then the abnormal state of clock chain circuit signal can be directly known, and be not necessarily to
It is further to carry out noise filtering processing, and switch control signal is sent according to the LOS indication signal in synchronous ethernet signal
To the clock driver cell 04, so that clock driver cell 04 closes the clock interface mould according to the switch control signal
The clock output of block 01.
When clock interface module 01 receives the synchronous ethernet signal that upstream clock equipment is transmitted by cable, due to
Synchronous ethernet physical chip can generate dropout interruption, and the generation of the interruption also can be in synchronous ethernet physical layer
Chip interior is handled by noise filtering, therefore, if the detection unit 03 of clock interface module 01 obtains together in practical applications
When walking the dropout interruption in ethernet signal, then the abnormal state of clock chain circuit signal can be directly known, and be not necessarily into one
The carry out noise filtering processing of step, and interrupted according to the dropout in synchronous ethernet signal and send switch control signal to institute
Clock driver cell 04 is stated, so that clock driver cell 04 closes the clock interface module 01 according to the switch control signal
Clock output.
When clock interface module 01 receives pulse per second (PPS) (1PPS) signal that upstream clock equipment is transmitted by 1PPS interface
When, the detection unit 03 of clock interface module 01 is measured in real time the state of received 1PPS signal, when detecting 1PPS
When the abnormal state of signal, which is sent to filter unit 05, is made an uproar by filter unit 05 to the 1PPS signal
Sound filtering processing, and continue to through noise filtering, treated that 1PPS signal detects, if still detecting the shape of 1PPS signal
State is abnormal, just sends switch control signal to the clock driver cell 04, so that clock driver cell 04 is according to the switch
Control the clock output of clock interface module 01 described in signal-off.In turn, when the phase-locked loop circuit in clock processing module 02
When detecting that the clock interface module 01 is without clock output within a preset time, clock hold mode can be immediately entered, is exported
System clock.
The present invention further provides a kind of clock keeping methods of clockwork.The clockwork includes: clock interface
Module and clock processing module.
It is the flow diagram of one embodiment of clock keeping method of clockwork of the present invention referring to Fig. 4, Fig. 4.
In one embodiment, the clock keeping method of the clockwork includes:
Step S10, the received clock chain circuit signal of clock interface module monitors, when judging the clock chain circuit signal
When abnormal, the clock output of the clock interface module is closed；
Step S20, the clock processing module close shape when the clock output for detecting the clock interface module is in
When state, into clock hold mode, output system clock.
The present embodiment detects the clock chain circuit that upstream clock equipment is sent by the clock interface module in clockwork
When signal occurs abnormal, the clock output of the clock interface module is closed；In this way, the clock processing module in clockwork exists
When detecting that the clock output of the clock interface module is in close state, you can learn that clock chain circuit abnormal signal, then stand
It carves and enters clock hold mode, output system clock, without clock interface module when detecting clock chain circuit abnormal signal,
DNU information is sent to clock processing module, clock processing module can just enter clock guarantor after being parsed again to DNU information
State is held, the troublesome operations such as forwarding and the parsing of DNU information are reduced, enables the clock processing module in clockwork rapid
Clock hold mode is entered, is shortened to greatest extent from clock interface module and detects clock chain circuit abnormal signal to clock
Processing module enters the time of clock hold mode, so that the frequency for greatly reducing clock processing module output system clock is jumped
Become, and control within 1ppb, to meet the retention property that clockwork should have.
Further, in other embodiments, above-mentioned steps S10 may include: that the clock interface module is received and examined
The clock chain circuit signal that upstream clock equipment is sent is surveyed, when judging the abnormal state of the clock chain circuit signal, generates switch
Signal is controlled, and closes the clock output of the clock interface module according to the switch control signal.
The clock chain circuit signal that the clock interface module real-time monitoring upstream clock equipment is sent, and to received clock
The state of link signal is detected, and upon this detection when the abnormal state of clock link signal, illustrates that data link disconnects
Or situations such as clock chain circuit dropout, then clock interface module loses the clock source of upstream clock equipment input, can not restore
Clock in clock chain circuit signal out, that is, be automatically locked on local crystal oscillator, but clock interface module can't export this at this time
Local crystal oscillator, that is, local oscillator clock of Shi Suoding, but switch control signal is generated, and control according to the switch control signal of generation
The clock output for making the clock interface module can be according to generation upon this detection when the abnormal state of clock link signal
Switch control signal closes the clock output of the clock interface module, in this way, the output clock of the clock interface module is
Become high-impedance state.
Further, in other embodiments, above-mentioned steps S20 may include:
When detecting that the clock interface module is without clock output within a preset time using phase-locked loop circuit, when entrance
Clock hold mode, output system clock.
When the clock output of the clock interface module is in close state namely when the output of the clock interface module
When clock becomes high-impedance state, phase-locked loop circuit is can be used to be detected in clock processing module.Since clock processing module uses
Be phase-locked loop circuit to lock the clock or enter clock hold mode that normal clock chain circuit signal restores, and phaselocked loop is electric
When road enters clock hold mode other than can be by way of distribution configuration command, it can also be detected when phase-locked loop circuit
When clock source is lost, automatically into clock hold mode is arrived, this is a kind of basic training that most phase-locked loop chips all have
Can, and the phase-locked loop circuit used in the clockwork of synchronous digital system must have this function.Therefore, this reality
Apply clockwork in example clock processing module can be used phase-locked loop circuit come to the clock output state of clock interface module into
Row detection, when the phase-locked loop circuit in clock processing module detects that the clock interface module is defeated without clock within a preset time
When out, you can learn that abnormal, clock source loss occurs in clock chain circuit signal, then clock processing module immediately enters clock holding shape
State, output system clock.It should be noted that when detecting the clock interface module within a preset time using phase-locked loop circuit
Clock output state before, which can be configured, as needed the preset time can be arranged lower such as 1
To 2 periods, in this way, detecting the clock interface module without clock output within 1 to 2 period using phase-locked loop circuit
When, clock processing module can immediately enter clock hold mode, reduce the time that detection is spent, can make clock processing module
Enter clock hold mode faster, to reduce the frequency hopping of output system clock.
Clock processing module detects institute within a preset time using this hardware means of phase-locked loop circuit in the present embodiment
The clock output state of clock interface module is stated, and when detecting the clock interface module without clock output, automatically into
Clock hold mode, output system clock shorten the time that clock processing module enters clock hold mode as far as possible, and
Without clock interface module when detecting clock chain circuit abnormal signal, Xiang Shizhong processing module sends DNU information, clock processing
Module can just enter clock hold mode after being parsed again to DNU information, reduce forwarding and parsing of DNU information etc.
Troublesome operation enables the clock processing module in clockwork to quickly enter clock hold mode, shortens to greatest extent
Detect that clock chain circuit abnormal signal enters the time of clock hold mode to clock processing module from clock interface module, from
And the frequency hopping of clock processing module output system clock is greatly reduced, and control within 1ppb, it is set with meeting clock
The standby retention property that should have.
Further, second embodiment of the invention proposes a kind of clock keeping method of clockwork, real above-mentioned first
On the basis of applying example, above-mentioned steps S10 further include:
Noise filtering processing is carried out to the clock chain circuit signal for being judged as abnormal, and to treated through noise filtering
The clock chain circuit signal is detected.
In the present embodiment, when the clock interface module detects the abnormal state of clock chain circuit signal, first to judgement
Noise filtering processing is carried out for the abnormal clock chain circuit signal, and is continued to through noise filtering treated the clock chain
Road signal is detected, if still detecting the abnormal state of the clock chain circuit signal, generates switch control signal, just with basis
The switch control signal closes the clock output of the clock interface module.In this way, only through dual inspection in the present embodiment
When surveying the abnormal state of the clock chain circuit signal, switch control signal can be just generated, efficiently avoids setting because of upstream clock
The case where standby clock transfer link unstable in short-term or environmental disturbances that may be present cause detection to judge by accident, can more accurately
The clock chain circuit signal condition sent to upstream clock equipment judges, and then is dropout in confirmation clock chain circuit signal
Etc. abnormalities when, just close the clock output of the clock interface module, caused by reducing because of erroneous judgement clock processing module into
A possibility that entering clock hold mode enhances the stability of clockwork.
Further, the clock chain circuit signal that upstream clock equipment is sent can be ethernet signal or pulse per second (PPS) (1PPS)
Signal.
The interface type that clock transmitting based on Ethernet generallys use is Ethernet optical port and Ethernet power port, works as clock
When interface module receives the synchronous ethernet signal that upstream clock equipment is transmitted by optical fiber, since optical module itself can produce
Raw dropout LOS indication signal, and will do it noise filtering processing inside optical module, i.e., optical module itself can lose signal
It loses and carries out the processing such as noise filtering, loss detection, therefore, if clock interface module gets synchronous ethernet in practical applications
LOS indication signal in signal then can directly know the abnormal state of clock chain circuit signal, and carry out noise without further
Filtering processing, and switch control signal is generated according to the LOS indication signal in synchronous ethernet signal, to be controlled according to the switch
The clock output of clock interface module described in signal-off processed.
When clock interface module receives the synchronous ethernet signal that upstream clock equipment is transmitted by cable, due to same
Step ethernet physical layer chip can generate dropout interruption, and the generation of the interruption also can be in synchronous ethernet physical layer core
It is handled inside piece by noise filtering, therefore, if clock interface module is got in synchronous ethernet signal in practical applications
Dropout interrupt, then can directly know the abnormal state of clock chain circuit signal, and carry out noise filtering without further
Processing, and interrupted according to the dropout in synchronous ethernet signal and generate switch control signal, according to the switch control
The clock output of clock interface module described in signal-off.
When clock interface module receives pulse per second (PPS) (1PPS) signal that upstream clock equipment is transmitted by 1PPS interface,
Clock interface module is measured in real time the state of received 1PPS signal, when detecting the abnormal state of 1PPS signal,
Noise filtering processing is carried out to the 1PPS signal, and is continued to treated that 1PPS signal detects through noise filtering, if still
So abnormal state of detection 1PPS signal, just generates switch control signal, when closing described according to the switch control signal
The clock output of clock interface module.In turn, when the phase-locked loop circuit in clock processing module detect it is described within a preset time
When clock interface module is without clock output, clock hold mode, output system clock can be immediately entered.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.Pass through above embodiment party
The description of formula, it is required general that those skilled in the art can be understood that above-described embodiment method can add by software
The mode of hardware platform is realized, naturally it is also possible to which by hardware, but in many cases, the former is more preferably embodiment.It is based on
Such understanding, substantially the part that contributes to existing technology can be with software product in other words for technical solution of the present invention
Form embody, which is stored in a storage medium (such as ROM/RAM, magnetic disk, CD), including
Some instructions are used so that a terminal device (can be mobile phone, computer, server or the network equipment etc.) executes this hair
Method described in bright each embodiment.
The above is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (10)
1. a kind of clockwork for keeping clock, which is characterized in that the clockwork includes: at clock interface module and clock
Manage module, wherein
The clock interface module, for monitoring received clock chain circuit signal, when judging the clock chain circuit abnormal signal,
Close the clock output of the clock interface module；
The clock processing module, for when the clock output for detecting the clock interface module is in close state, into
Enter clock hold mode, output system clock.
2. clockwork as described in claim 1, which is characterized in that the clock interface module includes: detection unit, clock
Driving unit, wherein
The detection unit, for receiving and detecting the clock chain circuit signal of upstream clock equipment transmission, when judging the clock
When the abnormal state of link signal, switch control signal is sent to the clock driver cell；
The clock driver cell, for closing the clock output of the clock interface module according to the switch control signal.
3. clockwork as claimed in claim 2, which is characterized in that the clock interface module further include:
Filter unit, for being judged as that the abnormal clock chain circuit signal carries out at noise filtering to through the detection unit
Reason, and to through noise filtering, treated that the clock chain circuit signal detects.
4. clockwork as claimed in claim 1 or 2, which is characterized in that the clock processing module is specifically used for:
When detecting that the clock interface module is without clock output within a preset time using phase-locked loop circuit, protected into clock
Hold state, output system clock.
5. clockwork as claimed in claim 4, which is characterized in that the clock chain circuit signal is ethernet signal or second arteries and veins
Rush signal.
6. a kind of clock keeping method of clockwork, which is characterized in that the clockwork includes: that clock interface module is timely
Clock processing module, the described method comprises the following steps:
The received clock chain circuit signal of clock interface module monitors is closed when judging the clock chain circuit abnormal signal
The clock output of the clock interface module；
The clock processing module is when the clock output for detecting the clock interface module is in close state, into clock
Hold mode, output system clock.
7. the clock keeping method of clockwork as claimed in claim 6, which is characterized in that the clock interface module monitors
Received clock chain circuit signal, when judging the clock chain circuit abnormal signal, the clock for closing the clock interface module is defeated
Out the step of includes:
The clock interface module receives and detects the clock chain circuit signal of upstream clock equipment transmission, when judging the clock chain
When the abnormal state of road signal, switch control signal is generated, and the clock interface mould is closed according to the switch control signal
The clock output of block.
8. the clock keeping method of clockwork as claimed in claim 7, which is characterized in that the clock interface module monitors
Received clock chain circuit signal, when judging the clock chain circuit abnormal signal, the clock for closing the clock interface module is defeated
Out the step of further include:
To being judged as that the abnormal clock chain circuit signal carries out noise filtering processing, and to through noise filtering, that treated is described
Clock chain circuit signal is detected.
9. the clock keeping method of clockwork as claimed in claims 6 or 7, which is characterized in that the clock processing module
When the clock output for detecting the clock interface module is in close state, into clock hold mode, when output system
The step of clock, specifically includes:
When detecting that the clock interface module is without clock output within a preset time using phase-locked loop circuit, protected into clock
Hold state, output system clock.
10. the clock keeping method of clockwork as claimed in claim 9, which is characterized in that the clock chain circuit signal is
Ethernet signal or second pulse signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410837161.6A CN105790873B (en) | 2014-12-26 | 2014-12-26 | Keep the clockwork and method of clock |
| PCT/CN2015/097014 WO2016101792A1 (en) | 2014-12-26 | 2015-12-10 | Clock device and method for maintaining clock |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410837161.6A CN105790873B (en) | 2014-12-26 | 2014-12-26 | Keep the clockwork and method of clock |
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| CN105790873A CN105790873A (en) | 2016-07-20 |
| CN105790873B true CN105790873B (en) | 2019-06-21 |
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| WO (1) | WO2016101792A1 (en) |
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| CN111355551A (en) * | 2020-02-11 | 2020-06-30 | 西安电子科技大学 | Network clock synchronization method and device suitable for semi-stable link |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1553478A1 (en) * | 2004-01-06 | 2005-07-13 | Alcatel | A redundant synchronous clock distribution method, a related clock module and a related clock slave device |
| CN101431444B (en) * | 2007-11-07 | 2011-06-22 | 中兴通讯股份有限公司 | Test method for transmission equipment clock synchronous information switching time delay |
| CN101252405B (en) * | 2008-03-27 | 2012-09-05 | 华为技术有限公司 | Clock detection and auto switching method and system |
| CN101547053A (en) * | 2008-03-28 | 2009-09-30 | 华为技术有限公司 | Clock-switching method and clock-generating device |
| CN101621324A (en) * | 2008-07-01 | 2010-01-06 | 联想(北京)有限公司 | Coordination method for communication resources and Bluetooth communication terminal |
| CN101645718B (en) * | 2008-08-07 | 2013-08-07 | 中兴通讯股份有限公司 | Method and device for holding clock |
| CN101853192A (en) * | 2010-05-31 | 2010-10-06 | 华为技术有限公司 | Exception handling method and system, off-chip logic device and chip |
| CN102946291A (en) * | 2012-11-12 | 2013-02-27 | 华为技术有限公司 | Clock maintaining method and clock equipment |
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| CN105790873A (en) | 2016-07-20 |
| WO2016101792A1 (en) | 2016-06-30 |
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