CN106788838A - A kind of system and method for Power time synchronization system robust control - Google Patents
A kind of system and method for Power time synchronization system robust control Download PDFInfo
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- CN106788838A CN106788838A CN201611013953.7A CN201611013953A CN106788838A CN 106788838 A CN106788838 A CN 106788838A CN 201611013953 A CN201611013953 A CN 201611013953A CN 106788838 A CN106788838 A CN 106788838A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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Abstract
The present invention relates to a kind of system and method for Power time synchronization system robust control, clock synchronization system includes at least two master clock device and from passing through optical fiber interconnections between clock apparatus, master clock device；Master clock device is interconnected by optical fiber with from clock apparatus；Source signal when clock synchronization system receives outside by master clock device, what source selected when ensureing the safe and reliable guarantee master clock device of source signal during outside is safe and reliable, master clock device is made up of clock receiving unit, clock unit and the output unit being sequentially connected, and clock synchronization system sets reliability judge module on the clock receiving unit and clock unit.The present invention starts with from clock synchronization system signal source, the source and signaling security in source judges during to input during by introducing multiple outside, the source signal during input that the interference or malice for preventing outside unstable signal are distorted, during so as to selecting the most reliable source as master clock device synchronization when source, it is ensured that the reliability of source signal during master clock device.
Description
Technical field
The present invention relates to automation equipment technical field of measurement and test, and in particular to a kind of Power time synchronization system robust control
System and method.
Background technology
Scheduling institutions at different levels, power plant, transformer station, centralized control center of power network etc. are required for an accurate time base of unification
It is accurate meeting various systems (such as dispatch automated system, EMS, Style Product Information Management System, monitoring system) and set
Standby (such as protective relaying device, intelligent electronic device, sequence of event SOE, plant stand automatic control equipment, security and stability control
Device, fault filter) requirement to time synchronized, it is ensured that real-time data acquisition time consistency, improve line fault range finding,
Phasor and the generator rotor angle accuracy that dynamically measurement, unit and electrical network parameter are verified, so as to improve power grid accident analysis and stability contorting
Level, improve operation of power networks efficiency and reliability.The accuracy of power system time synchronized is to ensure Operation of Electric Systems control
System and the important foundation condition of accident analysis, clock synchronization system are most important as its security reliability of time service source in station.
Power time synchronization system mainly includes master clock device and from clock apparatus.Master clock device utilizes satellite-signal
When carrying out time service, it is necessary to receive satellite-signal from open space using antenna, while real satellite signal is received, it is impossible to
Avoid the satellite-signal (curve) for receiving falseness, if receiving unit can not recognize curve, curve is worked as
Into actual signal, time service is carried out using curve, the time of mistake certainly will be obtained, cause serious consequence.Additionally, master clock is filled
Put source reliability when there is an only external sync low；Reliability select permeability in source when multiple outside；Output signal is not
The problems such as continuous, cause master clock device and the device higher to time accuracy degree of dependence cannot normal work, and because
Without accurate Time To Event so as to influence the crash analysis after accident occurs.Receive what master clock sent from clock apparatus
Time synchronizing signal is synchronized, to provide time synchronizing signal by time service equipment after synchronously completing.But applying at present
Lack the monitoring to clock synchronization system interior arrangement in journey, when a certain setup time synchronous abnormality, system can be influenceed to export
The reliability of time signal.
The content of the invention
To solve above-mentioned deficiency of the prior art, it is an object of the invention to provide a kind of Power time synchronization system robust
The system and method for control, the present invention starts with from clock synchronization system signal source, source and to input during by introducing multiple outside
The signaling security of Shi Yuan judged, the source signal during input that the interference or malice for preventing outside unstable signal are distorted,
During so as to selecting the most reliable source as master clock device synchronization when source, it is ensured that the reliability of source signal during master clock device
Property.
The purpose of the present invention is realized using following technical proposals：
The present invention relates to a kind of system of Power time synchronization system robust control, it is theed improvement is that, the time
Synchronization system includes at least two master clock devices and from clock apparatus, is interconnected by optical fiber between the master clock device；Often
One master clock device is interconnected from clock apparatus respectively with respectively by optical fiber；The clock synchronization system is received by master clock device
Source signal when outside, it is ensured that when outside source signal it is safe and reliable guarantee master clock device when source selection it is safe and reliable；Institute
State clock receiving unit, clock unit and output unit of the master clock device by being sequentially connected to constitute, the clock synchronization system
Reliability judge module is set on the clock receiving unit and clock unit.
Further, the clock receiving unit includes satellite signal reception module, wire signal receiver module and reliability
Property judge module；The reliability judge module is signaling security judge module；
The satellite reception module is used to receive the satellite-signal of at least two outside inputs；
The wire signal receiver module is used to receive (such as IRIG-B yards of wired time signal of at least one outside input
Signal)；
The signaling security judge module is used to judge the security of input signal；
For the satellite-signal of outside input, change, the ephemeris of the visible star of satellite-signal power, satellite are compared by detection
Parameter update frequency and amplitude, carrier frequency, bit rate and its rate of change, satellite-signal number change, pseudorange residuals and positioning
Deviation etc., Deceiving interference and pressing type interference signal outside exclusion；For wired time signal of outside input, by inspection
The continuity of survey input signal, check bit, verification mode, temporal quality exclude unstable insecure time source signal, from
And improve the security of external input signal.
Further, the clock unit by crystal oscillator module, when source control module, local zone time module and information management mould
Block is constituted；The time deviation of source and local zone time when source control module is used for relatively outside more effective when described, and select the most
Crystal oscillator and synchronous local zone time are tamed in source when source is as synchronization when reliable；
If in system electrification initial phase, when synchronization is selected behind source, when the master clock device is synchronous outside during source
Between；After if system completes initialization, when when local zone time and the synchronization selected, source time deviation is more than 1us, when source control mould
Source time when block is used to control local zone time Step wise approximation synchronous, takes progressively near mode, and follow-up amplitude is not more than 1us/
S, so as to meet electric power by the application demand of time service equipment；
The information that described information management module is used to process between each master clock device is exchanged and command interaction, and to letter
Breath is analyzed and collects.
Further, the output unit is used to for the time signal after master clock device synchronization to pass through different signal modes
Block is converted to different types of time output signal；
The output unit include for IRIG-B yards of signaling module of output power application signal, pulse signal module,
Serial ports message signals module and network message signaling module；The output signal of electric power application includes：The IRIG-B yards of signal mode
Block is used to export IRIG-B yards of signal, and the pulse signal module is used for output pulse signal, the serial ports message signals module
For exporting serial ports message signals, the network message signaling module is used to export network message signal.
The present invention also provides a kind of implementation method of power application clock synchronization system, and it is theed improvement is that, the reality
Existing method includes：
Step 1：Using the clock synchronization system of double master clock devices；
Step 2：Safe and reliable signal is received from clock apparatus, source signal and is completed when double master clock devices receive outside
It is synchronous；
Step 3：The output signal of master clock device monitoring clock synchronization system each device is determining failed equipment；
Step 4：Determine the signal of the output of clock synchronization system and the time deviation of master clock device.
Further, in the step 1, when the clock synchronization system is using double master clock device, two it is double main when
Clock device is mutually redundant, when when a certain master clock device receives satellite-signal, source failure cannot be synchronous, another master clock device
Source information when being provided for failure master clock, it is ensured that double master clock device normal works.
Further, in the step 2, each receives two IRIG-B signals of master clock from clock apparatus, when wherein
During one master clock device signal fault, automatically switched on another master clock device signal from clock apparatus, it is ensured that from clock
Device receives safe and reliable signal.
Further, in the step 3, the output signal of each device of clock synchronization system is monitored by master clock device
To determine failed equipment, realize that information communicates by optical port wavelength-division multiplex technique using on the basis of original wiring, optical fiber connection
Both sides same wavelength-division multiplex optical module is used in the case of different wave length is received and dispatched, while B yard of light is sent, monitoring is right
The feedback information that side sends, captures its rising edge time accuracy and information decoding.
Further, in the step 4, the source signal and after completing synchronization when device receives outside to two masters all the time, its
In master clock device receive another master clock device and each from IRIG-B yards of signal of clock apparatus output, and calculate
Go out each from the signal of clock apparatus output and the time deviation of one of master clock device, be designated as respectively：Δt11,Δ
t12,Δt13……Δt1n；Similarly, master clock 2 can receive master clock 1 and each believes from IRIG-B yards of clock output
Number and calculating deviate, be designated as respectively：Δ t21, Δ t22, Δ t23 ... Δ t2n, Δ t11 and Δ t21 are respectively one of them
Deviation between two master clock devices that master clock device and another master clock device are measured, remaining is two for measuring
Master clock device and the deviation from clock apparatus, one of master clock device and another master clock device pass through Network Synchronization
The deviation information for calculating, and one of master clock device serves as the manager of clock synchronization system, another master clock
Device serves as standby manager, when one of master clock device management work is abnormal, is completed by another master clock device
The management work of system.
In order to some aspects to the embodiment for disclosing have a basic understanding, simple summary is shown below is.Should
Summarized section is not extensive overview, nor to determine key/critical component or describe the protection domain of these embodiments.
Its sole purpose is that some concepts are presented with simple form, in this, as the preamble of following detailed description.
Compared with immediate prior art, the excellent effect that the technical scheme that the present invention is provided has is：
1. the present invention provide a kind of Power time synchronization system robust control system and its implementation, it is ensured that the time
Source is safe and reliable during synchronization system outside input, starts with by from clock synchronization system signal source, multiple outside by introducing
When source and to input when source signaling security judge, prevent outside unstable signal interference or malice distort it is defeated
Fashionable source signal, during so as to selecting the most reliable source as master clock device synchronization when source, it is ensured that source during master clock device
The reliability of signal；On the other hand the closed loop of clock synchronization system is realized by robust control, master clock device utilizes optical port ripple
Each device is monitored to clock synchronization system for point multiplexing technology, clock apparatus of timely discovery time synchronous abnormality and to it
It is adjusted, so that it is guaranteed that electric power time service is safe and reliable.Even if at outside there is saltus step in particular cases in source, by soft
The continuous-stable of part control mode control time synchronization system output time signal.
Source is input into the selectivity in source when quantity improves master clock device during by increasing master clock device outside, using signal
Source when security module prevents Deceiving interference and the pressing type interference signal from influenceing the synchronization of master clock device, prevents some maliciously
The deception of input signal, when source control module can from multiple outside when source signal in select the time the most safe and reliable same
Source during step, it is ensured that the normal work of master clock device, so as to provide time synchronizing signal from clock, system is ensured from signal source
The safety of system.
2. ensure that clock synchronization system internal operation is safe and reliable.
Clock synchronization system is formed closed loop by robust control, time synchronized system is monitored and managed using master clock device
Each device in system, once pinpoint the problems producing warning information in time, and is carried out by Monitoring Data and information to failed equipment
Compensation and adjustment make its reliable time signal of output, it is ensured that internal system operation safety.Meanwhile, when source control module according to choosing
Source time and local zone time take the mode synchronization local zone time for progressively following up during the synchronization selected, it is to avoid the time signal hair of output
Raw saltus step, improves the global reliability of clock apparatus, thus for whole power system provide safe and reliable by time service device when
Between synchronizing signal.
Brief description of the drawings
Fig. 1 is the master clock device structure chart that the present invention is provided；
Fig. 2 is the clock synchronization system closed loop schematic diagram that the present invention is provided；
Fig. 3 is the structure chart of the optical port wavelength-division multiplex that the present invention is provided；
Fig. 4 is the intelligent substation master clock device application schematic diagram that the present invention is provided.
Specific embodiment
Specific embodiment of the invention is described in further detail below in conjunction with the accompanying drawings.
The following description and drawings fully show specific embodiments of the present invention, to enable those skilled in the art to
Put into practice them.Other embodiments can include structure, logic, it is electric, process and it is other changes.Embodiment
Only represent possible change.Unless explicitly requested, otherwise single component and function are optional, and the order for operating can be with
Change.The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.This hair
The scope of bright embodiment includes the gamut of claims, and all obtainable of claims is equal to
Thing.Herein, these embodiments of the invention can individually or generally be represented that this is only with term " invention "
For convenience, and if in fact disclosing the invention more than, it is not meant to automatically limit the scope of the application to appoint
What single invention or inventive concept.
Embodiment one
The present invention proposes a kind of system and its implementation of Power time synchronization system robust control, by the method
Start with from clock synchronization system signal source, the source and signaling security in source is sentenced during to input during by introducing multiple outside
It is disconnected, source signal, source during so as to selecting the most reliable during the input that the interference or malice for preventing outside unstable signal are distorted
As master clock device synchronization when source, it is ensured that the reliability of source signal during master clock device；On the other hand robust control is passed through
The closed loop of clock synchronization system is realized, each device enters master clock device to clock synchronization system using optical port wavelength-division multiplex technique
Row monitoring, the clock apparatus of timely discovery time synchronous abnormality are simultaneously adjusted to it, so that it is guaranteed that the safety of electric power time service can
Lean on.Even if at outside there is saltus step in particular cases in source, when being exported by software-controlled manner control time synchronization system
Between signal continuous-stable.
As shown in figure 1, being the master clock device structure chart for providing of the invention, clock synchronization system is received by master clock device
Source signal when outside, in order to ensure source signal during outside it is safe and reliable should ensure that master clock device when source selection safety can
Lean on.Master clock device is mainly made up of clock receiving unit, clock unit and output unit, specifically as shown in Figure 1.It is main herein
Increase reliability judge module to provide the general safety reliability of master clock device by receiving unit and clock unit.
Clock receiving unit is by satellite reception module and wired time signal input module, signaling security judge module group
Into.Satellite reception module should receive at least two satellite-signals, and wired time signal input module should at least receive a kind of wired
Time signal (such as IRIG-B yards of signal).The quantity in source during by improving master clock device outside input, improves master clock device
When source signal multi-selection, it is to avoid source failure causes the problem that device cannot work when single.Meanwhile, increase signaling security
Judge module is judged the security of input signal.For the satellite-signal of outside input, satellite is compared by detection and is believed
Number power, the change of the visible star of satellite, ephemeris parameter update frequency and amplitude, carrier frequency, bit rate and its rate of change, satellite
Number of signals change, pseudorange residuals and deviations etc., Deceiving interference and pressing type interference signal outside exclusion；For outer
Wired time signal of portion's input, is excluded by continuity, check bit, verification mode, the temporal quality etc. that detect input signal
Unstable insecure time source signal, so as to improve the security of external input signal.
Clock unit by crystal oscillator module, when source control module, local zone time and information management module constitute.When source control mould
Block be used for it is relatively outside effectively when source and local zone time time deviation, during so as to selecting the most reliable source as it is synchronous when
Tame crystal oscillator and synchronous local zone time in source.If in the device power-up initializing stage, when synchronization is selected behind source, master clock device should
Source time when rapid synchronous outside；If after device completes initialization, when local zone time and the synchronization selected, source time deviation is big
When 1us, when source control module source time when local zone time Step wise approximation should be controlled synchronous, it is to avoid produce the big step of moment with
Enter, should take progressively near mode, follow-up amplitude not should be greater than 1us/s, so as to meet electric power by the application need of time service device
Ask.Information management module collects for processing the exchange of the information between each clock and command interaction, and information being analyzed
Deng.
Output unit is different types of for the time signal after clock apparatus synchronization to be converted to by different modules
Time output signal, the output signal of electric power application is broadly divided into：IRIG-B yards of signal, pulse signal, serial ports message signals, net
Network message signals etc..
The safe and reliable of source signal ensures the safe and reliable of system from signal source when outside, but cannot ensure in system
Time synchronized exception caused by portion's failure, therefore, the safe and reliable of whole system is further ensured by closed loop herein.
Embodiment two
The present invention also provides a kind of implementation method of the system of Power time synchronization system robust control, based on robust control
Clock synchronization system closed loop design with realize, implementation method includes：
Step 1：Using the clock synchronization system of double master clock devices；
Step 2：Safe and reliable signal is received from clock apparatus, source signal and is completed when double master clock devices receive outside
It is synchronous；
Step 3：The output signal of master clock device monitoring clock synchronization system each device is determining failed equipment；
Step 4：Determine the signal of the output of clock synchronization system and the time deviation of master clock device.
Deviation when obtaining mutual pair is connected between master clock 1 and master clock 2 by optical fiber, and it is same by way of network
Step information, master clock 1 and master clock 2 are connected with each by optical fiber from clock respectively, and each is obtained by wavelength-division multiplex technique
From the deviation of clock apparatus output signal, when the excessive device of discovery deviation, master clock is by network transmitting order to lower levels to the dress
Put and be adjusted, the reliability of output signal is recovered to the full extent.Master clock 1 as system manager, the conduct of master clock 2
Standby manager, when 1 failure of master clock, by the monitoring and management of the complete paired systems of master clock 2, it is ensured that clock synchronization system
It is safe and reliable, so that clock synchronization system forms closed loop, it is specific as shown in Figure 2.
Clock apparatus use wavelength-division multiplex optical module, an a length of 850nm of side's send wave, a length of 1510nm of received wave in Fig. 3；
The opposing party uses same wavelength-division multiplex optical module, a length of 1510nm of send wave, a length of 850nm of received wave.Two kinds of light of wavelength
Optical fiber signaling simultaneous transmission in same optical fiber, is independent of each other.
Specifically：
In step 1, clock synchronization system is configured using double master clocks, as shown in Figure 2.Lead between master clock 1 and master clock 2
Cross optical fiber interconnections and send IRIG-B information, when when a certain master clock receives satellite-signal, source failure cannot be synchronous, Ling Yizhu
Clock can be source information when failure master clock is provided, so that it is guaranteed that two master clock normal works.
In step 2, each master clock and from clock also by optical fiber interconnections, each receives two master clocks from clock
IRIG-B signals, when one of master clock signal fault, can automatically switch on another master clock signal, really from clock
Guarantor receives safe and reliable signal from clock.
In step 3, the when source signal for receiving it is safe and reliable it cannot be guaranteed that clock apparatus output signals security reliability, because
This, present invention design by the output signal of master clock monitoring clock synchronization system each device to determine failed equipment, in order to
Avoid increasing wiring, realize that information communicates by optical port wavelength-division multiplex technique on the basis of original wiring, the both sides of optical fiber connection
Same wavelength-division multiplex optical module is used in the case of different wave length is received and dispatched, while B yard of light is sent, other side is also monitored and is sent out
The feedback information for coming, captures its rising edge time accuracy and information decoding, and a such as a length of 850nm of side's send wave receives wavelength
It is 1510nm；The opposing party use same wavelength-division multiplex optical module, a length of 1510nm of send wave, a length of 850nm of received wave, specifically
As shown in Figure 3.
In step 4, the source signal and after completing synchronization when master clock 1 and master clock 2 receive outside, master clock 1 can connect
Receive master clock 2 and each from clock output IRIG-B yard signal, it is possible to calculate each device export signal and it is main when
The time deviation of clock 1, is designated as respectively：Δt11,Δt12,Δt13……Δt1n；Similarly, when master clock 2 can receive main
Clock 1 and each deviated from IRIG-B yards of signal and can calculating of clock output, be designated as respectively：Δt21,Δt22,Δ
T23 ... Δ t2n, Δ t11 and Δ t21 are respectively the deviation between two master clocks that master clock 1 and master clock 2 are measured, its
It is remaining be measure each from clock and the deviation of master clock, master clock 1 and master clock 2 by Network Synchronization calculate it is inclined
Difference information, and master clock 1 serves as the manager of clock synchronization system, master clock 2 serves as standby manager, when master clock 1 is managed
During operation irregularity, by the management work of the completion system of master clock 2.According to《Power system clock synchronization system technical specification》Will
Ask, the IRIG-B time accuracies of clock apparatus output should be better than 1 μ s, therefore under clock synchronization system normal running conditions,
No matter Δ t11, Δ t12, Δ t13 ... Δs t1n or Δ t21, the absolute value of Δ t22, Δ t23 ... Δs t2n all should be little
In 1 μ s.If a certain moment finds Δ t1n and Δ t2n (n>1) 1 μ s are both greater than, then it represents that clock n time synchronized exceptions, now,
Master clock 1 produce warning information and send order obtain clock n it is current when source selection information, if the when source of selection is master clock 1,
Δ t1n is then sent to clock apparatus n by master clock, and clock apparatus n compensates output signal Δ t1n after obtaining deviation, and uses
The compensation way of stepping avoids producing big bounce；If the when source of clock n selections is master clock 2, master clock 1 sends out Δ t2n
Clock n is given, is compensated in the same way, so as to ensure that the abnormal device of time synchronized can also export the reliable time
Signal.
Embodiment three
Fig. 4 is intelligent substation clock synchronization system typical case's application example, and master clock 1 and master clock 2 are standby each other, when main
Clock 1 provides time synchronizing signal for station level equipment, from clock reception master clock 1 and the IRIG-B signals of the output of master clock 2 simultaneously
The signal when being provided pair for measure and control device and protection device after completing synchronization.
Present invention can apply to the design of clock synchronization system in intelligent substation, application schematic diagram is as shown in Figure 4.When main
Clock device is deployed in station level, and using double master clock configurations, wherein master clock 1 is master clock, and master clock 2 is standby clock, by closing
Connection IRIG-B signals realize the communication of double master clocks.According to the design of this paper, clock apparatus should receive gps signal, the BDS of outside
Signal, wired input signal as master clock device input when source, malice is excluded by signaling security judge module and is taken advantage of
Deceive signal, by when source control module from input it is effective when source in select the most reliable when source be used as synchronization when source synchronization
Local zone time.After synchronization is completed, master clock device exports NTP signals and IRIG-B yards of signal for station equipment is synchronized.
Monitoring host computer, gateway machine of station level etc. receive synchronous timing signal of the NTP signals that send of master clock as device, observing and controlling dress
Put and receive IRIG-B yards of signal of clock apparatus output as the time synchronizing signal of device with protection device.For large-scale
Transformer station, can realize the synchronization from clock in each cell deployment from clock, IRIG-B yards of signal for receiving master clock from clock,
IRIG-B yards of signal is exported after synchronization for small indoor measure and control device, protection device provide synchronous timing signal.Master clock device
In when source control module source time and local zone time when can be relatively outside in real time difference, even if source time occurs at outside
When saltus step, the output signal continuous-stable of clock apparatus, the external timing signal of Step wise approximation selection, so as to avoid are protected
The saltus step of output signal, it is ensured that reliable continuous time signal can be received by time service device.In whole clock synchronization system
In, the safe and reliable of the signal source that system is input into is ensured by robust control, make master clock device as the time in internal system
The management end of synchronization system, the time synchronized state of each device in monitoring system, when discovered between synchronous abnormality device when,
Master clock can produce warning information and carry out parameter adjustment to ensure the time to the abnormal device of time synchronized by robust control
The safe and reliable output of synchronization system time signal.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than its limitations, although with reference to above-described embodiment pair
The present invention has been described in detail, and those of ordinary skill in the art can still enter to specific embodiment of the invention
Row modification or equivalent, these are applying without departing from any modification of spirit and scope of the invention or equivalent
Within pending claims of the invention.
Claims (9)
1. a kind of system of Power time synchronization system robust control, it is characterised in that the clock synchronization system is included at least
Two master clock devices and from clock apparatus, are interconnected between the master clock device by optical fiber；Each master clock device leads to
Optical fiber is crossed to be interconnected from clock apparatus respectively with respectively；The source signal when clock synchronization system receives outside by master clock device, protects
When card is outside during the safe and reliable guarantee master clock device of source signal source select it is safe and reliable；The master clock device by according to
The clock receiving unit of secondary connection, clock unit and output unit composition, the clock synchronization system receive single in the clock
Reliability judge module is set in unit and clock unit.
2. the system of Power time synchronization system robust control as claimed in claim 1, it is characterised in that the clock is received
Unit includes satellite signal reception module, wire signal receiver module and reliability judge module；The reliability judge module
It is signaling security judge module；
The satellite reception module is used to receive the satellite-signal of at least two outside inputs；
The wire signal receiver module is used to receive wired time signal of at least one outside input；
The signaling security judge module is used to judge the security of input signal；
For the satellite-signal of outside input, change, the ephemeris parameter of the visible star of satellite-signal power, satellite are compared by detection
Update frequency and amplitude, carrier frequency, bit rate and its rate of change, satellite-signal number change, pseudorange residuals and deviations
Deng Deceiving interference and pressing type interference signal outside exclusion；It is defeated by detecting for wired time signal of outside input
Enter the continuity of signal, check bit, verification mode, temporal quality and exclude unstable insecure time source signal, so as to carry
The security of external input signal high.
3. the system of Power time synchronization system robust control as claimed in claim 1, it is characterised in that the clock unit
By crystal oscillator module, when source control module, local zone time module and information management module constitute；When described source control module be used for than
The time deviation of source and local zone time when relatively outside effective, and crystal oscillator is tamed in source when source is as synchronization when selecting the most reliable
And synchronous local zone time；
If in system electrification initial phase, when synchronization is selected behind source, the source time when master clock device is synchronous outside；If
After system completes initialization, when when local zone time and the synchronization selected, source time deviation is more than 1us, when source control module be used for
Source time when control local zone time Step wise approximation is synchronous, takes progressively near mode, and follow-up amplitude is not more than 1us/s, so that
Electric power is met by the application demand of time service equipment；
The information that described information management module is used to process between each master clock device is exchanged and command interaction, and information is entered
Row analysis collects.
4. the system of Power time synchronization system robust control as claimed in claim 1, it is characterised in that the output unit
For the time signal after master clock device synchronization to be converted into different types of time output letter by different signaling modules
Number；
The output unit includes IRIG-B yards of signaling module, pulse signal module, the serial ports for output power application signal
Message signals module and network message signaling module；The output signal of electric power application includes：The IRIG-B yards of signaling module is used
In IRIG-B yards of signal is exported, the pulse signal module is used for output pulse signal, and the serial ports message signals module is used for
Output serial ports message signals, the network message signaling module is used to export network message signal.
5. a kind of implementation method of the system for applying Power time synchronization system robust control as claimed in claim 1, it is special
Levy and be, the implementation method includes：
Step 1：Using the clock synchronization system of double master clock devices；
Step 2：Safe and reliable signal is received from clock apparatus, source signal and is completed together when double master clock devices receive outside
Step；
Step 3：The output signal of master clock device monitoring clock synchronization system each device is determining failed equipment；
Step 4：Determine the signal of the output of clock synchronization system and the time deviation of master clock device.
6. implementation method as claimed in claim 5, it is characterised in that in the step 1, when the clock synchronization system is used
During double master clock devices, two double master clock devices are mutually redundant, the source failure when a certain master clock device receives satellite-signal
When cannot be synchronous, another master clock device be source information when failure master clock is provided, it is ensured that double master clock device normal works.
7. implementation method as claimed in claim 5, it is characterised in that in the step 2, each receives two from clock apparatus
The IRIG-B signals of master clock, when one of master clock device signal fault, another master are automatically switched to from clock apparatus
On clock apparatus signal, it is ensured that receive safe and reliable signal from clock apparatus.
8. implementation method as claimed in claim 5, it is characterised in that in the step 3, the time is monitored by master clock device
The output signal of synchronization system each device to determine failed equipment, using passing through optical port wavelength-division multiplex on the basis of original wiring
Technology realizes that information communicates, and the both sides of optical fiber connection use same wavelength-division multiplex optical mode in the case of different wave length is received and dispatched
Block, while B yard of light is sent, the feedback information that monitoring other side sends, captures its rising edge time accuracy and information is decoded.
9. implementation method as claimed in claim 5, it is characterised in that in the step 4, in two masters, device receives outer all the time
Source signal and after completing synchronization during portion, one of master clock device receives another master clock device and each is filled from clock
IRIG-B yards of signal of output is put, and calculates each from the signal of clock apparatus output and the time of one of master clock device
Deviation, is designated as respectively：Δt11,Δt12,Δt13……Δt1n；Similarly, master clock 2 can receive master clock 1 and each
The IRIG-B yards of signal and calculating exported from clock deviate, and are designated as respectively：Δ t21, Δ t22, Δ t23 ... Δ t2n, Δ
T11 and Δ t21 are respectively between two master clock devices that one of master clock device and another master clock device are measured
Deviation, remaining is two master clock devices and the deviation from clock apparatus for measuring, one of master clock device and another
The deviation information that one master clock device is calculated by Network Synchronization, and one of master clock device serves as time synchronized
The manager of system, another master clock device serves as standby manager, when one of master clock device management work exception
When, by the management work of another master clock device completion system.
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