CN106788838B - System and method for robust control of power time synchronization system - Google Patents
System and method for robust control of power time synchronization system Download PDFInfo
- Publication number
- CN106788838B CN106788838B CN201611013953.7A CN201611013953A CN106788838B CN 106788838 B CN106788838 B CN 106788838B CN 201611013953 A CN201611013953 A CN 201611013953A CN 106788838 B CN106788838 B CN 106788838B
- Authority
- CN
- China
- Prior art keywords
- time
- master clock
- signal
- clock device
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000013307 optical fiber Substances 0.000 claims abstract description 14
- 230000001360 synchronised effect Effects 0.000 claims description 26
- 230000003287 optical effect Effects 0.000 claims description 15
- 230000009977 dual effect Effects 0.000 claims description 10
- 230000002159 abnormal effect Effects 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 9
- 238000013459 approach Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 4
- 230000001629 suppression Effects 0.000 claims description 4
- 230000003993 interaction Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
Abstract
The invention relates to a system and a method for robust control of a power time synchronization system, wherein the time synchronization system comprises at least two master clock devices and at least two slave clock devices, and the master clock devices are interconnected through optical fibers; the master clock device is interconnected with the slave clock device through an optical fiber; the time synchronization system is characterized in that a master clock device receives an external time source signal, the safety and the reliability of the external time source signal are guaranteed, namely the safety and the reliability of time source selection of the master clock device are guaranteed, the master clock device is composed of a clock receiving unit, a clock unit and an output unit which are sequentially connected, and the time synchronization system is provided with a reliability judging module on the clock receiving unit and the clock unit. The invention starts from a time synchronization system signal source, and avoids the interference of external unstable signals or maliciously distorted input source signals by introducing a plurality of external time sources and judging the signal safety of the input source, thereby selecting the most reliable time source as the synchronization time source of the main clock device and ensuring the reliability of the time source signals of the main clock device.
Description
Technical Field
The invention relates to the technical field of automatic equipment testing, in particular to a system and a method for robust control of a power time synchronization system.
Background
All levels of scheduling mechanisms, power plants, substations, centralized control centers and the like of the power grid need a uniform and accurate time reference to meet the requirements of various systems (such as a scheduling automation system, an energy management system, a production information management system and a monitoring system) and equipment (such as a relay protection device, intelligent electronic equipment, a time sequence recording SOE, automatic plant station control equipment, a safety and stability control device and a fault filter) on time synchronization, ensure the consistency of real-time data acquisition time, and improve the accuracy of line fault ranging, phasor and power angle dynamic measurement and unit and power grid parameter verification, thereby improving the level of power grid accident analysis and stable control and improving the operating efficiency and reliability of the power grid. The accuracy of the time synchronization of the power system is an important basic condition for guaranteeing the operation control and the fault analysis of the power system, and the safety and the reliability of the time synchronization system as a time service source in a station are very important.
The power time synchronization system mainly comprises a master clock device and a slave clock device. When the main clock device utilizes the satellite signal for time service, the satellite signal must be received from an open space by utilizing an antenna, a false satellite signal (deception signal) cannot be avoided from being received while a real satellite signal is received, if a receiving unit cannot identify the deception signal, the deception signal is used as the real signal, and the deception signal is utilized for time service, so that wrong time must be obtained, and serious consequences are caused. In addition, the master clock device has the problem of low source reliability when only one external synchronization is available; multiple external time sources reliable selection problem; the problem of discontinuous output signals and the like causes that a main clock device and a device with higher time accuracy dependence degree can not work normally, and accident analysis after an accident happens is influenced because of no accurate event occurrence time. The slave clock device receives a time synchronization signal sent by the master clock for synchronization, and provides the time synchronization signal for the time service equipment after synchronization is completed. However, in the application process, the monitoring of the internal devices of the time synchronization system is lacked, and when the time synchronization of a certain device is abnormal, the reliability of the system for outputting the time signal is affected.
Disclosure of Invention
In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a system and a method for robust control of a power time synchronization system, which starts from a time synchronization system signal source, eliminates interference of external unstable signals or input source signals which are maliciously tampered by introducing a plurality of external time sources and judging the signal security of the input sources, thereby selecting the most reliable time source as a synchronization time source of a master clock device and ensuring the reliability of the time source signals of the master clock device.
The purpose of the invention is realized by adopting the following technical scheme:
the invention relates to a system for robust control of a power time synchronization system, which is improved in that the time synchronization system comprises at least two master clock devices and slave clock devices, wherein the master clock devices are interconnected through optical fibers; each master clock device is respectively interconnected with each slave clock device through optical fibers; the time synchronization system receives an external time source signal by a master clock device, and ensures the safety and reliability of the external time source signal, namely the safety and reliability of time source selection of the master clock device; the master clock device is composed of a clock receiving unit, a clock unit and an output unit which are connected in sequence, and the time synchronization system is provided with a reliability judging module on the clock receiving unit and the clock unit.
Furthermore, the clock receiving unit comprises a satellite signal receiving module, a wired signal receiving module and a reliability judging module; the reliability judging module is a signal safety judging module;
the satellite receiving module is used for receiving at least two satellite signals input from the outside;
the wired signal receiving module is used for receiving at least one externally input wired time signal (such as an IRIG-B code signal);
the signal safety judgment module is used for judging the safety of the input signal;
for satellite signals input from the outside, by detecting and comparing the power of the satellite signals, the change of visible satellites of the satellite, the update frequency and amplitude of ephemeris parameters, carrier frequency, code rate and change rate thereof, the change of the number of the satellite signals, pseudo-range residual errors, positioning deviations and the like, the deceptive interference and the suppression interference signals from the outside are eliminated; for the externally input wired time signal, unstable unreliable time source signals are eliminated by detecting the continuity, check bits, check modes and time quality of the input signal, so that the safety of the externally input signal is improved.
Furthermore, the clock unit consists of a crystal oscillator module, a time source management module, a local time module and an information management module; the time source management module is used for comparing the time deviation between an external effective time source and local time, and selecting the most reliable time source as a synchronous time source to tame the crystal oscillator and synchronize the local time;
if the system is powered on and initialized, after the synchronous time source is selected, the master clock device synchronizes the external time source time; if the system is initialized, and when the deviation between the local time and the selected synchronous time source time is greater than 1us, the time source management module is used for controlling the local time to gradually approach the synchronous time source time, and a gradual approach mode is adopted, wherein the follow-up amplitude is not greater than 1us/s, so that the application requirement of the electric power time service equipment is met;
the information management module is used for processing information exchange and command interaction among the master clock devices and analyzing and summarizing information.
Furthermore, the output unit is used for converting the time signal synchronized by the master clock device into different types of time output signals through different signal modules;
the output unit comprises an IRIG-B code signal module, a pulse signal module, a serial port message signal module and a network message signal module, wherein the IRIG-B code signal module is used for outputting power application signals; the output signals of the power application include: the IRIG-B code signal module is used for outputting IRIG-B code signals, the pulse signal module is used for outputting pulse signals, the serial port message signal module is used for outputting serial port message signals, and the network message signal module is used for outputting network message signals.
The invention also provides an implementation method of the application power time synchronization system, and the improvement is that the implementation method comprises the following steps:
step 1: a time synchronization system using a dual master clock device;
step 2: the slave clock device receives safe and reliable signals, and the double-master clock device receives external time source signals and completes synchronization;
and step 3: the master clock device monitors output signals of all devices of the time synchronization system to determine a fault device;
and 4, step 4: the time offset of the signal of the output of the time synchronization system and the master clock device is determined.
Further, in step 1, when the time synchronization system adopts dual master clock devices, the two dual master clock devices are redundant to each other, and when a source failure cannot be synchronized when a certain master clock device receives a satellite signal, the other master clock device provides time source information for the failed master clock, so that the dual master clock devices are ensured to work normally.
Further, in step 2, each slave clock device receives IRIG-B signals of two master clocks, and when one master clock device fails, the slave clock device automatically switches to the other master clock device, so as to ensure that the slave clock device receives safe and reliable signals.
Further, in step 3, the output signals of the devices of the time synchronization system are monitored by the master clock device to determine a faulty device, information communication is realized by an optical port wavelength division multiplexing technology on the basis of the original wiring, both the two parties of the optical fiber connection adopt the same wavelength division multiplexing optical module under the condition of transmitting and receiving different wavelengths, and the feedback information sent by the other party is monitored while the optical B code is sent, so that the accuracy of the rising edge time and the information decoding are captured.
Further, in step 4, after the two master/slave devices receive the external time source signal and complete synchronization, one of the master clock devices receives the IRIG-B code signal output by the other master clock device and each of the slave clock devices, and calculates a time offset between the signal output by each of the slave clock devices and one of the master clock devices, which is expressed as: Δ t11, Δ t12, Δ t13 … … Δ t1 n; similarly, the master clock 2 may receive the IRIG-B code signals output by the master clock 1 and the slave clocks, and calculate the deviation, which is respectively recorded as: Δ t21, Δ t22, Δ t23 … …, Δ t2n, Δ t11 and Δ t21 are respectively the measured deviations between two master clock devices of one master clock device and the other master clock device, and the rest are the measured deviations between the two master clock devices and the slave clock devices, wherein the deviation information calculated by network synchronization of the one master clock device and the other master clock device is obtained, one master clock device serves as a manager of the time synchronization system, the other master clock device serves as a standby manager, and when the management work of one master clock device is abnormal, the management work of the system is completed by the other master clock device.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
Compared with the closest prior art, the technical scheme provided by the invention has the following excellent effects:
1. the robust control system of the power time synchronization system and the implementation method thereof ensure the safety and reliability of external input sources of the time synchronization system, and eliminate the interference of external unstable signals or input source signals which are maliciously distorted by starting from a time synchronization system signal source and introducing a plurality of external time sources and judging the signal safety of the input sources, thereby selecting the most reliable time source as the synchronization time source of a main clock device and ensuring the reliability of the time source signals of the main clock device; on the other hand, the closed loop of the time synchronization system is realized through robust control, the master clock device monitors all devices of the time synchronization system by using an optical port wavelength division multiplexing technology, and the clock device with abnormal time synchronization is found and adjusted in time, so that the safety and the reliability of power time service are ensured. Even under the special condition that the source jumps when the external device is used, the continuous stability of the time signal output by the time synchronization system is controlled in a software control mode.
The selectivity of the time source of the master clock device is improved by increasing the input quantity of the external time source of the master clock device, the signal security module is utilized to prevent deceptive interference and suppression type interference signals from influencing the synchronous time source of the master clock device, deception of some malicious input signals is avoided, the time source control module can select the most safe and reliable time synchronization time source from a plurality of external time source signals, the normal work of the master clock device is ensured, time synchronization signals are provided for the slave clock, and the safety of a system is ensured on the slave signal source.
2. The internal operation of the time synchronization system is ensured to be safe and reliable.
The time synchronization system forms a closed loop through robust control, each device in the time synchronization system is monitored and managed by the main clock device, once a problem is found, alarm information is generated in time, and a fault device is compensated and adjusted through monitoring data and information to output a reliable time signal, so that the internal operation safety of the system is ensured. Meanwhile, the time source control module synchronizes the local time in a step-by-step follow-up mode according to the selected synchronous time source time and the local time, so that the jumping of the output time signal is avoided, the overall reliability of the clock device is improved, and a safe and reliable time synchronization signal is provided for the whole power system timed device.
Drawings
FIG. 1 is a block diagram of a master clock apparatus provided by the present invention;
FIG. 2 is a schematic diagram of a closed loop of the time synchronization system provided by the present invention;
FIG. 3 is a block diagram of the wavelength division multiplexing of the optical port provided by the present invention;
fig. 4 is an application schematic diagram of the master clock device of the intelligent substation provided by the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims. Embodiments of the invention may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
Example one
The invention has proposed a system and its implement method of robust control of electric power time synchronization system, start from the signal source of the time synchronization system through this method, through introducing multiple external time sources and judging the signal security of the source of input, stop the source signal of input of the interference or malicious tampering of the external unstable signal, thus elect the most reliable time source as the synchronous time source of the main clock device, guarantee the reliability of the source signal of the main clock device; on the other hand, the closed loop of the time synchronization system is realized through robust control, the master clock device monitors all devices of the time synchronization system by using an optical port wavelength division multiplexing technology, and the clock device with abnormal time synchronization is found and adjusted in time, so that the safety and the reliability of power time service are ensured. Even under the special condition that the source jumps when the external device is used, the continuous stability of the time signal output by the time synchronization system is controlled in a software control mode.
As shown in fig. 1, for the structure diagram of the master clock apparatus provided by the present invention, the time synchronization system receives an external time source signal from the master clock apparatus, and in order to ensure the safety and reliability of the external time source signal, that is, to ensure the safety and reliability of the time source selection of the master clock apparatus. The master clock device mainly comprises a clock receiving unit, a clock unit and an output unit, and is specifically shown in fig. 1. The reliability judging module is added to the receiving unit and the clock unit to provide the overall safe reliability of the main clock device.
The clock receiving unit consists of a satellite receiving module, a wired time signal input module and a signal safety judgment module. The satellite receiving module should receive at least two satellite signals, and the cable time signal input module should receive at least one cable time signal (e.g., IRIG-B code signal). By increasing the number of external input sources of the main clock device, the multi-selectivity of source signals of the main clock device is improved, and the problem that the device cannot work due to single source failure is avoided. Meanwhile, a signal safety judgment module is added to judge the safety of the input signal. For satellite signals input from the outside, by detecting and comparing the power of the satellite signals, the change of visible satellites of the satellite, the update frequency and amplitude of ephemeris parameters, carrier frequency, code rate and change rate thereof, the change of the number of the satellite signals, pseudo-range residual errors, positioning deviations and the like, the deceptive interference and the suppression interference signals from the outside are eliminated; for the externally input wired time signal, unstable unreliable time source signals are eliminated by detecting the continuity, check bits, check modes, time quality and the like of the input signal, so that the safety of the externally input signal is improved.
The clock unit consists of a crystal oscillator module, a time source management module and a local time and information management module. The time source management module is used for comparing the time deviation between the external effective time source and the local time, so that the most reliable time source is selected as the synchronous time source to tame the crystal oscillator and synchronize the local time. If the device is in a power-on initialization stage, after a synchronous time source is selected, the main clock device quickly synchronizes the external time source time; if the device finishes initialization, when the deviation between the local time and the selected synchronous source time is larger than 1us, the source time management module controls the local time to gradually approach the synchronous source time to avoid instantaneous large step following, a gradual following mode is adopted, and the following amplitude is not larger than 1us/s, so that the application requirement of the power time-served device is met. The information management module is used for processing information exchange and command interaction among the clocks, analyzing and summarizing information and the like.
The output unit is used for converting the time signals after the clock device is synchronized into different types of time output signals through different modules, and the output signals of the power application mainly comprise: IRIG-B code signals, pulse signals, serial port message signals, network message signals and the like.
The safety and reliability of the external source signal can be ensured from the signal source, but the time synchronization abnormity caused by the internal fault of the system can not be ensured, so that the safety and reliability of the whole system can be further ensured through closed loop.
Example two
The invention also provides a method for realizing the robust control system of the power time synchronization system, which is based on the closed-loop design and realization of the robust control time synchronization system and comprises the following steps:
step 1: a time synchronization system using a dual master clock device;
step 2: the slave clock device receives safe and reliable signals, and the double-master clock device receives external time source signals and completes synchronization;
and step 3: the master clock device monitors output signals of all devices of the time synchronization system to determine a fault device;
and 4, step 4: the time offset of the signal of the output of the time synchronization system and the master clock device is determined.
The method comprises the steps that a main clock 1 and a main clock 2 are connected through optical fibers to obtain time synchronization deviation of each other, information is synchronized in a network mode, the main clock 1 and the main clock 2 are connected with each slave clock through the optical fibers respectively, deviation of output signals of each slave clock device is obtained through a wavelength division multiplexing technology, when a device with overlarge deviation is found, the main clock issues commands through the network to adjust the device, and reliability of the output signals is recovered to the maximum extent. The main clock 1 is used as a manager of the system, the main clock 2 is used as a standby manager, and when the main clock 1 fails, the main clock 2 completes monitoring and management of the system to ensure safety and reliability of the time synchronization system, so that the time synchronization system forms a closed loop, as shown in fig. 2.
In fig. 3, the clock device uses a wavelength division multiplexing optical module, one of which has a transmitting wavelength of 850nm and a receiving wavelength of 1510 nm; the other uses the same wavelength division multiplexing optical module, and has a transmission wavelength of 1510nm and a reception wavelength of 850 nm. The optical fiber signals with two wavelengths are transmitted in the same optical fiber at the same time without mutual influence.
Specifically, the method comprises the following steps:
in step 1, the time synchronization system adopts a dual master clock configuration, as shown in fig. 2. The main clocks 1 and 2 are interconnected through optical fibers and send IRIG-B information, when a source fault cannot be synchronized when one main clock receives satellite signals, the other main clock can provide time source information for the fault main clock, and therefore the two main clocks can work normally.
In step 2, each master clock and each slave clock are also interconnected through optical fibers, each slave clock receives IRIG-B signals of two master clocks, and when one master clock signal fails, the slave clock can be automatically switched to the other master clock signal, so that the slave clock is ensured to receive safe and reliable signals.
In step 3, the received time source signal is safe and reliable, and the signal output by the clock device cannot be ensured to be safe and reliable, so that the invention designs that the output signal of each device of the time synchronization system is monitored by the main clock to determine a fault device, in order to avoid increasing wiring, information communication is realized by the optical port wavelength division multiplexing technology on the basis of the original wiring, two sides of optical fiber connection adopt the same wavelength division multiplexing optical module under the condition of receiving and transmitting different wavelengths, and when transmitting an optical B code, the feedback information transmitted by the other side is also monitored, the time accuracy of the rising edge of the feedback information is captured, and information decoding is carried out, if the transmitting wavelength of one side is 850nm, and the receiving wavelength is 1510 nm; the other one uses the same wavelength division multiplexing optical module, and has a transmission wavelength of 1510nm and a reception wavelength of 850nm, as shown in fig. 3.
In step 4, after the master clock 1 and the master clock 2 receive the external time source signal and complete synchronization, the master clock 1 may receive the IRIG-B code signal output by the master clock 2 and each slave clock, and may calculate the time deviation between the signal output by each device and the master clock 1, which is respectively expressed as: Δ t11, Δ t12, Δ t13 … … Δ t1 n; similarly, the master clock 2 may receive the IRIG-B code signals output by the master clock 1 and the slave clocks, and may calculate an offset, which is respectively denoted as: the time synchronization system comprises a main clock 1, a main clock 2, a time synchronization system, a clock synchronization system and a clock synchronization system, wherein the time synchronization system comprises Δ t21, Δ t22, Δ t23 … … Δ t2n, Δ t11 and Δ t21 which are respectively the deviations between the. According to the technical specification of the power system time synchronization system, the time accuracy of the IRIG-B output by the clock device is better than 1 μ s, so that under the normal working condition of the time synchronization system, the absolute values of the Δ t11, the Δ t12, the Δ t13 … …, the Δ t1n, the Δ t21, the Δ t22 and the Δ t23 … …, the Δ t2n are not more than 1 μ s. If the time synchronization of the clock n is abnormal when delta t1n and delta t2n (n >1) are both larger than 1 mu s at a certain moment, the time synchronization of the clock n is represented, at the moment, the main clock 1 generates alarm information and sends a command to acquire the current time source selection information of the clock n, if the selected time source is the main clock 1, the main clock sends delta t1n to the clock device n, the clock device n compensates delta t1n for an output signal after acquiring deviation, and a stepping compensation mode is adopted to avoid generating large jitter; if the time source selected by the clock n is the master clock 2, the master clock 1 transmits Δ t2n to the clock n, and compensation is performed in the same manner, so that a device with abnormal time synchronization can output a reliable time signal.
EXAMPLE III
Fig. 4 shows a typical application example of the time synchronization system of the intelligent substation, in which a master clock 1 and a master clock 2 are used as backup, the master clock 1 provides a time synchronization signal for the station control layer device, and the slave clock receives IRIG-B signals output by the master clock 1 and the master clock 2 and provides a time synchronization signal for the measurement and control device and the protection device after synchronization is completed.
The method can be applied to the design of a time synchronization system in the intelligent substation, and an application schematic diagram is shown in fig. 4. The master clock device is deployed on a station control layer and adopts double-master clock configuration, wherein a master clock 1 is a master clock, a master clock 2 is a standby clock, and communication of the double master clocks is realized by associating IRIG-B signals. According to the design of the clock device, the clock device is used for receiving external GPS signals, BDS signals and wired input signals as input sources of the main clock device, malicious deception signals are eliminated through the signal safety judgment module, and the most reliable time source is selected from the input effective time sources through the time source management module to serve as a synchronous time source synchronous local time. And after the synchronization is finished, the master clock device outputs an NTP signal and an IRIG-B code signal to synchronize the in-station equipment. The monitoring host, the network shutdown device and the like of the station control layer receive NTP signals sent by the main clock as synchronous time signals of the device, and the measurement and control device and the protection device receive IRIG-B code signals output by the clock device as time synchronous signals of the device. For a large-scale transformer substation, a slave clock can be deployed in each small room, the slave clock receives an IRIG-B code signal of a master clock to realize synchronization of the slave clock, and the IRIG-B code signal is output after synchronization to provide a synchronization time signal for a measurement and control device and a protection device in the small room. The time source management module in the main clock device can compare the difference value between the external time source time and the local time in real time, even when the external time source time jumps, the output signal of the clock device is protected to be continuous and stable and gradually approaches to the selected external time signal, so that the jump of the output signal is avoided, and the time service device can be ensured to receive reliable and continuous time signals. In the whole time synchronization system, the safety and the reliability of a signal source input by the system are ensured through robust control, a master clock device is used as a management end of the time synchronization system in the system to monitor the time synchronization state of each device in the system, and when a device with abnormal time synchronization is found, the master clock can generate alarm information and carry out parameter adjustment on the device with abnormal time synchronization through robust control so as to ensure the safety and the reliability of the time signal output of the time synchronization system.
Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can make modifications and equivalents to the embodiments of the present invention without departing from the spirit and scope of the present invention, which is set forth in the claims of the present application.
Claims (5)
1. A system for robust control of a power time synchronization system is characterized in that the time synchronization system comprises at least two master clock devices and slave clock devices, wherein the master clock devices are interconnected through optical fibers; each master clock device is respectively interconnected with each slave clock device through optical fibers; the time synchronization system receives an external time source signal by a master clock device, and ensures the safety and reliability of the external time source signal, namely the safety and reliability of time source selection of the master clock device; the master clock device consists of a clock receiving unit, a clock unit and an output unit which are connected in sequence, and the time synchronization system is provided with a reliability judgment module on the clock receiving unit and the clock unit;
the clock unit consists of a crystal oscillator module, a time source management module, a local time module and an information management module; the time source management module is used for comparing the time deviation between an external effective time source and local time, and selecting the most reliable time source as a synchronous time source to tame the crystal oscillator and synchronize the local time;
if the system is powered on and initialized, after the synchronous time source is selected, the master clock device synchronizes the external time source time; if the system is initialized, and when the deviation between the local time and the selected synchronous time source time is greater than 1us, the time source management module is used for controlling the local time to gradually approach the synchronous time source time, and a gradual approach mode is adopted, wherein the follow-up amplitude is not greater than 1us/s, so that the application requirement of the electric power time service equipment is met;
the information management module is used for processing information exchange and command interaction among the master clock devices and analyzing and summarizing information;
the output unit is used for converting the time signals synchronized by the master clock device into different types of time output signals through different signal modules;
the output unit comprises an IRIG-B code signal module, a pulse signal module, a serial port message signal module and a network message signal module, wherein the IRIG-B code signal module is used for outputting power application signals; the output signals of the power application include: the IRIG-B code signal module is used for outputting an IRIG-B code signal, the pulse signal module is used for outputting a pulse signal, the serial port message signal module is used for outputting a serial port message signal, and the network message signal module is used for outputting a network message signal;
the clock receiving unit comprises a satellite signal receiving module, a wired signal receiving module and a reliability judging module; the reliability judging module is a signal safety judging module;
the satellite signal receiving module is used for receiving at least two satellite signals input from the outside;
the wired signal receiving module is used for receiving at least one externally input wired time signal;
the signal safety judgment module is used for judging the safety of the input signal;
for satellite signals input from the outside, by detecting and comparing the power of the satellite signals, the change of visible satellites of the satellite, the update frequency and amplitude of ephemeris parameters, carrier frequency, code rate and change rate thereof, the change of the number of the satellite signals, pseudo-range residual errors and positioning deviations, the deception jamming and suppression jamming signals from the outside are eliminated; for the externally input wired time signal, unstable unreliable time source signals are eliminated by detecting the continuity, check bits, check modes and time quality of the input signal, so that the safety of the externally input signal is improved.
2. An implementation method of a system applying robust control of a power time synchronization system according to claim 1, the implementation method comprising:
step 1: a time synchronization system using a dual master clock device;
step 2: the slave clock device receives safe and reliable signals, and the double-master clock device receives external time source signals and completes synchronization;
and step 3: the master clock device monitors output signals of all devices of the time synchronization system to determine a fault device;
and 4, step 4: determining a time offset of a signal of an output of the time synchronization system and the master clock device;
in step 4, after the two master clock devices receive the external time source signal and complete synchronization, one of the master clock devices receives the IRIG-B code signal output by the other master clock device and each of the slave clock devices, and calculates the time offset between the signal output by each of the slave clock devices and one of the master clock devices, which is respectively expressed as: Δ t11, Δ t12, Δ t13 … … Δ t1 n; similarly, the master clock 2 may receive the IRIG-B code signals output by the master clock 1 and the slave clocks, and calculate the deviation, which is respectively recorded as: Δ t21, Δ t22, Δ t23 … …, Δ t2n, Δ t11 and Δ t21 are respectively the measured deviations between two master clock devices of one master clock device and the other master clock device, and the rest are the measured deviations between the two master clock devices and the slave clock devices, wherein the deviation information calculated by network synchronization of the one master clock device and the other master clock device is obtained, one master clock device serves as a manager of the time synchronization system, the other master clock device serves as a standby manager, and when the management work of one master clock device is abnormal, the management work of the system is completed by the other master clock device.
3. The method as claimed in claim 2, wherein in step 1, when the time synchronization system employs dual master clock devices, the two dual master clock devices are redundant to each other, and when a source failure cannot be synchronized when one master clock device receives a satellite signal, the other master clock device provides time source information for the failed master clock, so as to ensure that the dual master clock devices operate normally.
4. The method as claimed in claim 2, wherein in step 2, each slave clock device receives IRIG-B signals of two master clocks, and when one master clock device fails, the slave clock device automatically switches to the other master clock device to ensure that the slave clock device receives safe and reliable signals.
5. The method of claim 2, wherein in step 3, the master clock device monitors the output signals of the devices of the time synchronization system to determine the faulty device, and the optical port wavelength division multiplexing technology is used to implement information communication based on the original wiring, and both the fiber-optic connection and the fiber-optic connection use the same wavelength division multiplexing optical module when transmitting and receiving different wavelengths, and when transmitting the optical B code, the feedback information from the other party is monitored, and the accuracy of the rising edge time and the information decoding are captured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611013953.7A CN106788838B (en) | 2016-11-18 | 2016-11-18 | System and method for robust control of power time synchronization system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611013953.7A CN106788838B (en) | 2016-11-18 | 2016-11-18 | System and method for robust control of power time synchronization system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106788838A CN106788838A (en) | 2017-05-31 |
| CN106788838B true CN106788838B (en) | 2020-08-18 |
Family
ID=58968882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611013953.7A Active CN106788838B (en) | 2016-11-18 | 2016-11-18 | System and method for robust control of power time synchronization system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106788838B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107831649A (en) * | 2017-11-01 | 2018-03-23 | 福州开发区慧聚通信技术有限公司 | Operating frequency phase wireless synchronization device |
| CN108063644A (en) * | 2017-11-27 | 2018-05-22 | 国网安徽省电力公司六安供电公司 | A kind of timing tracking accuracy verification and reliability evaluation system |
| CN108282243B (en) * | 2017-12-28 | 2019-06-07 | 清华大学 | A kind of clock source reliability guarantee method suitable for master-slave mode method for synchronizing time |
| CN111061147A (en) * | 2019-11-28 | 2020-04-24 | 南京国电南自电网自动化有限公司 | Wireless network-based regional intelligent substation time service system and method |
| CN111077759B (en) * | 2020-01-06 | 2021-03-26 | 中国科学院微小卫星创新研究院 | Performance evaluation method of spaceborne atomic clock |
| CN112327765A (en) * | 2020-10-20 | 2021-02-05 | 中国核电工程有限公司 | Design method for redundant time service architecture of distributed control system of nuclear power plant |
| CN112398565B (en) * | 2020-11-06 | 2022-06-28 | 华能新能源股份有限公司河北分公司 | Method and system for generating time scale adjusting instruction and adjusting time scale |
| CN115047938B (en) * | 2022-08-12 | 2022-11-04 | 浙江大学 | Clock synchronization method, system, electronic device and computer readable storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010149088A1 (en) * | 2009-12-10 | 2010-12-29 | 中兴通讯股份有限公司 | Method and system for implementing time synchronization in local area network (lan) |
| CN103513569A (en) * | 2013-09-17 | 2014-01-15 | 国家电网公司 | Method for synchronizing redundant time of intelligent substation |
| CN104125031A (en) * | 2014-06-26 | 2014-10-29 | 电信科学技术第五研究所 | Time synchronizing high-reliability source selecting method |
| CN104821870A (en) * | 2015-02-13 | 2015-08-05 | 北京科东电力控制系统有限责任公司 | Master station smart power grid scheduling technology support system-based clock synchronization method |
| CN105301951A (en) * | 2015-09-29 | 2016-02-03 | 国电南瑞科技股份有限公司 | Multi-source decision realization method of time synchronization system based on analytic hierarchy method |
-
2016
- 2016-11-18 CN CN201611013953.7A patent/CN106788838B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010149088A1 (en) * | 2009-12-10 | 2010-12-29 | 中兴通讯股份有限公司 | Method and system for implementing time synchronization in local area network (lan) |
| CN103513569A (en) * | 2013-09-17 | 2014-01-15 | 国家电网公司 | Method for synchronizing redundant time of intelligent substation |
| CN104125031A (en) * | 2014-06-26 | 2014-10-29 | 电信科学技术第五研究所 | Time synchronizing high-reliability source selecting method |
| CN104821870A (en) * | 2015-02-13 | 2015-08-05 | 北京科东电力控制系统有限责任公司 | Master station smart power grid scheduling technology support system-based clock synchronization method |
| CN105301951A (en) * | 2015-09-29 | 2016-02-03 | 国电南瑞科技股份有限公司 | Multi-source decision realization method of time synchronization system based on analytic hierarchy method |
Non-Patent Citations (1)
| Title |
|---|
| 贵州电网智能变电站时间同步系统的应用;王琳;《贵州电力技术》;20160930;第19卷(第9期);160-164 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106788838A (en) | 2017-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106788838B (en) | System and method for robust control of power time synchronization system | |
| US8275486B2 (en) | Electric power system automation using time coordinated instructions | |
| US9709682B2 (en) | Multi-constellation GNSS integrity check for detection of time signal manipulation | |
| US7617408B2 (en) | System and method for providing accurate time generation in a computing device of a power system | |
| US9319100B2 (en) | Delay compensation for variable cable length | |
| US10288741B2 (en) | Multi-constellation GNSS integrity check for detection of time signal manipulation | |
| US9083503B2 (en) | Synchronized clock event report | |
| MX2015001972A (en) | Quality of precision time sources. | |
| MX2011010035A (en) | Fault tolerant time synchronization. | |
| MX2015004152A (en) | Manipulation resilient time distribution network. | |
| CN103338102B (en) | A kind of time synchronization system in nuclear power plant | |
| MX2015003976A (en) | Detection of manipulated satellite time signals. | |
| CN103209069A (en) | Time synchronization device and method based on precise time protocol | |
| CN111698052B (en) | Homologous time synchronization system crossing power safety zone | |
| CN113141227B (en) | Time determination method, system and medium based on hierarchical control | |
| MX2015006705A (en) | Multi-constellation gnss integrity check for detection of time signal manipulation. | |
| Yin et al. | Research on Time Synchronization Monitoring Technology of Nuclear Power Station | |
| MX2015006701A (en) | Multi-constellation gnss integrity check for detection of time signal manipulation. | |
| CN117880953A (en) | Remote monitoring method and system for time service precision of power time synchronization device | |
| CN117014093A (en) | Time setting method and device | |
| KR20170104305A (en) | Relay and synchronization system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |