CN108600748A - The method that FPGA detects video signal transmission failure in laser television - Google Patents
The method that FPGA detects video signal transmission failure in laser television Download PDFInfo
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- CN108600748A CN108600748A CN201810709521.2A CN201810709521A CN108600748A CN 108600748 A CN108600748 A CN 108600748A CN 201810709521 A CN201810709521 A CN 201810709521A CN 108600748 A CN108600748 A CN 108600748A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
- H04N17/045—Self-contained testing apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/004—Diagnosis, testing or measuring for television systems or their details for digital television systems
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Abstract
The invention discloses the method and apparatus that FPGA in a kind of laser television detects video signal transmission failure, belong to video signal treatment technique field.The receiving terminal and transmitting terminal of the FPGA forms the transmission link of vision signal, the method includes：When detect the semaphore lock state of the receiving terminal is abnormal, the receiving terminal parses the vision signal timing information occur mistake or the transmitting terminal semaphore lock state it is abnormal when, export fault-signal.Using the present invention, it can prevent laser television from persistently keeping the state of display mistake.
Description
The application be on February 24th, 2017 propose it is entitled " in laser television FPGA detect video signal transmission
The divisional application of the Chinese invention patent application 201710103358.0 of the method and apparatus of failure ".
Technical field
The present invention relates to video signal treatment technique field, more particularly to FPGA detects vision signal in a kind of laser television
The method and apparatus of transmission fault.
Background technology
With the development of technology, laser television has obtained extensive popularization.Present laser television is in order to meet video counts
A kind of VBO (V-By-One, video signal transmission standard) signal is all used according to the demand of transmission speed.
During laser television is shown, VBO signals can pass through SOC (System-On-Chip, system on chip),
FRC (Frame Rate Conversion, block diagram of frame rate converter), FPGA (Field-Programmable Gate Array, scene
Programmable gate array), the processing of the components such as DLP (Digital Light Processing, Digital Light Processor), then export
Display.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems：
FPGA is not fine to the Treatment Stability of VBO signals, causes the displays such as blank screen, white screen, Hua Ping, ghost image sometimes
Mistake occurs.
Invention content
In order to solve problems in the prior art, an embodiment of the present invention provides FPGA in a kind of laser television to detect video letter
The method and apparatus of number transmission fault.The technical solution is as follows：
In a first aspect, the method for providing FPGA detections video signal transmission failure in a kind of laser television, the FPGA
Receiving terminal and transmitting terminal formed vision signal transmission link, the method includes：
When detecting that the semaphore lock state of the receiving terminal is abnormal, the receiving terminal solves the vision signal
When the semaphore lock state of timing information generation mistake or the transmitting terminal that analysis obtains is abnormal, fault-signal is exported.
Optionally, normal in the semaphore lock state of the receiving terminal of the FPGA, detect connecing for the FPGA
Whether the timing information that receiving end parses the vision signal is correct；
It is correct in the timing information, whether just to detect the semaphore lock state of the transmitting terminal of the FPGA
Often.
Optionally, the semaphore lock state for detecting the receiving terminal is abnormal, including：
When detecting that the locking signal of the receiving terminal becomes high level, and to reach first default for the duration of high level
When duration, determine that the semaphore lock state of the receiving terminal is abnormal.
Optionally, the timing information for detecting that the receiving terminal parses the vision signal occurs
Mistake, including：
The timing information includes at least one of following sub-information：Hactive, Htotal, Vactive and
Vtotal；
According to predetermined period, detect in timing information under each corresponding current value of sub-information and current display mode
The continuous mismatch number of a reference value, and when any continuous mismatch number reaches predetermined threshold value, determine the timing letters
Mistake occurs for breath.
Optionally, the semaphore lock state for detecting the transmitting terminal is abnormal, including：
When detecting that the locking signal of the transmitting terminal becomes high level, and to reach second default for the duration of high level
When duration, determine that the semaphore lock state of the transmitting terminal is abnormal.
Second aspect provides a kind of device of FPGA detections video signal transmission failure in laser television, the FPGA
Receiving terminal and transmitting terminal form the transmission link of vision signal, described device includes：
Detection module, for when detecting that the semaphore lock state of the receiving terminal is abnormal, the receiving terminal is to described
When the semaphore lock state of timing information generation mistake or the transmitting terminal that vision signal is parsed is abnormal,
Export fault-signal.
Optionally, the detection module, is additionally operable to：
Semaphore lock state in the receiving terminal of the FPGA is normal, detects the receiving terminal of the FPGA to institute
Whether correct state the timing information that vision signal is parsed；
It is correct in the timing information, whether just to detect the semaphore lock state of the transmitting terminal of the FPGA
Often.
Optionally, the detection module, is used for：
When detecting that the locking signal of the receiving terminal becomes high level, and to reach first default for the duration of high level
When duration, determine that the semaphore lock state of the receiving terminal is abnormal.
Optionally, the detection module, is used for：
The timing information includes at least one of following sub-information：Hactive, Htotal, Vactive and
Vtotal；
According to predetermined period, detect in timing information under each corresponding current value of sub-information and current display mode
The continuous mismatch number of a reference value, and when any continuous mismatch number reaches predetermined threshold value, determine the timing letters
Mistake occurs for breath.
Optionally, the detection module, is used for：
When detecting that the locking signal of the transmitting terminal becomes high level, and to reach second default for the duration of high level
When duration, determine that the semaphore lock state of the transmitting terminal is abnormal.
The advantageous effect that technical solution provided in an embodiment of the present invention is brought is：
In the embodiment of the present invention, when detect the semaphore lock state of receiving terminal is abnormal, receiving terminal to vision signal into
When the semaphore lock state of timing information generation mistake or transmitting terminal that row parsing obtains is abnormal, fault-signal is exported.
Processing in this way can prevent laser television from persistently protecting after transmission fault occurs in laser television and leads to display mistake
Hold the state of display mistake.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of laser television provided in an embodiment of the present invention；
Fig. 2 is the method that FPGA detects video signal transmission failure in a kind of laser television provided in an embodiment of the present invention
Flow diagram；
Fig. 3 is the method that FPGA detects video signal transmission failure in a kind of laser television provided in an embodiment of the present invention
Flow diagram；
Fig. 4 is the device that FPGA detects video signal transmission failure in a kind of laser television provided in an embodiment of the present invention
Structural schematic diagram.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
An embodiment of the present invention provides the method that FPGA in a kind of laser television detects video signal transmission failure, this method
It can be realized by laser television.Wherein, laser television may include memory, FPGA, FRC, SOC, display unit (DLP),
The components such as the master controller of FPGA, equipment inner structure figure can be as shown in Figure 1.FPGA includes receiving terminal, transmitting terminal and signal
Processing module, receiving terminal are also referred to as Rx (Receiver is received) module, and transmitting terminal is also referred to as Tx (Transmitter, hair
Send) module, the transmission link of receiving terminal and transmitting terminal formation vision signal.Master controller can be used for the control to FPGA, example
Such as, the Rx modules of FPGA or Tx modules are carried out resetting operation etc..Memory can be RAM (Random Access
Memory, random access memory), Flash (flash memory) etc. can be used for storing needed for the data received, processing procedure
The data etc. generated in data, processing procedure, such as a reference value of each information in timing information, the first preset duration, second pre-
If duration, preset times threshold value etc..The different components of FPGA, FRC, SOC namely for video frequency signal processing.Display unit is
The component that output is finally shown for vision signal can be DLP, liquid crystal display etc..Laser television can also include transceiver unit,
Input part, audio output part, audio input means etc..Transceiver unit can be used for carrying out data transmission with miscellaneous equipment,
Such as bluetooth component, WiFi (wireless fidelity, Wireless Fidelity) component etc..Input part can be touch screen, keyboard,
Mouse etc..Audio output part can be speaker, earphone etc..Audio input means can be microphone etc..
The embodiment of the present invention by vision signal be VBO signals for carry out scheme detailed description, other situations with etc
Seemingly, the present embodiment is not repeated.
The method that FPGA detects video signal transmission failure in laser television provided in an embodiment of the present invention, can be in laser
TV completes starting up or completes the switching of different types of vision signal, and vision signal enter stable state after execute.It holds
Row main body is FPGA, and FPGA can upon failure detection, and exporting fault-signal in specific application can be by fault-signal
It is sent to the master controller of FPGA, which can be MCU (Microcontroller Unit, micro-control unit), use
In being controlled FPGA according to fault-signal.
As shown in Fig. 2, the process flow of this method may include following step：
Step 201, whether the semaphore lock state that detects receiving terminal is normal, receiving terminal is parsed to obtain to vision signal
Whether timing information correct, whether the semaphore lock state of transmitting terminal normal.
Whether detection FPGA occurs Rx losing locks, the timing (letters for reflecting video signal pixels point quantity whether occurs
Breath) information errors, Tx losing locks whether occur.
Wherein, FPGA can be made of multiple gate-controlled components, be can be used for carrying out geometric correction to the image of display, made figure
As view field and curtain region fit like a glove, to reach best display effect.Vision signal is before and after flowing through FPGA unit
And during flowing through FPGA unit itself, failure may be sent, fault type may include：The semaphore lock shape of receiving terminal
The timing that state is abnormal, receiving terminal parses vision signal (is used for the letter of reflecting video signal pixels point quantity
Breath) information errors, the semaphore lock state of transmitting terminal be abnormal.The semaphore lock state of receiving terminal can normally be referred to as Rx locks
Fixed, the semaphore lock state of receiving terminal is abnormal to can be referred to as Rx losing locks.The semaphore lock state of transmitting terminal can normally be referred to as Tx
Locking, the semaphore lock state of transmitting terminal is abnormal to can be referred to as Tx losing locks.
In force, FPGA may include Rx modules, signal processing module, Tx modules, and signal processing module can be used for
The parsing of vision signal, it is (effective that parsing obtains data-signal, synchronizing signal, clk (clock) signal, DE signals in VBO signals
Data strobe signal), timing information etc..FPGA can detect whether Rx modules occur Rx losing locks, and detect signal processing mould
Timing information errors whether occur in block, and detect whether Tx modules occur Tx losing locks.Rx losing locks can be used for reflecting Rx moulds
Block can not normally receive vision signal.Tx losing locks can be used for reflecting that DLP can not normally receive the video letter of FPGA transmissions
Number.Timing information may include at least one of following sub-information：Hactive (being shown displayed across pixel number) information,
Htotal (lateral actual pixels points) information, Vactive (longitudinal display pixel points) information and Vtotal (longitudinal practical pictures
Vegetarian refreshments number) information.It is to be appreciated that pixel not all in vision signal is all shown, so display pixel points are than real
Border pixel number will lack, and actual pixels points are the pixel numbers actually possessed in vision signal, and display pixel points are can
Shown pixel number.
Optionally, can be that certain detection ordering is arranged in different error situations, it can be according to " Rx losing locks → timing
The sequence of information errors → Tx losing locks " is detected.
Correspondingly, specific detection process can be：Whether the semaphore lock state for detecting receiving terminal is normal, in receiving terminal
Semaphore lock state it is normal in the case of, just whether the timing information that detection receiving terminal parses vision signal
Really, correct in timing information, whether the semaphore lock state for detecting transmitting terminal is normal.
As shown in figure 3, processing can be as follows：
Whether step 201a, detection FPGA occur Rx losing locks.
Step 201b, in the state that Rx losing locks do not occur for FPGA, whether detection FPGA occurs timing information errors.
Step 201c, in the state that timing information errors do not occur for FPGA, whether detection FPGA occurs Tx losing locks.
In force, FPGA can preferentially detect whether that Rx losing locks occur.If Rx losing locks have occurred, can not continue
Timing information errors and Tx losing locks are detected, and mistake is reported into master controller, if Rx losing locks do not occur, can be continued
It detects whether that timing information errors occur.In case of timing information errors, then can not continue to detect Tx losing locks, and will
Mistake reports to master controller, if timing information errors do not occur, can continue to detect whether that Tx losing locks occur.If
Tx losing locks have occurred, then mistake can have been reported to master controller, if Tx losing locks do not occur, can be not processed.
Optionally, the whether normal processing mode of semaphore lock state for detecting receiving terminal can be as follows：When detecting Rx
The locking signal of module becomes high level, and when the duration of high level reaches the first preset duration, determines the letter of receiving terminal
Number lock-out state is abnormal；When it is low level to detect the locking signal of Rx modules, alternatively, when the locking for detecting Rx modules
Signal becomes high level, and when the duration of high level is not up to the first preset duration, determines the semaphore lock shape of receiving terminal
State is normal.
In force, multiple pins are connected with each other between FPGA and FRC, respectively there are one pins on wherein FPGA and FRC
For locking signal pin, the two pins are connected with each other, and can be used for transmitting locking signal.Start or believe in laser television
Number switching when, handshake procedure can be carried out between FPGA and FRC.During shaking hands, FRC can draw high locking signal, locking letter
Number become high level, while FRC can be sent preset for shaking hands by the pin except locking signal pin to FPGA
Data.After FPGA receives the data for shaking hands, if there is no problem for data, locking signal can be dragged down, locking signal
Become low level.After FRC detects that locking signal is pulled low, then start to send vision signal to FPGA.Between SOC and FRC,
Video signal transmission between FRC and FPGA, between FPGA and DLP can carry out handshake procedure in a manner mentioned above.
During follow-up FRC sends vision signal to FPGA, if Rx modules do not receive vision signal, or do not solve
Vision signal is precipitated, then locking signal can be drawn high, locking signal becomes high level at this time.FPGA, which works as, detects that locking signal becomes
For high level when, then the duration of start recording high level then judges to occur when duration is more than the first preset duration
Rx losing locks.When the duration of high level is not up to the first preset duration, FPGA can consider, and Rx losing locks do not occur, alternatively,
When locking signal is low level, FPGA can consider, and Rx losing locks do not occur.Wherein, the first preset duration can be by technology
Personnel are arbitrarily arranged according to actual demand, such as 0.5 second.
Optionally, detection FPGA the processing modes of timing information errors whether occurs can be as follows：According to predetermined period,
Detect the continuous mismatch time of each corresponding current value of sub-information and a reference value under current display mode in timing information
Number, and when the corresponding continuous mismatch number of any sub-information reaches predetermined threshold value, determine that mistake occurs for timing information, such as
The corresponding continuous mismatch number of all sub-informations of fruit is all not up to predetermined threshold value, it is determined that timing information is correct.
Wherein, the corresponding current value of sub-information is mismatched with a reference value under current display mode, it is also assumed that being phase
There is mistake in the sub-information answered.
In force, FPGA can periodically detect Hactive information in timing information, Htotal information,
The correctness of Vactive information and Vtotal information, and correspond to one continuous errors number of each Information Statistics respectively, that is, it counts
4 continuous errors numbers.Often reach a cycle when, if Hactive information, Htotal information, Vactive information and
There is mistake in any information in Vtotal information, then the continuous errors number of the information is added 1, for the letter not malfunctioned
Breath, then by its corresponding continuous errors number clear 0.It is then possible to either with or without reaching in judging 4 continuous errors numbers of statistics
Preset times threshold value reaches preset times threshold value if there is the corresponding continuous errors number of one or more information, then judges
Timing information errors occur, if the corresponding continuous errors number of any information is all not up to preset times threshold value, it is determined that
Timing information errors do not occur.
Optionally, can be arranged Hactive information under different display patterns, Htotal information, Vactive information and
The a reference value of Vtotal information judges Hactive information, Htotal information, Vactive information and Vtotal by a reference value
Whether information occurs mistake, and corresponding processing may include steps of：
Step 1 obtains the first current display pattern.
Wherein, display pattern may include 2D (two-dimensional, two dimension) pattern, 3D (three-
Dimensional, three-dimensional) pattern (pattern that can be watched by 3D eyes) etc..
In force, display pattern can automatically be set by user setting, or by laser television according to current vision signal
It sets.When executing the method for the embodiment of the present invention, the display pattern (i.e. the first display pattern) of current setting can be obtained.
Step 2, according to pre-stored Hactive information, Htotal information, Vactive information and Vtotal information
The correspondence of a reference value and display pattern determines Hactive information under the first display pattern, Htotal information, Vactive letters
The a reference value of breath and Vtotal information.
In force, laser television just set for it and has been regarded under different display modes in production phase, technical staff
The Hactive information of frequency signal, the numerical value of Htotal information, Vactive information and Vtotal information, normal vision signal is all
Meet these numerical value, these numerical value may act as under different display modes Hactive information, Htotal information,
The a reference value of Vactive information and Vtotal information.A reference value table can be set up in video output device, as shown in table 1.
Table 1
| Display pattern | Hactive information | Htotal information | Vactive information | Vtotal information |
| 2D patterns | 3840 | 4472 | 2160 | 2236 |
| 3D patterns | 1920 | 2180 | 1080 | 1146 |
It is corresponding can to search the first display pattern after obtaining the first current display pattern in a reference value table by FPGA
Each a reference value.
Step 3, if the current value of Hactive information is mismatched with a reference value under the first display pattern, it is determined that
Mistake occurs for Hactive information, otherwise determines that mistake does not occur for Hactive information；If the current value of Htotal information and the
A reference value under one display pattern mismatches, it is determined that mistake occurs for Htotal information, otherwise determines that Htotal information does not occur
Mistake；If the current value of Vactive information is mismatched with a reference value under the first display pattern, it is determined that Vactive information
Mistake occurs, otherwise determines that mistake does not occur for Vactive information；If under the current value of Vtotal information and the first display pattern
A reference value mismatch, it is determined that Vtotal information occur mistake, otherwise determine Vtotal information mistake does not occur.
In force, in normal vision signal, Hactive information, Htotal information, Vactive information and
The numerical value of Vtotal information is should be identical with corresponding a reference value, allows for smaller deviation.Due to swinging of signal
Fixed reason, may be such that Hactive information, Htotal information, Vactive information and Vtotal information numerical value occur compared with
Big deviation, if the difference of certain information current value and a reference value is more than predetermined threshold value, it may be considered that the current value of the information
It is mismatched with a reference value, and then judges that mistake occurs for the information.
Optionally, the whether normal processing mode of semaphore lock state for detecting transmitting terminal can be as follows：When detecting Tx
The locking signal of module becomes high level, and when the duration of high level reaches the second preset duration, determines the letter of transmitting terminal
Number lock-out state is abnormal；When it is low level to detect the locking signal of Tx modules, alternatively, when the locking for detecting Tx modules
Signal becomes high level, and when the duration of high level is not up to the second preset duration, determines the semaphore lock shape of transmitting terminal
State is normal.
In force, multiple pins are connected with each other between FPGA and DLP, respectively there are one pins on wherein FPGA and DLP
For locking signal pin, the two pins are connected with each other, and can be used for transmitting locking signal.Start or believe in laser television
Number switching when, handshake procedure can be carried out between FPGA and DLP.During shaking hands, FPGA can draw high locking signal, locking letter
Number become high level, while FPGA can be sent preset for shaking hands by the pin except locking signal pin to DLP
Data.After DLP receives the data for shaking hands, if there is no problem for data, locking signal can be dragged down, locking signal is
Become low level.After FPG detects that locking signal is pulled low, then start to send vision signal to DLP.
During follow-up FPGA sends vision signal to DLP, if the Rx modules of DLP do not receive vision signal,
Or do not parse vision signal, then locking signal can be drawn high, locking signal becomes high level at this time.FPGA, which works as, detects Tx moulds
When the locking signal of block becomes high level, then the duration of start recording high level, when duration is more than second default
When long, then judge that Tx losing locks occur.When the duration of high level is not up to the second preset duration, FPGA can consider and not send out
Raw Tx losing locks, alternatively, when locking signal is low level, FPGA can consider, and Tx losing locks do not occur.Wherein, second is default
Duration can be arbitrarily arranged by technical staff according to actual demand, such as 0.5 second.
Step 202, when detecting that the semaphore lock state of receiving terminal is abnormal or receiving terminal parses vision signal
When the semaphore lock state of obtained timing information errors or transmitting terminal is abnormal, failure is transmitted to vision signal and is repaiied
It is multiple.
In force, in laser television, it can be provided with register, when FPGA detects Rx losing locks, timing information
When any error event in mistake, Tx losing locks occurs, FPGA can determine that fault type is Rx losing locks, timing information errors
Or Tx losing locks, FPGA can be by fault type record in a register at this time.Meanwhile it can be sent to master controller and interrupt letter
Number, interrupt signal is used to that master controller to be notified to stop current other work, carries out the reparation of video signal transmission failure.Master control
After device processed receives interrupt signal, it is possible to determine that transmission fault occurs in vision signal, and then can inquire register to determine event
Hinder type.Hereafter, master controller can take corresponding reclamation activities, reclamation activities can be varied, can be with based on personnel
It is pre-set according to actual demand.For example, reclamation activities can be that laser television is resetted and (restarted).
Optionally, can fault restoration be transmitted to vision signal as follows, respective handling can be as follows：When
Detect that the timing that the semaphore lock state of receiving terminal is abnormal or receiving terminal parses the vision signal believes
When breath mistake or the abnormal semaphore lock state of transmitting terminal, controls the block diagram of frame rate converter FRC being connect with FPGA and carry out reset behaviour
Make.
In force, after the transmission fault of vision signal occurs in FPGA, laser television will appear blank screen, white screen, Hua Pinghuo
The wrong phenomenon of the display such as ghost image, if being repaired without transmission fault, laser television can be continued for blank screen, white screen, flower
Screen or ghost image.FPGA is detected sends interrupt signal after error event to master controller, and master controller is receiving interrupt signal
When, FRC can be controlled and carry out reset operation.In this way, FRC will carry out handshake procedure, success of shaking hands with FPGA and SOC again
Afterwards, subsequent video signal transmission can be carried out.Phenomena such as blank screen, white screen, flower screen or ghost image can thus be terminated, laser television
It can show correct image.Of course it is not excluded after FRC resets operation, what video signal transmission failure occurred again in FPGA can
Energy property, in this case, FPGA can detect error event again, and then send interrupt signal, master controller to master controller
Above-mentioned transmission fault repair process is carried out again, that is, repeats the above flow.
Optionally, can be in such a way that the different fault type of face carry out different fault restorations, respective handling can be as follows：
Situation one, when fault type be receiving terminal semaphore lock state is abnormal or receiving terminal parses vision signal
When timing information errors, reset operation is carried out to receiving terminal；Situation two, when the semaphore lock state that fault type is transmitting terminal
When abnormal, reset operation is carried out to transmitting terminal.
In force, when fault type is Rx losing locks or timing information errors, master controller can control Rx modules
Carry out reset operation.When fault type is Tx losing locks, master controller can control Tx modules and carry out reset operation.
When carrying out above-mentioned reset operation, some other operation processings can also be carried out according to the difference of fault type,
Different explanations is carried out to the above situation one and situation two separately below.
Situation one
Optionally, after carrying out reset operation to receiving terminal, it can also be handled as follows and ensure that FPGA enters stable shape
State：According to the semaphore lock state of preset cycle detection receiving terminal；Judge that whether continuous the semaphore lock state of receiving terminal is N number of
Period is normal, if so, terminating, to the detection of the semaphore lock state of receiving terminal, to be resetted if it is not, then controlling and receiving end
Operation, and continue to detect the semaphore lock state of receiving terminal；Vision signal is solved according to preset cycle detection receiving terminal
Analyse obtained timing information；Judging timing information, whether the continuous N period is correct, if so, terminating to believe timing
Whether just the detection of breath if it is not, then controlling and receiving end carries out reset operation, and continues the semaphore lock state of detection receiving terminal
Often；Wherein, N and M is preset positive integer.
Specifically, after the Rx modules to FPGA carry out reset operation (step a0), following steps a1- can also be carried out
The processing of a5：
Whether step a1 occurs Rx losing locks according to preset cycle detection FPGA.
Step a2 carries out reset operation to the Rx modules of FPGA again if detecting Rx losing locks.
Step a3 terminates the periodicity inspection to Rx losing locks if Rx losing locks are not detected within continuous N number of period
It surveys, and timing information errors whether occurs according to preset cycle detection FPGA.
Step a4 carries out reset operation to the Rx modules of FPGA again if detecting timing information errors.
Step a5 terminates if timing information errors are not detected within the continuous M period to timing information
Mistake is periodically detected；Wherein, N and M is preset positive integer.
Optionally, when carrying out above-mentioned steps a1-a5 detections, Tx modules can be placed in reset state, it is corresponding to handle
Can be：When fault type be receiving terminal semaphore lock state is abnormal or receiving terminal parses vision signal
When timing information errors, control transmitting terminal keeps reset state；After terminating to the detection of timing information, control is sent
Reset state is exited at end.
Specific processing can be as follows：When fault type be Rx losing locks or timing information errors when, control Tx modules into
Enter and keeps reset state (step a0 ')；After terminating to being periodically detected of timing information errors, control Tx modules are moved back
Go out reset state (step a6).Step a0 ' can be executed before step a0.
Wherein, it is that certain component of control or equipment are introduced into the operation that reset state exits reset state again to reset operation, multiple
Position state is idle state.
In this way, when fault type is Rx losing locks or timing information errors, main controller controls Tx modules enter and protect
Reset state is held, Tx modules will not continue to work, then vision signal will not be transferred to subsequent component, to show figure
Picture.Because when carrying out above-mentioned steps a1-a5 detections, it can't determine whether vision signal is stablized, if unstable,
The image that laser television is shown can be the image of entanglement, do so the image that can prevent display entanglement.Terminating to timing
After being periodically detected of information errors, it may be determined that Rx modules are normal, at this point, control Tx modules exit reset state.
Optionally, after control Tx modules exit reset state, Tx modules can also further be detected, phase
The processing answered can be：According to the semaphore lock state of preset cycle detection transmitting terminal；Judge the semaphore lock shape of transmitting terminal
Whether the continuous P period is normal for state, if so, terminating the detection to the semaphore lock state of transmitting terminal, if it is not, then controlling hair
Sending end carries out reset operation, and continues to detect the semaphore lock state of transmitting terminal；Wherein, P is preset positive integer.
Specifically, above-mentioned flow can also include the processing of step a7-a9：
Whether step a7 occurs Tx losing locks according to preset cycle detection FPGA.
Step a8 terminates the periodicity inspection to Tx losing locks if Tx losing locks are not detected within the continuous P period
It surveys.
Step a9 carries out reset operation, and again according to pre- to the Tx modules of FPGA again if detecting Tx losing locks
If cycle detection described in FPGA Tx losing locks whether occur.
Wherein, P is preset positive integer.The numerical value of above-mentioned N, M, P can be arbitrarily arranged according to actual demand, and numerical value can be with
It is identical to can also be different.
Optionally, in the processing procedure of above-mentioned a0-a9, if the operation that reset is repeated can not also solve to repair event
Barrier, then can carry out following handle：If occurred in detecting FPGA in the preset duration after video signal transmission failure, begin
Do not occur the case where " continuously N number of period is normal for the semaphore lock state of receiving terminal " eventually, or does not occur " timing information always
The continuous N period is correct " the case where, or do not occur " the semaphore lock state continuous P period of transmitting terminal is normal " always
The case where, then send out preset alarm signal.
If there is the above situation, illustrating to reset repeatedly also can not solve to repair failure, then can be determined that problem not
It is happened on FPGA, at this moment can send out alarm signal, such as alarm sound, alarm light.It, can be with after user has found alarm signal
Restart laser television.
Situation two
Optionally, after carrying out reset operation to transmitting terminal, it can also be handled as follows and ensure that FPGA enters stable shape
State：According to the semaphore lock state of transmitting terminal described in preset cycle detection；Judge whether the semaphore lock state of transmitting terminal connects
The continuous P period is normal, if so, terminating the detection to the semaphore lock state of transmitting terminal, if it is not, then controlling transmitting terminal progress
Operation is resetted, and continues to detect the semaphore lock state of transmitting terminal；Wherein, P is preset positive integer.
Specifically, after the Tx modules to FPGA carry out reset operation (step b0), following steps b1- can also be carried out
The processing of b3：
Whether step b1 occurs Tx losing locks according to preset cycle detection FPGA.
Step b2 carries out reset operation to the Tx modules of FPGA again if detecting Tx losing locks.
Step b3 terminates the periodicity inspection to Tx losing locks if Tx losing locks are not detected within the continuous P period
It surveys；Wherein, P is preset positive integer.
It optionally,, can be with if restarting repeatedly can not also solve to repair failure in the processing procedure of above-mentioned b0-b3
Carry out following processing：If occurred in detecting FPGA in the preset duration after video signal transmission failure, do not occur always
The case where " the semaphore lock state continuous P period of transmitting terminal is normal ", then send out preset alarm signal.
If there is the above situation, illustrating to restart repeatedly also can not solve to repair failure, then can be determined that problem not
It is happened on FPGA, at this moment can send out alarm signal, such as alarm sound, alarm light.It, can be with after user has found alarm signal
Restart laser television.
It is above-mentioned after determining fault restoration, master controller can delete the letter of the fault type recorded in register
Breath.
In the embodiment of the present invention, when detect the semaphore lock state of receiving terminal is abnormal, receiving terminal to vision signal into
When the semaphore lock state of timing information generation mistake or transmitting terminal that row parsing obtains is abnormal, fault-signal is exported.
Processing in this way can prevent laser television from persistently protecting after transmission fault occurs in laser television and leads to display mistake
Hold the state of display mistake.
Based on the same technical idea, the embodiment of the present invention additionally provides FPGA detections vision signal in a kind of laser television
The device of transmission fault, the receiving terminal and transmitting terminal of FPGA form the transmission link of vision signal, as shown in figure 4, the device packet
It includes：
Detection module 410, for when detecting that the semaphore lock state of the receiving terminal is abnormal, the receiving terminal is to institute
The semaphore lock state for stating timing information generation mistake or the transmitting terminal that vision signal is parsed is abnormal
When, export fault-signal.
Optionally, the detection module 410, is additionally operable to：
Semaphore lock state in the receiving terminal of the FPGA is normal, detects the receiving terminal of the FPGA to institute
Whether correct state the timing information that vision signal is parsed；
It is correct in the timing information, whether just to detect the semaphore lock state of the transmitting terminal of the FPGA
Often.
Optionally, the detection module 410, is used for：
When detecting that the locking signal of the receiving terminal becomes high level, and to reach first default for the duration of high level
When duration, determine that the semaphore lock state of the receiving terminal is abnormal.
Optionally, the detection module 410, is used for：
The timing information includes at least one of following sub-information：Hactive, Htotal, Vactive and
Vtotal；
According to predetermined period, detect in timing information under each corresponding current value of sub-information and current display mode
The continuous mismatch number of a reference value, and when any continuous mismatch number reaches predetermined threshold value, determine the timing letters
Mistake occurs for breath.
Optionally, the detection module 410, is used for：
When detecting that the locking signal of the transmitting terminal becomes high level, and to reach second default for the duration of high level
When duration, determine that the semaphore lock state of the transmitting terminal is abnormal.
In the embodiment of the present invention, when detect the semaphore lock state of receiving terminal is abnormal, receiving terminal to vision signal into
When the semaphore lock state of timing information generation mistake or transmitting terminal that row parsing obtains is abnormal, fault-signal is exported.
Processing in this way can prevent laser television from persistently protecting after transmission fault occurs in laser television and leads to display mistake
Hold the state of display mistake.
It should be noted that：The device of FPGA detections video signal transmission failure in the laser television that above-described embodiment provides
It, only the example of the division of the above functional modules, can be in practical application when detecting video signal transmission failure
It is completed as needed and by above-mentioned function distribution by different function modules, i.e., the internal structure of device is divided into different work(
Energy module, to complete all or part of the functions described above.In addition, FPGA is examined in the laser television that above-described embodiment provides
The embodiment of the method for FPGA detections video signal transmission failure belongs in the device of survey video signal transmission failure and laser television
Same design, specific implementation process refer to embodiment of the method, and which is not described herein again.
One of ordinary skill in the art will appreciate that realizing that all or part of step of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can be stored in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (4)
1. a kind of method that FPGA detects video signal transmission failure in laser television, which is characterized in that the reception of the FPGA
End and transmitting terminal form the transmission link of vision signal,
Starting up is completed in the laser television or completes different types of vision signal switching, and vision signal enters stabilization
After state, following step is executed：
When detecting that the semaphore lock state of the receiving terminal is abnormal, the receiving terminal to the vision signal parse
When the semaphore lock state of the timing information generation mistake or the transmitting terminal that arrive is abnormal, fault-signal is exported；
Wherein, normal in the semaphore lock state of the receiving terminal of the FPGA, detect the receiving terminal pair of the FPGA
Whether the timing information that the vision signal is parsed is correct；It is correct in the timing information, inspection
Whether the semaphore lock state for surveying the transmitting terminal of the FPGA is normal；
The vision signal is VBO signals.
2. according to the method described in claim 1, it is characterized in that, the semaphore lock state for detecting the receiving terminal not
Normally, including：
When detecting that the locking signal of the receiving terminal becomes high level, and the duration of high level reaches the first preset duration
When, determine that the semaphore lock state of the receiving terminal is abnormal.
3. according to the method described in claim 1, it is characterized in that, it is described detect the receiving terminal to the vision signal into
Mistake occurs for the timing information that row parsing obtains, including：
The timing information includes at least one of following sub-information：Hactive, Htotal, Vactive and Vtotal；
According to predetermined period, each corresponding current value of sub-information and the benchmark under current display mode in timing information are detected
The continuous mismatch number of value, and when any continuous mismatch number reaches predetermined threshold value, determine the timing information hair
Raw mistake.
4. according to the method described in claim 1, it is characterized in that, the semaphore lock state for detecting the transmitting terminal not
Normally, including：
When detecting that the locking signal of the transmitting terminal becomes high level, and the duration of high level reaches the second preset duration
When, determine that the semaphore lock state of the transmitting terminal is abnormal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810709521.2A CN108600748A (en) | 2017-02-24 | 2017-02-24 | The method that FPGA detects video signal transmission failure in laser television |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810709521.2A CN108600748A (en) | 2017-02-24 | 2017-02-24 | The method that FPGA detects video signal transmission failure in laser television |
| CN201710103358.0A CN106851262B (en) | 2017-02-24 | 2017-02-24 | The method and apparatus that FPGA detects video signal transmission failure in laser television |
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| CN201710103358.0A Division CN106851262B (en) | 2017-02-24 | 2017-02-24 | The method and apparatus that FPGA detects video signal transmission failure in laser television |
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| CN201710103358.0A Active CN106851262B (en) | 2017-02-24 | 2017-02-24 | The method and apparatus that FPGA detects video signal transmission failure in laser television |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110021253A (en) * | 2019-04-24 | 2019-07-16 | 晶晨半导体(上海)股份有限公司 | The V-by-One signal control method and system of display device |
| CN110139096A (en) * | 2019-04-17 | 2019-08-16 | 深圳康佳电子科技有限公司 | TV automated testing method, storage medium, TV and external detection equipment |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726668B (en) * | 2020-06-05 | 2022-05-27 | 青岛信芯微电子科技股份有限公司 | FPGA, double-screen television, startup display method, equipment and medium |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN106851262B (en) | 2019-02-15 |
| CN106851262A (en) | 2017-06-13 |
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Address after: 266000, No. 218, Bay Road, Qingdao economic and Technological Development Zone, Shandong Applicant after: Hisense Video Technology Co., Ltd Address before: 266555 No. 151, Zhuzhou Road, Laoshan District, Shandong, Qingdao Applicant before: HISENSE ELECTRIC Co.,Ltd. |
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Application publication date: 20180928 |