WO2024094191A1

WO2024094191A1 - Display data processing method and apparatus, electronic device, and storage medium

Info

Publication number: WO2024094191A1
Application number: PCT/CN2023/129717
Authority: WO
Inventors: 付建林
Original assignee: 展讯通信（上海）有限公司
Priority date: 2022-11-04
Filing date: 2023-11-03
Publication date: 2024-05-10
Also published as: CN115691391A

Abstract

A display data processing method and apparatus, an electronic device, and a storage medium, capable of correcting display timing of a plurality of data packets in display data, thereby ensuring the correctness of displayed pictures in a display screen. The display data processing method comprises: acquiring display data (101); parsing a plurality of data packets in the display data into display pixel interface (DPI) signals (102); and if the timing of the DPI signals is consistent with preset timing (103), sending the display data (104).

Description

Display data processing method, device, electronic device and storage medium

This application claims priority to the Chinese patent application filed with the China Patent Office on November 4, 2022, with application number CN202211377172.1 and invention name “A display data processing method, device, electronic device and storage medium”, all contents of which are incorporated by reference in this application.

Technical Field

The embodiments of the present application relate to the field of display technology, and in particular, to a display data processing method, device, electronic device and storage medium.

Background technique

At present, with the development of display technology, display devices can realize various complex display requirements and are widely used in various fields, such as automotive smart cockpits, financial cash registers, and commercial displays, bringing convenience to people's lives.

However, in the prior art, when display data is transmitted through a display link between a system on a chip (SOC) and a display device, the display timing of multiple data packets in the display data is easily affected by external environmental interference, such as a wide temperature range, high humidity, high dust and electrical electromagnetic interference, which can easily lead to display abnormalities due to interference.

Summary of the invention

The embodiments of the present application provide a display data processing method, device, electronic device and storage medium, which can correct the display timing of display data in a display link, thereby improving display anomalies caused by interference in the display link.

In a first aspect, an embodiment of the present application provides a display data processing method, the method comprising:

Get display data;

Parsing multiple data packets in the display data into display pixel interface DPI signals;

If the timing of the DPI signal is consistent with the preset timing, sending the display data;

If the timing of the DPI signal is inconsistent with the preset timing, the multiple data packets are corrected so that the timing of the DPI signal obtained by parsing the corrected multiple data packets is consistent with the preset timing, and display data including the corrected multiple data packets is sent.

In the embodiment of the present application, since a data packet decoder is provided in the display link, multiple data packets in the display data received by the display link can be parsed into a display pixel interface DPI signal, and the DPI signal can show the timing of the multiple data packets. Based on the preset timing, if it is determined that the timing of the DPI signal is consistent with the preset timing, indicating that the timing of the multiple data packets in the above display data is correct, then the multiple data packets in the display data are sent based on the display link. If it is determined that the timing of the DPI signal is inconsistent with the preset timing, indicating that the timing of the multiple data packets in the above display data is wrong, the multiple data packets are corrected, so that the corrected multiple data packets are decoded. The timing of the DPI signal obtained by analysis is consistent with the preset timing, and then the display data including the corrected multiple data packets are sent to ensure that the display screen can display the correct picture based on the multiple data packets with correct timing.

So that the display screen can show the correct picture based on multiple data packets with correct timing.

Optionally, the display data is display serial interface DSI data.

In the embodiment of the present application, the display data in the acquired display data is DSI data.

Optionally, the display data includes a control timing data packet and a display data packet, and the multiple data packets are the control timing data packets in the display data.

In an embodiment of the present application, the display data includes a control timing data packet and a display data packet, wherein the control timing data packet is used to implement display control or transmission control, and the display data packet is used to implement the display of the picture, wherein the control timing data packet is susceptible to change due to external interference, therefore, only the control timing data packet in the display data can be parsed and corrected, and there is no need to parse the display data packet, so multiple data packets in the display data are control timing data packets to improve data processing and transmission speeds.

Optionally, the control timing data packet includes a horizontal back porch HBP data packet, a horizontal front porch HFP data packet, a horizontal synchronization valid HSA data packet, a vertical back porch VBP data packet, a vertical front porch VFP data packet and a vertical synchronization broadband VSA data packet.

In the embodiment of the present application, the control timing data packet includes a horizontal back shoulder HBP data packet, a horizontal front shoulder HFP data packet, a horizontal synchronization valid HSA data packet, a vertical back shoulder VBP data packet, a vertical front shoulder VFP data packet and a vertical synchronization broadband VSA data packet, wherein the horizontal back shoulder HBP data packet, the horizontal front shoulder HFP data packet and the horizontal synchronization valid HSA data packet represent the line cycle, the vertical back shoulder VBP data packet, the vertical front shoulder VFP data packet and the vertical synchronization broadband VSA data packet represent the field cycle, and parsing multiple data packets in the display data into the display pixel interface DPI signal is to parse the above-mentioned various control timing data packets into DPI signals.

Optionally, the DPI signal includes a vertical synchronization VSYNC signal and a horizontal synchronization HSYNC signal.

In an embodiment of the present application, the DPI signal includes a vertical synchronization VSYNC signal and a horizontal synchronization HSYNC signal, wherein the vertical synchronization VSYNC signal represents the DPI signal corresponding to each frame of the picture, and the horizontal synchronization HSYNC signal represents the DPI signal corresponding to a line in each frame of the picture. Based on the comparison of the timing of the vertical synchronization VSYNC signal and the horizontal synchronization HSYNC signal with the preset timing, it is possible to determine whether the timing of multiple data packets is correct, that is, if the timing of the vertical synchronization VSYNC signal and the horizontal synchronization HSYNC signal is consistent with the preset timing, it is determined that the timing of the multiple data packets is correct; if the timing of the vertical synchronization VSYNC signal or the horizontal synchronization HSYNC signal is inconsistent with the preset timing, it is determined that the timing of the multiple data packets is incorrect.

Optionally, the DPI signal includes an invalid display signal in the display data signal.

In an embodiment of the present application, the display data signal includes a valid display signal and an invalid display signal, wherein the valid display signal can be used to characterize the grayscale value of the display pixel to realize the display function, and the invalid display signal originally has no practical effect. In an embodiment of the present application, the DPI signal also includes an invalid display signal in the display data signal, and the invalid display signal that originally has no practical effect can be multiplexed to identify the data packet in the display data, so that the timing of the DPI signal can be determined based on the invalid display signal. Whether it is consistent with the preset timing.

Optionally, the display data includes display data in n display links, n＞1;

The parsing of the plurality of data packets in the display data into display pixel interface DPI signals comprises:

Sequentially parsing multiple data packets in the display data into display pixel interfaces based on the n display links DPI signal.

In an embodiment of the present application, when the display link is n links connected in series, where n is an integer greater than 1, the display data includes the display data in the n display links. When there is only one display link between the system on chip SOC and the display device, multiple data packets in the display data are parsed into display pixel interface DPI signals. When there are n display links between the system on chip SOC and the display device, each display link is provided with a data packet decoder, and multiple data packets in the display data are parsed into display pixel interface DPI signals in turn based on the n display links, that is, the data packet decoder in each display link will parse the multiple data packets in the received display data to obtain the display pixel interface DPI signal, and determine whether the timing of the DPI signal is consistent with the preset timing. If they are consistent, multiple data packets are sent to the next display link based on the display link. If they are inconsistent, multiple data packets are corrected and then sent to the next display link, so that the display screen can display the correct picture based on the multiple data packets finally received.

In a second aspect, an embodiment of the present application provides a display data processing device, the device comprising:

An acquisition unit, used for acquiring display data;

A parsing unit, used for parsing a plurality of data packets in the display data into display pixel interface DPI signals;

A sending unit, configured to send the display data if the timing of the DPI signal is consistent with a preset timing;

A correction unit is used to correct the multiple data packets if the timing of the DPI signal is inconsistent with the preset timing, so that the timing of the DPI signal obtained by parsing the corrected multiple data packets is consistent with the preset timing, and send display data including the corrected multiple data packets.

Optionally, the display data is display serial interface DSI data.

Optionally, the control timing data packet includes: a horizontal back shoulder HBP data packet, a horizontal front shoulder HFP data packet, a horizontal synchronization valid HSA data packet, a vertical back shoulder VBP data packet, a vertical front shoulder VFP data packet and a vertical synchronization broadband VSA data packet.

Optionally, the display data includes display data in n display links, n＞1;

The parsing unit is used for:

Based on the n display links, multiple data packets in the display data are parsed into display pixel interface DPI signals in sequence.

In a third aspect, an embodiment of the present application provides an electronic device, comprising at least one processor and a memory connected to the at least one processor, wherein the at least one processor is used to implement the steps of the method as described in any one of the first aspects when executing a computer program stored in the memory.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method as described in any one of the first aspects.

It should be understood that the second to fourth aspects of the embodiments of the present invention are consistent with the technical solutions of the first aspect of the embodiments of the present invention, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be described in detail.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

FIG2 is a flow chart of a display data processing method provided in an embodiment of the present application;

FIG3 is a schematic diagram of DSI data provided in an embodiment of the present application;

FIG4 is a schematic diagram of a DPI signal provided in an embodiment of the present application;

FIG5 is a schematic diagram of a data packet decoder provided in an embodiment of the present application parsing a DSI data packet;

FIG6 is a schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

FIG7 is a schematic diagram of a display scheme provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of a display data processing device provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of the structure of another electronic device provided in an embodiment of the present application.

Detailed ways

In order to better understand the technical solution of this specification, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be clear that the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit this specification. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

With the development of display technology, display solutions have become more and more complex, so that the display system can meet various display requirements, and users have higher requirements for the display effects on the display screen. Among them, the timing of data packets transmitted in the display link is the key to ensuring the display effect of the picture displayed on the display screen.

The inventors of the present application have discovered through research that, during data packet transmission, the display timing of the data packets is susceptible to external interference, resulting in errors in the display timing of the transmitted data packets. As a result, the display screen will display the screen based on the data packets with incorrect timing, with misaligned lines or missing screens, thus affecting the display effect.

In view of this, an embodiment of the present application provides a display data processing method, which can be applied to an electronic device as shown in FIG1 . The electronic device may include a system on chip (SOC) and a display device. Considering that when the display device is far away from the system on chip SOC, the display screen requires the system on chip SOC to transmit the display data to the display device over a long distance and at high speed. Therefore, there is a display link between the system on chip SOC and the display device, that is, the SOC is connected to the display device through the display link communication. The SOC can send the display data to the display device through the display link. A display data processing device may be provided in the display link, and the display data processing may specifically be a display link chip. The SOC may also be other devices capable of generating a display device, and the display The data processing device may be provided with a packet decoder (packet protocol structure decoder), which has the ability to parse packets. The display device may be a plurality of display interfaces and display screens corresponding to the plurality of display interfaces, such as the mobile industry processor-serial display interface MIPI-DSI, the low voltage differential signal interface LVDS, the embedded display port EDP, the high-definition multimedia interface HDMI, and the display screens corresponding to the four interfaces.

The technical solution provided by the embodiment of the present application is introduced below in conjunction with the accompanying drawings. Referring to FIG2 , an embodiment of the present invention provides a display data processing method, which can be applied to the above-mentioned display data processing device. The method flow is described as follows:

Step 101, obtaining display data;

For example, display data generated and sent by the SOC is received, and the display data is, for example, display serial interface (DSI) data. As shown in FIG3, a structure of DSI data is used as an example for specific description, and FIG3 illustrates the timing between data packets in the DSI data. Among them, the vertical sync start (Vertical Sync Start, VSS) data packet represents a frame of data field synchronization, the horizontal sync start (Horizontal Sync Start, HSS) data packet represents the start of line synchronization, and the horizontal sync end (Horizontal Sync End, HSE) data packet represents the end of line synchronization. The line cycle displayed by the horizontal sync active (Horizontal Sync Active, HSA) data packet, the horizontal back porch (Horizontal Back Porch, HBP) data packet and the horizontal front porch (Horizontal Front Porch, HFP) data packet is filled with blank data packets, and its length (including data packet overhead) is calculated to match the cycle specified by the peripheral data. The field period displayed by the vertical sync active (VSA) data packet, the vertical back porch (VBP) data packet and the vertical front porch (VFP) data packet is filled with blank lines composed of HSS data packets, HSA data packets, HSE data packets, blanking or low power interval (BLLP) data packets and blank data packets, and the effective display data is transmitted by the active lines per frame (VACT) data. Therefore, for the entire display link, the correct parsing of the DSI synchronization cycle packet, timing (HBP, HFP, HSA, VBP, VFP, VSA), and display data by each link is the fundamental to ensure normal display.

Step 102, parse multiple data packets in the display data into display pixel interface (DPI) signals.

The multiple data packets in step 102 are at least part of the data packets in the display data. As shown in FIG4 , the DPI signal corresponds to the data packets in the display data, and the data in the display data is in the form of encapsulated data packets. In step 102, the multiple data packets are parsed into DPI signals, and the DPI signals have specific signal waveforms.

Step 103, determining whether the timing of the DPI signal is consistent with the preset timing, if yes, that is, if the timing of the DPI signal is consistent with the preset timing, executing step 104, sending the display data to the display device, if no, that is, if the timing of the DPI signal is inconsistent with the preset timing, executing step 105;

Step 105 , correcting the multiple data packets so that the timing of the DPI signal obtained by parsing the corrected multiple data packets is consistent with the preset timing, and executing step 106 , sending the display data including the corrected multiple data packets to the display device.

Specifically, as shown in FIG. 3 and FIG. 4, the timing of multiple data packets in the correct display data is fixed. Therefore, after the correct multiple data packets are parsed into DPI signals, the timing of the corresponding signals is also fixed. The fixed DPI signal timing is the preset timing. If the current display data is not disturbed and the data is changed, If the sequence of the packets is different, then the timing of the DPI signal after parsing should be consistent with the preset timing. Therefore, if it is determined in step 103 that the timing of the DPI signal is consistent with the preset timing, it means that the display data is not interfered with and is correct display data, so the correct display data can be sent to the display device. If the current display data is interfered with by the outside world and the sequence of the data packets is abnormal, then the timing of the DPI signal after parsing will change, that is, it is inconsistent with the preset timing, which means that the display data is abnormal. Therefore, step 105 is executed to correct the display data, and then the corrected display data is sent to the display device so that the display device can display normally.

The display data processing method in the embodiment of the present application parses multiple data packets in the display data into DPI signals, and then determines whether the display data is abnormal based on the timing of the DPI signal. If abnormal, the display data is corrected, that is, the display timing of the display data in the display link can be corrected, thereby improving the display abnormality caused by interference in the display link.

In some embodiments, the display data includes a control timing data packet and a display data packet, and the plurality of data packets are the control timing data packets in the display data.

Specifically, the control timing data packet is used to implement display control or transmission control, and the display data packet is used to implement the display of the picture. The control timing data packet is easily changed by external interference, so only the control timing data packet in the display data can be parsed and corrected, without parsing the display data packet, so as to improve the data processing and transmission speed.

In some embodiments, the control timing data packets include horizontal back shoulder HBP data packets, horizontal front shoulder HFP data packets, horizontal synchronization active HSA data packets, vertical back shoulder VBP data packets, vertical front shoulder VFP data packets and vertical synchronization wideband VSA data packets, wherein the horizontal back shoulder HBP data packets, horizontal front shoulder HFP data packets and horizontal synchronization valid HSA data packets represent line cycles, the vertical back shoulder VBP data packets, vertical front shoulder VFP data packets and vertical synchronization active VSA data packets represent field cycles, and parsing the control timing data packets in the display data into DPI signals means parsing the above-mentioned various control timing data packets into DPI signals.

In some embodiments, the DPI signal includes a vertical synchronization VSYNC signal and a horizontal synchronization HSYNC signal, wherein the vertical synchronization VSYNC signal represents the DPI signal corresponding to each frame of the picture, and the horizontal synchronization HSYNC signal represents the DPI signal corresponding to a line in each frame of the picture, and parsing the control timing data packet in the display data into the DPI signal is to parse the control timing data packet into a vertical synchronization VSYNC signal and a horizontal synchronization HSYNC signal.

Specifically, for example, in FIG. 4 , in each frame, the signal corresponding to the display area is located between the signal corresponding to VBP and the signal corresponding to VFP; in each row, the signal corresponding to the display data area is located between the signal corresponding to HBP and HFP. The VSYNC signal includes a portion corresponding to VBP and a portion corresponding to VFP, and the HSYNC signal includes a portion corresponding to HBP and a portion corresponding to HFP. For correct display data, in each frame, the high and low level timings of the signal corresponding to the control timing, such as the portion of the VSYNC signal located outside the display area, are fixed and the same; in each row, the high and low level timings of the signal corresponding to the control timing, such as the portion of the HSYNC signal located outside the display data area, are fixed and the same. Therefore, it is possible to determine whether the timing of the DPI signal is consistent with the preset timing based on the above signal. In addition, corresponding to abnormal display data, according to the high and low level timings in the DPI signal, the data packet corresponding to a certain section of the DPI signal can be specifically determined, and based on the preset timing, it is possible to determine what kind of order disorder has occurred in the data packet, so that the order of the data packets in the display data can be adjusted to achieve the correction of the data packet.

In some embodiments, the DPI signal includes an invalid display signal in the display data signal.

Specifically, for example, in Figure 4, DB is a display data signal, wherein 0, 1, 2, 3, ..., n are valid display signals, and the parts other than 0 to n are invalid display signals. The valid display signal can be used to characterize the grayscale value of the display pixel and realize the display function. The invalid display signal originally has no practical effect. In an embodiment of the present application, the invalid display signal that originally has no practical effect can be multiplexed to identify the data packets in the display data, so that it is possible to determine whether the timing of the DPI signal is consistent with the preset timing based on the invalid display signal, that is, to determine whether the order of multiple data packets in the display data is abnormal, and when the order of multiple data packets is abnormal, the order of the data packets in the display data can be corrected according to the identification of the invalid display signal.

In some embodiments, as shown in FIG. 5 , a packet decoder in a display link may parse multiple packets in the DSI data into a VSYNC signal, an HSYNC signal, a DB signal, and a data enable (DE) signal.

In some embodiments, referring to FIG. 6 , the display link may be n links connected in series, where n is an integer greater than 1, and the display data includes the display data in the n display links. To ensure that the display screen can display the correct picture based on the multiple data packets finally received, the timing of the multiple data packets sent from the entire display link to the display device must be correct.

As a possible implementation, when there are n display links between the system on chip SOC and the display device, a data packet decoder can be provided in each display link, and multiple data packets in the display data are sequentially parsed into DPI signals based on the n display links, that is, the data packet decoder in each display link will parse the multiple data packets in the received display data to obtain the DPI signal, and determine whether the timing of the DPI signal is consistent with the preset timing. If they are consistent, multiple data packets are sent to the next display link based on the display link. If they are inconsistent, the multiple data packets are corrected and then sent to the next display link, so that the display screen can display the correct picture based on the multiple data packets finally received.

For example, when display link 1 receives multiple data packets in display data, the data packet decoder in display link 1 will parse the multiple data packets in the display data to obtain a DPI signal, and determine whether the timing of the DPI signal is consistent with the preset timing. If they are consistent, the multiple data packets are sent to display link 2 based on the display link. If they are inconsistent, the multiple data packets are corrected and then sent to display link 2, until the data packet decoder in display link n parses the multiple data packets in the display data to obtain a DPI signal, and determines whether the timing of the DPI signal is consistent with the preset timing. If they are consistent, the multiple data packets are sent to the display device based on the display link. If they are inconsistent, the multiple data packets are corrected and then sent to the display device.

Please refer to Figure 7, which is a display solution provided in an embodiment of the present application. The display solution can be used in a vehicle-mounted intelligent cockpit. The DSI data sent by the application processor AP (application process) is converted into two DSI outputs, namely DSI1 and DSI2, through a field programmable gate array (FPGA). Each DSI is then connected to a serialization chip Serializer for data processing, and then connected to a deserialization chip Deserializer through an FPD Link III interface for data processing. Four LVDS signals are separated through four LVDS interfaces to drive four vehicle-mounted screens Lvds panel1, Lvds panel2, Lvds panel3 and Lvds panel4, which correspond to the central control entertainment information display, co-pilot display, instrument information display and head-up information display, respectively. The FPGA corresponds to display link 1, the serializer corresponds to display link 2, and the deserializer corresponds to display link 3. The three display links in series transmit DSI data. In combination with the embodiment of the present application, multiple data packets in the display data are sequentially parsed into DPI signals based on the three display links to determine the timing of the DPI signal. Check whether the timing is consistent with the preset timing.

Please refer to FIG. 8 , which is a display data processing device provided in an embodiment of the present application. The device includes: an acquisition unit 201 , a parsing unit 202 , a sending unit 203 and a correction unit 204 .

An acquisition unit 201 is used to acquire display data;

A parsing unit 202, configured to parse a plurality of data packets in the display data into display pixel interface DPI signals;

The sending unit 203 is used to send the display data if the timing of the DPI signal is consistent with the preset timing;

The correction unit 204 is used to correct the multiple data packets if the timing of the DPI signal is inconsistent with the preset timing, so that the timing of the DPI signal obtained by parsing the corrected multiple data packets is consistent with the preset timing, and send display data including the corrected multiple data packets.

Optionally, the display data is display serial interface DSI data.

Optionally, the control timing data packets include: horizontal back shoulder HBP data packets, horizontal front shoulder HFP data packets, horizontal synchronization valid HSA data packets, vertical back shoulder VBP data packets, vertical front shoulder VFP data packets and vertical synchronization broadband VSA data packets.

Optionally, the display data includes display data in n display links, n＞1;

The parsing unit 202 is used for:

Based on n display links, multiple data packets in the display data are parsed into display pixel interface DPI signals in sequence.

Please refer to Figure 9. Based on the same inventive concept, an embodiment of the present application also provides an electronic device, which may include at least one processor 301. The at least one processor 301 is used to execute a computer program stored in a memory to implement the steps of the display data processing method shown in Figure 2 provided in an embodiment of the present application.

Optionally, the processor 301 may specifically be a central processing unit, a specific ASIC, or one or more integrated circuits for controlling program execution.

Optionally, the electronic device may further include a memory 302 connected to at least one processor 301, and the memory 302 may include a ROM, a RAM, and a disk memory. The memory 302 is used to store data required by the processor 301 when it is running, that is, it stores instructions that can be executed by at least one processor 301, and at least one processor 301 executes the method shown in Figure 1 by executing the instructions stored in the memory 302. Among them, the number of memories 302 is one or more. Among them, the memory 302 is shown together in Figure 9, but it should be noted that the memory 302 is not a required functional module, so it is shown in dotted lines in Figure 9.

Among them, the acquisition unit 201, the parsing unit 202, the sending unit 203 and the correction unit 204 and the corresponding physical devices can all be the aforementioned processor 301. The electronic device can be used to execute the method provided by the embodiment shown in Figure 2. Therefore, for the functions that can be implemented by each functional module in the electronic device, reference can be made to the corresponding description in the embodiment shown in Figure 2, and no further details are given.

An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer executes the method as shown in FIG. 2 .

The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this book shall be included in the scope of protection of this manual.

Claims

A display data processing method, characterized by comprising:

Get display data;

Parsing multiple data packets in the display data into display pixel interface DPI signals;

If the timing of the DPI signal is consistent with the preset timing, sending the display data;

If the timing of the DPI signal is inconsistent with the preset timing, the multiple data packets are corrected so that the timing of the DPI signal obtained by parsing the corrected multiple data packets is consistent with the preset timing, and display data including the corrected multiple data packets is sent.
The method according to claim 1, characterized in that

The display data is display serial interface DSI data.
The method according to claim 1, characterized in that

The display data includes a control timing data packet and a display data packet, and the multiple data packets are the control timing data packets in the display data.
The method according to claim 3, characterized in that

The control timing data packets include: horizontal back porch HBP data packets, horizontal front porch HFP data packets, horizontal synchronization activity HSA data packets, vertical back porch VBP data packets, vertical front porch VFP data packets and vertical synchronization activity VSA data packets.
The method according to claim 4, characterized in that

The DPI signal includes a vertical synchronization VSYNC signal and a horizontal synchronization HSYNC signal.
The method according to claim 4, characterized in that

The DPI signal includes an invalid display signal in the display data signal.
The method according to any one of claims 2 to 6, characterized in that

The display data includes display data in n display links, n>1;

The parsing of the plurality of data packets in the display data into display pixel interface DPI signals comprises:

Based on the n display links, multiple data packets in the display data are parsed into display pixel interface DPI signals in sequence.
A display data processing device, characterized in that the device comprises:

An acquisition unit, used for acquiring display data;

A parsing unit, used for parsing a plurality of data packets in the display data into display pixel interface DPI signals;

A sending unit, configured to send the display data if the timing of the DPI signal is consistent with a preset timing;

A correction unit is used to correct the multiple data packets if the timing of the DPI signal is inconsistent with the preset timing, so that the timing of the DPI signal obtained by parsing the corrected multiple data packets is consistent with the preset timing, and send display data including the corrected multiple data packets.
An electronic device, characterized in that the electronic device comprises at least one processor and a memory connected to the at least one processor, and the at least one processor is used to implement the steps of the method as described in any one of claims 1 to 7 when executing a computer program stored in the memory.
A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.