CN215453109U

CN215453109U - Car machine display device and car

Info

Publication number: CN215453109U
Application number: CN202122191630.XU
Authority: CN
Inventors: 姜鸿雷; 陈志谦; 程果; 宋潇辉; 李响; 向青宝
Original assignee: Hubei Ecarx Technology Co Ltd
Current assignee: Ecarx Hubei Tech Co Ltd
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2022-01-07
Anticipated expiration: 2031-09-10

Abstract

The embodiment of the utility model provides a vehicle-mounted display device and a vehicle, relates to the technical field of vehicle-mounted devices, and can realize multi-screen display on the vehicle-mounted display device. In the vehicle-mounted display equipment, the SOC is used for sending any frame of RGB image in the video data to the FPGA through the DPI interface. The FPGA is used for dividing the received RGB image into a first image and a second image, converting first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data through the first LVDS interface. And converting the second RGB data corresponding to the second image into second LVDS data, and sending the second LVDS data through a second LVDS interface. The first display is used for displaying a first image according to the first LVDS data. The second display is used for displaying a second image according to the second LVDS data.

Description

Car machine display device and car

Technical Field

The utility model relates to the technical field of vehicle machines, in particular to a vehicle machine display device and a vehicle.

Background

With the development of the intelligent cabin technology, more and more applications are integrated in a vehicle-mounted machine system of a vehicle, so that the vehicle-mounted machine system can provide functions of multimedia data playing, driving assistance, vehicle positioning, call making and the like for a user.

At present, the display equipment of the vehicle machine is generally only provided with one display screen for displaying various application interfaces. At present, the vehicle display equipment cannot be configured with a plurality of display screens, and the plurality of display screens are arranged to respectively display different pictures, namely, multi-screen display on the vehicle display equipment cannot be carried out.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model aims to provide a vehicle-mounted display device and a vehicle, so as to realize multi-screen display on the vehicle-mounted display device. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present invention provides a vehicle display device, including: the system level chip SOC, the field programmable gate device FPGA, the first display and the second display;

the SOC is connected with the FPGA through a DPI interface and is used for sending any frame of RGB image in video data to the FPGA through the DPI interface;

the FPGA is used for receiving the RGB image through a DPI interface, dividing the RGB image into a first image and a second image, converting first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data through a first LVDS interface; converting second RGB data corresponding to the second image into second LVDS data, and sending the second LVDS data through a second LVDS interface;

the first display is connected with the FPGA through a first LVDS interface and used for receiving the first LVDS data through the first LVDS interface and displaying the first image according to the first LVDS data;

the second display is connected with the FPGA through a second LVDS interface and used for receiving the second LVDS data through the second LVDS interface and displaying the second image according to the second LVDS data.

In a second aspect, an embodiment of the present invention provides a vehicle, including the in-vehicle display device according to the first aspect.

According to the vehicle-mounted display equipment and the vehicle provided by the embodiment of the utility model, the FPGA can receive the RGB image sent by the SOC through the DPI interface, and the RGB image is divided into the first image and the second image. Moreover, the FPGA can respectively convert the RGB data corresponding to the two images into LVDS data and respectively send the LVDS data to the two displays, so that the two displays respectively display the first image and the second image. Therefore, data received from one input interface of the FPGA are distributed to different displays for displaying, namely, multi-screen display on the vehicle display equipment is realized.

Of course, it is not necessary for any product in which the utility model is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by referring to these drawings.

Fig. 1 is a schematic structural diagram of a vehicle display device according to an embodiment of the present invention;

FIG. 2 is an exemplary diagram of an RGB image provided by an embodiment of the utility model;

fig. 3 is a schematic structural diagram of another vehicle-mounted display device according to an embodiment of the present invention;

fig. 4 is an exemplary diagram of a JEIDA format according to an embodiment of the present invention;

fig. 5 is an exemplary diagram of a VESA format according to an embodiment of the present invention;

FIG. 6 is an exemplary diagram of a timing diagram of a VESA signal according to an embodiment of the utility model;

fig. 7 is a schematic structural diagram of another car display device according to an embodiment of the present invention.

Fig. 8 is an exemplary schematic diagram of a video timing chart according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived from the embodiments given herein by one of ordinary skill in the art, are within the scope of the utility model.

In order to perform multi-screen display on the in-vehicle display device, referring to fig. 1, an embodiment of the present invention provides an in-vehicle display device, including: a System On Chip (SOC) 101, a Field Programmable Gate Array (FPGA) 102, a first display 103, and a second display 104.

The SOC 101 is connected to the FPGA 102 through a Display Pixel Interface (DPI) and is configured to send any frame of RGB image in the video data to the FPGA 102 through the DPI Interface. Wherein, RGB represents three color channels of Red (Red, R), Green (Green, G) and Blue (Blue, B). The RGB images in the video data may be sent to the FPGA 102 in sequence according to the playing order.

The FPGA 102 is configured to receive the RGB image through the DPI interface, divide the RGB image into a first image and a second image, convert first RGB data corresponding to the first image into first LVDS data, send the first LVDS data through the first LVDS interface, convert second RGB data corresponding to the second image into second LVDS data, and send the second LVDS data through the second LVDS interface.

The first display 103 is connected to the FPGA 102 through the first LVDS interface, and is configured to receive the first LVDS data through the first LVDS interface and display a first image according to the first LVDS data.

The second display 104 is connected to the FPGA 102 through a second LVDS interface, and is configured to receive second LVDS data through the second LVDS interface and display a second image according to the second LVDS data.

In the embodiment of the present invention, the first image and the second image may be image frames in different video data processed in the SOC 101, and the SOC 101 splices two image frames in the different video data to form one RGB image.

In the vehicle-mounted display device provided by the embodiment of the utility model, the FPGA can receive the RGB image sent by the SOC through the DPI interface and divide the RGB image into the first image and the second image. Moreover, the FPGA can respectively convert the RGB data corresponding to the two images into LVDS data and respectively send the LVDS data to the two displays, so that the two displays respectively display the first image and the second image. Therefore, data received from one input interface of the FPGA are distributed to different displays for displaying, namely, multi-screen display on the vehicle display equipment is realized.

It should be noted that "first" and "second" in the embodiments of the present invention are used only for distinguishing and are not used to limit modules or data. For example, "first" and "second" of the first LVDS interface and the second LVDS interface are used only to distinguish the two LVDS interfaces. The first LVDS interface and the second LVDS interface may be the same LVDS interface or different LVDS interfaces, and this is not specifically limited in the embodiment of the present invention. For example, the LVDS interface includes two types, whose data signal formats are a VESA standard conforming to Video Electronics Standards Association (VESA) and a JEIDA standard conforming to Japanese Electronics Industry Development Association (JEIDA), respectively.

In the embodiment of the present invention, SOC 101 is further configured to: before any RGB image in the video data is sent to the FPGA 102 through the DPI interface, a first video and a second video are obtained, and then each frame of first image of the first video is respectively spliced with each frame of second image of the second video at the corresponding moment, so that an initial RGB image is obtained. And then converting the RGB data of the initial RGB image according to the specified RGB format to obtain the RGB image. Wherein, the bit occupied by each pixel point in the RGB data of the designated RGB format is more than the bit occupied by each pixel point in the RGB data of the initial RGB format.

During stitching, the SOC 101 may stitch each first image and each second image in a one-to-one correspondence according to the playing order of the video frames.

For example, as shown in fig. 2, the resolution of the first image is 1920 × 720, which means that the length of the first image is 1920 pixels, and the width of the first image is 720 pixels. The resolution of the second image is 800 × 480, which means that the length of the second image is 800 pixels and the width of the second image is 480 pixels. The resolution of the RGB image obtained by stitching the first image and the second image is (1920+800) × 720 ═ 2720 × 720.

For example, the initial RGB format of the RGB data may be an RGB555 format, and in the RGB555 format, each pixel point is represented by 16 bits (bit) or 2 bytes (byte) or 1 word (word), that is, each pixel point occupies 16 bits. In the RGB data of a pixel point, three color channels are respectively represented by 5 bits, the highest bit is empty, and the RGB data of an RGB555 format of the pixel point are arranged from the high bit to the low bit as follows:

X R0 R1 R2 R3 R4 G0 G1 G2 G3 G4 B0 B1 B2 B3 B4

wherein, X represents null, R0-R4 represent the color value of the red channel of the pixel, G0-G4 represent the color value of the green channel of the pixel, and B0-B4 represent the color value of the blue channel of the pixel.

For another example, the initial RGB format of the RGB data may be an RGB24 format, and in the RGB24 format, each pixel point is represented by 24 bits to 3 bytes, that is, each pixel point occupies 24 bits. In the RGB data of one pixel, three color channels are represented by 8 bits, respectively, and the RGB data of the RGB24 format of one pixel is arranged from high order to low order as follows:

R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7

R0-R7 represent the color value of the red channel of the pixel, G0-G7 represent the color value of the green channel of the pixel, and B0-B7 represent the color value of the blue channel of the pixel.

For example, the specified RGB format may be an RGB888 format, and in the RGB888 format, each pixel point is represented by 24 bits, that is, each pixel point occupies 24 bits, and a color value of each color channel is represented by 8 bits.

In the embodiment of the present invention, the SOC 101 may employ a quantization compensation method when converting the RGB data of the RGB image from the initial RGB format to the specified RGB format.

Based on this, SOC 101 is specifically configured to: the RGB data of the initial RGB format is padded to the upper bits of the specified RGB format. After filling, if each bit of the specified RGB format is not completely filled, filling with the low bit of the RGB data of the initial RGB format. If the low bit of the RGB data in the initial RGB format is used for filling, and the bit of the designated RGB format is not completely filled, the RGB data is used for carrying out cyclic compensation.

For example, RGB data in RGB555 format is "X R0R 1R 2R 3R 4G 0G 1G 2G 3G 4B 0B 1B 2B 3B 4", and the RGB555 format is converted into RGB888 format to obtain "{ R0R 1R 2R 3R 4R 2R 3R 4} { G0G 1G 2G 3G 4G 2G 3G 4} { B0B 1B 2B 3B 4B 2B 3B 4 }".

For example, RGB data in RGB332 format is "R2R 1R 0G 2G 1G 0B 1B 0", and the RGB data is converted from RGB332 format to RGB888 format, resulting in "{ R2R 1R 0R 2R 1R 0R 2R 1} { G2G 1G 0G 2G 1G 0G 2G 1} { B1B 0B 1B 0B 1B 0B 1B 0 }".

In the embodiment of the utility model, the RGB data is converted into the uniform specified format for transmission, so that the data transmission efficiency can be improved.

In an embodiment of the utility model, the DPI interface comprises: a DPI Data channel, a Clock (CLK) channel, a column sync channel, a row sync channel, and a Data Enable (DE) channel. The CLK channel is used for transmitting a DPI clock signal, the DPI clock signal is used for determining at what time to transmit data, and the transmission sequence of the group of RGB data corresponding to each pixel point is ensured, so that the accuracy of data transmission is improved; the column synchronization channel is used for transmitting column synchronization signals, and the column synchronization signals are used for counting to obtain the column numbers of the currently transmitted pixel points in the image, namely the pixel columns of the currently transmitted RGB image; the line synchronization channel is used for transmitting line synchronization signals, the line synchronization signals are used for counting and obtaining the line number of a currently transmitted pixel point in an image, namely the pixel line of the currently transmitted RGB image, and the position of the currently transmitted pixel point is determined according to the obtained line number (pixel line) and column number (pixel column); the data enable channel is used for transmitting a data enable signal and is used for controlling signal transmission and closing transmission.

In the embodiment of the present invention, the DPI data channels include channels D0 to D11, and when the SOC 101 sends any frame of RGB image in the video data to the FPGA 102 through the DPI interface, a clock double-edge sampling mode is adopted, and the RGB data transmitted by the channels D0 to D11 respectively corresponding to the rising edge and the falling edge of the clock signal are as shown in table one.

Watch 1

DPI data channel	Rising edge	Falling edge
			D0	G4	B0
D1	G5	B1
			D2	G6	B2
D3	G7	B3
			D4	R0	B4
D5	R1	B5
			D6	R2	B6
D7	R3	B7
			D8	R4	G0
D9	R5	G1
			D10	R6	G2
D11	R7	G3

In the embodiment of the present invention, a pixel is represented by a set of RGB data, for example, the RGB555 format RGB data of a pixel is arranged from high order to low order as follows:

X R0 R1 R2 R3 R4 G0 G1 G2 G3 G4 B0 B1 B2 B3 B4

each channel of the DPI interface of the SOC 101 corresponds to each channel of the DPI interface of the FPGA 102 one by one, and is used to send each bit of a group of RGB data. For example, in table one, when the clock signal transmitted by the SOC 101 is at a rising edge, the D0 channel transmits G4 data, and correspondingly, when the clock signal received by the FPGA 102 is at a rising edge, the D0 channel receives G4 data.

In the embodiment of the present invention, as shown in fig. 3, the FPGA 102 includes: a DPI interface, a receiving unit 1021, a first register (buffer)1022, and a second register 1023.

The receiving unit 1021 is connected to the SOC 101 through a DPI interface, and is configured to: receiving the RGB image sent by the SOC 101 through a DPI interface, and determining first RGB data of a first image and second RGB data of a second image from the RGB image;

the receiving unit 1021 is connected to the first register 1022, and stores the first RGB data corresponding to the first image into the first register 1022;

the receiving unit 1021 is further coupled to the second register 1023, and stores the second RGB data corresponding to the second image into the second register 1023.

Wherein, a pixel point is represented by a group of RGB data; and the first RGB data of the first image is used for representing the set of RGB data of all pixel points forming the first image, and the second RGB data of the second image is used for representing the set of RGB data of all pixel points forming the second image. Therefore, in the embodiment of the present invention, the first RGB data includes a plurality of sets of RGB data, and each set of RGB data in the first RGB data is used to represent a pixel point in the first image; the second RGB data includes a plurality of sets of RGB data, and each set of RGB data in the second RGB data is used to represent a pixel point in the second image. For example, taking the format of RGB data as RGB888 as an example, each set of RGB data includes 24 bits, and the 24 bits represent color values of three channels of one pixel.

Optionally, the first register 1022 and the second register 1023 may be different registers or the same register. When the first register 1022 and the second register 1023 are the same register, the buffer unit of the first RGB image in the register is different from the buffer unit of the second RGB image in the register.

As shown in fig. 3, FPGA 102 has a first conversion unit 1024 and a second conversion unit 1025.

The first conversion unit 1024 is connected to the first register 1022, and is configured to read the first RGB data from the first register 1022;

the first conversion unit 1024 is further connected to the first display 103 via a first LVDS interface, and is further configured to send the first RGB data to the first display 103 via the first LVDS interface according to the first LVDS format.

The second converting unit 1025 is connected to the second register 1023 for reading the second RGB data from the second register 1023;

the second conversion unit 1025 is further connected to the second display 104 via a second LVDS interface, and is further configured to send the second RGB data to the second display 104 via the second LVDS interface according to a second LVDS format.

In the embodiment of the utility model, the FPGA can store the RGB data of different images into different memories, so that the ordering of data storage is improved, the RGB data of different images can be read from different cache units when the RGB data are converted into LVDS data, and the efficiency of data conversion is improved.

In the embodiment of the present invention, the DPI interface of the FPGA 102 includes a column synchronization channel and a row synchronization channel.

Based on this, the receiving unit 1021 is connected with the column synchronization channel, and is specifically configured to receive a signal of the column synchronization channel, and determine a pixel column of the currently transmitted RGB image according to the signal of the column synchronization channel;

the receiving unit 1021 is connected to the line synchronization channel, and is specifically configured to receive a signal of the line synchronization channel, and determine a pixel line of the currently transmitted RGB image according to the signal of the line synchronization channel.

Because the pixel row of the pixel point represents the line number of the pixel point in the RGB image, the pixel column represents the column number of the pixel point in the RGB image. The first specified range is the range of the first image in the RGB image, and the second specified range is the range of the second image in the RGB image. Therefore, for each pixel point of the RGB image, if the number of rows and the number of columns of the pixel point belong to the first designated range, it is determined that the pixel point belongs to the first image, and a group of RGB data corresponding to the pixel point is determined as the first RGB data. And if the number of the lines and the number of the columns of the pixel point belong to a second specified range, determining that the pixel point belongs to a second image, and determining a group of RGB data corresponding to the pixel point as second RGB data.

For example, as shown in fig. 2, the first designated range is 1920 × 720, that is, RGB data corresponding to pixel points whose pixel rows do not exceed 1920 and pixel columns do not exceed 720 is taken as the first RGB data. The second specified range is [1921,2720 ]. times.480, that is, RGB data corresponding to a pixel point whose pixel row belongs to [1921,2720] and whose pixel column does not exceed 480 is taken as second RGB data.

In the embodiment of the utility model, the FPGA can determine the image to which each pixel point belongs according to the position of the pixel point in the RGB image, so that the RGB image is split into the first image and the second image, and the first image and the second image can be displayed in different displays in a follow-up manner.

In the embodiment of the utility model, the DPI interface further comprises a DPI clock channel and a DPI data channel.

Based on this, the receiving unit 1021 is connected with the DPI clock channel, and is specifically used for receiving the clock signal through the DPI clock channel;

the receiving unit 1021 is connected to the DPI data channel, and is specifically configured to receive the set of RGB data corresponding to the currently transmitted pixel point sent by the SOC 101 through the DPI data channel in one clock cycle of the clock signal.

In one clock cycle of the DPI clock channel, the DPI data channel transmits a group of RGB data, and meanwhile, according to pixel rows and pixel columns of pixel points corresponding to the group of RGB data, whether the group of RGB data is first RGB data or second RGB data can be determined and stored in a register corresponding to the image to which the group of RGB data belongs.

In the embodiment of the present invention, the first LVDS interface may be a VESA interface or a JEIDA interface, the second LVDS interface may be a VESA interface or a JEIDA interface, similarly, both the first LVDS format and the second LVDS format may be VESA format or JEIDA format, and the first LVDS format and the second LVDS format may be the same or different.

The LVDS interface includes an LVDS clock Channel (CLK) and 4 LVDS data channels (TxOUT 0-TxOUT 3). The LVDS clock channel is used for transmitting clock signals. Each LVDS data channel transmits a serial signal through a pair (i.e., two) of differential data lines, and each LVDS data channel transmits 7 bits of data in one clock cycle.

As shown in fig. 4, fig. 4 shows data in JEIDA format corresponding to one pixel point transmitted through the JEIDA interface, a broken line below CLK in fig. 4 represents a clock signal transmitted by the LVDS clock channel in one signal period, and data corresponding to TxOUT0 to TxOUT3 respectively represent data transmitted by the LVDS data channel in one clock period.

As shown in fig. 5, fig. 5 shows data in VESA format corresponding to one pixel point transmitted through the VESA interface, a broken line below CLK in fig. 5 represents a clock signal transmitted by the LVDS clock channel in one signal period, and data corresponding to TxOUT0 to TxOUT3 respectively represent data transmitted by the LVDS data channel in one clock period.

In the embodiment of the present invention, DE in fig. 4 and 5 denotes data enable. VS denotes Vertical Synchronization (Vsync), i.e., a column Synchronization signal, HS denotes row Synchronization (Hsync), i.e., a row Synchronization signal, and XX denotes null.

For example, fig. 6 is a timing diagram of signals transmitted through the VESA interface. R _0[ i ] (n) represents Ri data in RGB data in the RGB888 format for the nth pixel, and so on, i ═ 0,1,2, …, 7. G _0[ i ] (n) represents Gi data in RGB data in the nth pixel RGB888 format, and so on, i ═ 0,1,2, …, 7. B _0[ i ] (n) represents Bi data in the RGB data in the format of the nth pixel RGB888, and so on, i is 0,1,2, …, 7.

The embodiment of the utility model can display different image data in different displays, and the resolution of the image data displayed by the different displays can be different, thereby realizing the multi-screen display of pictures with different resolutions. Alternatively, the resolutions of the first image and the second image may be the same or different, and this is not particularly limited in the embodiment of the present invention.

In the embodiment of the present invention, the FPGA 102 and the first display 103 and the FPGA 102 and the second display 104 may also be connected by a serial chip and a deserializing chip.

Specifically, as shown in fig. 7, the first LVDS interface of the in-vehicle display device according to the embodiment of the present invention includes a first serial chip (Serializer)105 and a first Deserializer chip (Deserializer) 106.

The first serial chip 105 is connected to the first converting unit 1024, and is configured to receive the first LVDS data sent by the first converting unit 1024, convert the first LVDS data into first serial data, and send the first serial data to the first deserializing chip 106;

the first deserializing chip 106 is connected to the first serial chip 105, and is configured to receive first serial data sent by the first serial chip 105 and restore the first serial data into first LVDS data;

the first deserializing chip 106 is connected to the first display 103, and is configured to send the restored first LVDS data to the first display 103.

Correspondingly, the second LVDS interface of the on-board display device has a second serial chip 107 and a second deserializing chip 108;

the second serial chip 107 is connected to the second conversion unit 1025, and is configured to receive the second LVDS data sent by the second conversion unit 1025, convert the first LVDS data into second serial data, and send the second serial data to the second deserializing chip 108;

the second deserializing chip 108 is connected to the second serial chip 107, and is configured to receive second serial data sent by the second serial chip 107 and restore the second serial data into second LVDS data;

the second deserializing chip 108 is connected to the second display 104, and is configured to send the restored second LVDS data to the second display 104.

In the embodiment of the present invention, the first serial chip 105 and the first deserializing chip 106 may be connected by an in-vehicle cable, and the second serial chip 107 and the second deserializing chip 108 may be connected by an in-vehicle cable, which may be a differential twisted pair. By adding the serial chip and the deserializing chip between the FPGA and the display, the transmission distance of LVDS data can be increased, and the limitation of the position of the display on multi-screen display is reduced.

In the case that the image transmitted in the embodiment of the present invention is a video frame image, the display plays a video based on the received video frame image, as shown in fig. 8, and fig. 8 is a synchronization timing chart of the video provided in the embodiment of the present invention.

In fig. 8, the first line shows a VSYNC (Vertical synchronization signal, Vertical synchronization signal field synchronization) signal. The second line of broken lines represents a Horizontal synchronization signal (HSYNC) signal, and the VSYNC signal and the HSYNC signal are used to indicate the positions of the pixels indicated by the transmitted LVDS data in the image. The third row of broken lines represents ENABLE, which is used to control the input and output of signals. The fourth broken line represents a DCK (Data Clock) signal.

Wherein 1frame represents the transmission of one frame of image. When a frame of image is transmitted, it includes VBP (Vertical Back port), VACT (Vertical Active area), and VFP (Vertical Front port). Where VBP represents the number of inactive lines at the beginning of the image frame after the vertical synchronization period. The VBP includes VLW (Vertical Low Pulse width) and VBP. VLW represents the time to display a row of pixel points. VACT represents the image frame height. The VFP indicates the number of invalid lines from the end of outputting the image frame of the present transmission to the start of the next frame vertical synchronization period.

"Zoom in" in fig. 8 indicates that the polygonal lines of the HSYNC signal, the ENABLE signal, and the DCK signal are amplified each for the same period of time, and the amplified polygonal lines are shown below "Zoom in".

1H (1Line time) represents the Line time of the HSYNC signal, and 1H includes HBP (Horizontal Back Port), HACT (Horizontal Active), and HFP (Horizontal Front Port). Where HBP denotes the number of pixel clock cycles to be inserted when the pixel data of each row or each column starts to be output, HACT denotes the image frame width, and HFP denotes the number of pixel clock cycles between the end of the pixel data of each row or each column and the row clock output pulse. The HBP includes HLW (Horizontal Low Pulse width) which represents a pixel clock period and HBP. The HBP period corresponds to DTST (Data Transfer Start Time) at the ENABLE signal. DB represents the transmitted pixel data, and vaid data represents valid data. Optionally, the pixel data is LVDS data of a pixel point.

The functional characteristics of the embodiments of the present invention are explained below:

in the embodiment of the present invention, for the RGB data input by the DPI interface of the FPGA 102, the clock frequency may be 120 megahertz (Mega Hertz, Mhz), and the resolution of the image corresponding to the RGB data may be 2720 × 720@60 Hz. Where 60 is the refresh rate of the display.

For the LVDS data output by the LVDS interface of the FPGA 102, the clock frequency may be 100Mhz, and the resolution of the image corresponding to the LVDS data may include 1920 × 720@60Hz and 800 × 480@60Hz, that is, video in two different video formats is supported to be output simultaneously.

In the embodiment of the present invention, signal names, data to be transmitted, corresponding FPGA pin positions, and Input/Output (IO) standards transmitted by each channel (i.e., pin) of the DPI interface are shown in table two.

Watch two

Where rst _ n represents a reset (reset) signal, which is active at a low level. The SOC 101 is further configured to send a reset signal to the FPGA 102 through the rst _ n channel to control the FPGA to reset.

Optionally, the FPGA 102 may also be connected to the SOC 101 through a status pin, and the FPGA 102 is further configured to send the status of the FPGA 102 to the SOC through the status pin.

Referring to table three, the first LVDS interface pin and the second LVDS interface pin are described below with an example of a resolution of 1920 × 720 for the first image data and a resolution of 800 × 480 for the second image data.

Watch III

The embodiment of the utility model provides a vehicle which comprises any one vehicle display device.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. Particularly, for the vehicle embodiment, since it is basically similar to the car display device embodiment, the description is relatively simple, and relevant points can be referred to the partial description of the car display device embodiment.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. The utility model provides a car machine display device which characterized in that includes: the system level chip SOC, the field programmable gate device FPGA, the first display and the second display;

2. The in-vehicle display device of claim 1, wherein the FPGA has a DPI interface, a receiving unit, a first register and a second register,

the receiving unit is connected with the SOC through a DPI interface and used for receiving the RGB images sent by the SOC through the DPI interface and determining first RGB data of a first image and second RGB data of a second image from the RGB images;

the receiving unit is connected with the first register and used for storing first RGB data corresponding to the first image into the first register;

the receiving unit is further connected to the second register, and is configured to store the second RGB data corresponding to the second image in the second register.

3. The on-board display device of claim 2, wherein the FPGA has a first conversion unit and a second conversion unit;

the first conversion unit is connected with the first register and used for reading first RGB data from the first register;

the first conversion unit is also connected with the first display through a first LVDS interface and is also used for sending the first RGB data to the first display through the first LVDS interface according to a first LVDS format;

the second conversion unit is connected with the second register and used for reading second RGB data from the second register;

the second conversion unit is further connected with the second display through a second LVDS interface, and is further configured to send the second RGB data to the second display through the second LVDS interface according to a second LVDS format.

4. The vehicle-mounted display device according to claim 2, wherein the DPI interface of the FPGA comprises a column synchronization channel and a row synchronization channel;

the receiving unit is connected with the column synchronization channel, and is specifically used for receiving the signal of the column synchronization channel and determining the pixel column of the currently transmitted RGB image according to the signal of the column synchronization channel;

the receiving unit is connected with the line synchronization channel, and is specifically configured to receive a signal of the line synchronization channel, and determine a pixel line of the currently transmitted RGB image according to the signal of the line synchronization channel.

5. The in-vehicle display device of claim 4, wherein the DPI interface of the FPGA further comprises a DPI clock channel and a DPI data channel,

the receiving unit is connected with the DPI clock channel and is specifically used for receiving a clock signal through the DPI clock channel;

the receiving unit is connected with the DPI data channel and is specifically used for receiving the group of RGB data corresponding to the currently transmitted pixel point sent by the SOC through the DPI data channel in one clock cycle of a clock signal.

6. The in-vehicle display device according to claim 3, wherein the first LVDS interface of the in-vehicle display device has a first serial chip and a first deserializing chip;

the first serial chip is connected with the first conversion unit and used for receiving the first LVDS data sent by the first conversion unit, converting the first LVDS data into first serial data and sending the first serial data to the first deserializing chip;

the first deserializing chip is connected with the first serial chip and used for receiving first serial data sent by the first serial chip and restoring the first serial data into first LVDS data;

the first deserializing chip is connected with the first display and used for sending the restored first LVDS data to the first display.

7. The in-vehicle display device according to claim 3, wherein the second LVDS interface of the in-vehicle display device has a second serial chip and a second deserializing chip;

the second serial chip is connected with the second conversion unit and used for receiving the second LVDS data sent by the second conversion unit, converting the first LVDS data into second serial data and sending the second serial data to the second deserializing chip;

the second deserializing chip is connected with the second serial chip and used for receiving second serial data sent by the second serial chip and restoring the second serial data into second LVDS data;

the second deserializing chip is connected with the second display and used for sending the restored second LVDS data to the second display.

8. The on-board display device according to any one of claims 1 to 7, wherein the first LVDS interface is a VESA interface or a JEIDA interface; the second LVDS interface is a VESA interface or a JEIDA interface.

9. A vehicle characterized by comprising the in-vehicle display device according to any one of claims 1 to 8.