CN111726668B

CN111726668B - FPGA, double-screen television, startup display method, equipment and medium

Info

Publication number: CN111726668B
Application number: CN202010503844.3A
Authority: CN
Inventors: 夏建龙; 王伟; 徐卫
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2020-06-05
Filing date: 2020-06-05
Publication date: 2022-05-27
Anticipated expiration: 2040-06-05
Also published as: CN111726668A

Abstract

The invention discloses an FPGA, a double-screen television, a startup display method, equipment and a medium, wherein a VBO-RX module in the FPGA is used for sending a first signal to an MCU (microprogrammed control unit) when not receiving a stable image signal; the graphic card generating module is used for receiving a starting command sent by the MCU after receiving the first signal and generating a LOGO image to be displayed on the lower panel according to the graphic card information of the pre-stored LOGO image; the output end TX module is used for receiving a LOGO image to be displayed on a lower panel and sending the LOGO image to the lower panel for display. According to the invention, when the VBO-RX module does not receive a stable image signal, the MCU controls the graphics card generating module to start, and the LOGO image is generated according to the pre-stored graphics card information, so that time buffering can be provided for stable connection of the image signal and the VBO-RX module, and the problem of black screen or screen splash during startup display is avoided.

Description

FPGA, double-screen television, startup display method, equipment and medium

Technical Field

The invention relates to the technical field of stacked screen televisions, in particular to an FPGA (field programmable gate array), a dual-screen television, a startup display method, equipment and a medium.

Background

The existing television can not meet the requirements of users on the definition and the color reproduction of image display more and more, and a screen-folding television is provided for meeting the requirements of the users.

The screen folding refers to a screen folding display scheme adopting an upper panel and a lower panel, wherein the upper panel is a color screen, and the color screen is used for focusing on the fine control of colors, so that the attention on the reduction colors can be realized; the lower panel is a black and white screen that focuses on fine dimming, which can present high contrast and dark field details. In the prior art, a top panel is controlled by a Timing Controller (TCON), and a bottom panel is controlled by a Field Programmable Gate Array (FPGA).

After the FPGA finishes loading the netlist file, the MCU configures parameters for a screen folding algorithm processing module and a VBO-RX module in the FPGA, the VBO-RX module of the FPGA is reset after the parameter configuration is finished, the reset VBO-RX module receives an image signal, after the image signal is stably connected with the VBO-RX module, the VBO-RX module analyzes the image signal into a stable Timing signal and sends the stable Timing signal to the screen folding algorithm processing module, the Timing signal is processed by the screen folding algorithm processing module to increase transmittance information and then is sent to an output end TX module in the FPGA, and the output end TX module sends the image signal to a lower panel. And after the lower panel receives the stable image signal, displaying an image.

In the prior art, because an image signal is unstable, when the image signal is not connected with a VBO-RX module for a long time, a LOGO image to be displayed on a lower panel cannot be generated, and the LOGO image cannot be displayed even if the lower panel is electrified, so that the problem of black screen during starting is caused; when the connection established between the image signal and the VBO-RX module is unstable, the connection is interrupted and reconnected irregularly, so that the lower panel image cannot be generated stably, and the problem of screen splash during startup is caused.

Disclosure of Invention

The embodiment of the invention provides an FPGA (field programmable gate array), a dual-screen television, a startup display method, equipment and a medium, which are used for solving the problems of black screen and screen splash generated when a stacked-screen television is started due to instability of an image signal in the conventional VBO (visual basic input output) format.

The embodiment of the invention provides a programmable gate array (FPGA), which comprises an image card generating module, an output end TX module and a VBO-RX module;

the VBO-RX module is used for sending a first signal to the MCU when not receiving a stable image signal;

the graphic card generating module is used for receiving a starting command sent by the MCU after receiving the first signal, and generating a LOGO image to be displayed on the lower panel according to the graphic card information of the pre-stored LOGO image, wherein the graphic card information comprises light transmittance information;

and the output end TX module is used for receiving a LOGO image to be displayed on the lower panel and sending the LOGO image to the lower panel for display.

Further, the graphics card generation module comprises:

the acquisition submodule is used for acquiring the picture card information of a pre-stored LOGO image after receiving a starting command sent by the MCU and sending the picture card information to the time sequence control submodule;

the timing sequence generation submodule is used for generating a first timing sequence signal for controlling the display of the LOGO image according to the received clock signal sent by the MCU and sending the first timing sequence signal to the timing sequence control submodule;

and the time sequence control submodule is used for determining each first target time for displaying the LOGO image according to the received first time sequence signal, and sending the LOGO image to be displayed on the lower panel generated according to the graph card information to the output end TX module at each first target time.

Further, the graphics card generation module further comprises: an MCU _ REG sub-module;

the MCU _ REG submodule is used for receiving target identification information of a starting command received by the identification configured by the MCU;

and the obtaining submodule is used for determining that the starting command is received when the identification information of the MCU _ REG is monitored to be the target identification information of the received starting command.

Further, the VBO-RX module is further configured to control the VBO-RX module to reset when receiving a first control signal sent by the MCU, where the first control signal is sent after the MCU receives the first signal.

Further, the VBO-RX module is specifically configured to determine whether an image signal received by the VBO-RX module is locked, and if not, determine that a stable image signal is not received; if so, analyzing each image to be displayed corresponding to the second time sequence signal according to the image signal, judging whether the number of pixel points contained in each image to be displayed is within a preset numerical range, and if not, determining that a stable image signal is not received; and if so, determining that the stable image signal is received.

Further, the FPGA further includes: a screen folding algorithm processing module;

the screen folding algorithm processing module is configured to determine each second target time of a display image according to the second timing signal analyzed by the VBO-RX module and the image data of the image signal, and send the image data to the output terminal TX module at each second target time;

the output end TX module is further used for sending a second signal to the MCU after the LOGO image is displayed, and outputting the image data sent by the screen folding algorithm processing module;

the graphic card generating module is further configured to stop generating the LOGO image to be displayed on the lower panel when receiving a close command sent by the MCU, where the close command is sent by the MCU after receiving the second signal.

Further, the FPGA further includes: a storage module;

the storage module is used for storing the graphic card information of the LOGO image;

the image card generating module is used for acquiring the image card information from the storage module.

Correspondingly, the embodiment of the invention provides a dual-screen television, which further comprises: an MCU and a lower panel;

the FPGA is used for sending a first signal to the MCU when determining that a stable image signal is not received;

the MCU is used for generating a starting command and sending the starting command to the FPGA after receiving the first signal;

the FPGA is further used for generating a LOGO image to be displayed on a lower panel according to the picture card information of the pre-stored LOGO image after receiving the starting command, and sending the LOGO image to the lower panel, wherein the picture card information comprises light transmittance information;

and the lower panel is used for receiving and displaying the LOGO image.

Further, the FPGA is specifically configured to send a second signal to the MCU after the LOGO image is displayed and when it is determined that a stable image signal is received;

the MCU is further used for generating a closing command for controlling the FPGA to stop generating the LOGO image after receiving the second signal, and sending the closing command to the FPGA;

the FPGA is specifically used for stopping generating the LOGO image after receiving the closing command, generating a main interface image and sending the main interface image to the lower panel;

and the lower panel is also used for receiving and displaying the main interface image.

Correspondingly, an embodiment of the present invention provides a power-on display method, which is applied to any one of the FPGAs described above, and the method includes:

if the stable image signal is determined not to be received, sending a first signal to the MCU;

receiving a starting command sent by the MCU after receiving the first signal, and generating a LOGO image to be displayed on a lower panel according to the picture card information of the pre-stored LOGO image;

and sending the LOGO image to a lower panel for display.

Further, the step of generating a LOGO image to be displayed on a lower panel according to the pre-stored graphic card information of the LOGO image includes:

receiving a clock signal sent by the MCU, and generating a first time sequence signal for controlling the display of the LOGO image;

and determining each first target moment for displaying the LOGO image according to the first time sequence signal, and generating the LOGO image to be displayed at each first target moment.

Further, the sending the LOGO image to a lower panel for display comprises:

and at each first target moment, sending the LOGO image to be displayed to the lower panel for display.

Further, the method further comprises:

after the LOGO image is displayed and when a stable image signal is determined to be received, sending a second signal to the MCU;

receiving a closing command sent by the MCU, and stopping generating the LOGO image to be displayed on the lower panel;

and determining each second target time of the displayed image according to the analyzed second time sequence signal and the image data of the image signal, and sending the image data to the lower panel for displaying at each second target time.

Accordingly, an embodiment of the present invention provides an electronic device, where the electronic device includes a processor and a memory, where the memory is used to store a computer program, and the processor is used to implement the steps of any one of the above-mentioned power-on display methods when executing the computer program stored in the memory.

Accordingly, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of any one of the above boot-up display methods.

The embodiment of the invention provides an FPGA, a double-screen television, a startup display method, equipment and a medium, wherein the FPGA comprises a graphic card generating module, an output end TX module and a VBO-RX module; the VBO-RX module is used for sending a first signal to the MCU when not receiving a stable image signal; the graphic card generating module is used for receiving a starting command sent by the MCU after receiving the first signal and generating a LOGO image to be displayed on a lower panel according to the graphic card information of the pre-stored LOGO image, wherein the graphic card information comprises light transmittance information; and the output end TX module is used for receiving a LOGO image to be displayed on the lower panel and sending the LOGO image to the lower panel for display. In the embodiment of the invention, when the VBO-RX module does not receive a stable image signal, the MCU controls the graphics card generating module to start, the started graphics card generating module can generate a LOGO image according to pre-stored graphics card information, and the LOGO image is displayed on a lower panel through the output end TX module, so that time buffering can be provided for stable connection of the image signal and the VBO-RX module, and the problems of black screen during startup display caused by disconnection and screen splash during startup caused by unstable connection are avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of an FPGA according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a graphics card generating module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an FPGA according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a dual-screen television based on an FPGA according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a dual-screen television according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1:

fig. 1 is a schematic structural diagram of an FPGA according to an embodiment of the present invention, and as shown in fig. 1, the FPGA100 includes: the system comprises a graphic card generating module 101, an output end TX module 102 and a VBO-RX module 103;

the VBO-RX module 103 is configured to send a first signal to the MCU200 when not receiving a stable image signal;

the graphic card generating module 101 is configured to receive a start command sent by the MCU200 after receiving the first signal, and generate a LOGO image to be displayed on the lower panel according to graphic card information of the LOGO image stored in advance, where the graphic card information includes light transmittance information;

and the output end TX module 102 is used for receiving a LOGO image to be displayed on the lower panel and sending the LOGO image to the lower panel for display.

In an embodiment of the present invention, the FPGA100 includes a graphics card generating module 101, an output terminal TX module 102, and a VBO-RX module 103.

The VBO-RX module 103 is connected to an image signal input port of the FPGA100 for receiving an image signal. In the embodiment of the present invention, the image signal is a VBO format signal.

In the embodiment of the present invention, if the VBO-RX module receives a stable image signal, the VBO-RX module 103 analyzes the image signal to obtain a timing signal and image data of the image signal. When the VBO-RX module 103 determines that it does not receive a stable image signal, in order to avoid the problem of causing a blank screen or a screen splash to appear on the lower panel, in the embodiment of the present invention, the FPGA100 includes the graphics card generating module 101, and the graphics card generating module 101 may generate a LOGO image to be displayed according to pre-stored graphics card information.

In order to facilitate the MCU to determine whether to activate the graphics card generating module 101 in the FPGA100, in the embodiment of the present invention, the VBO-RX module 103 sends a first signal to the MCU200 when determining that it does not receive a stable image signal. Wherein the VBO-RX module 103 does not establish a stable connection with the image signal when determining that it does not receive a stable image signal.

After receiving the first signal, the MCU200 determines that the VBO-RX module 103 is not stably connected to the image signal, and the MCU200 sends a start command to the card generating module 101. Specifically, when the MCU200 monitors that the netlist file of the FPGA100 is loaded and receives the first signal sent by the VBO-RX module 103, the MCU200 sends a start command to the FPGA 100.

After the loading of the netlist file is completed, the pin FPGA _ done on the FPGA is pulled up, and when the MCU200 monitors that the pin FPGA _ done is pulled up, it is determined that the loading of the netlist file of the FPGA100 is completed.

After receiving the start command, the graphics card generation module 101 generates a LOGO image to be displayed on the lower panel according to the graphics card information of the LOGO image stored in advance. In order to accurately generate a LOGO image with light transmittance meeting requirements, in the embodiment of the present invention, the graphic card information includes: position information, shape information, luminance information, and light transmittance information of the LOGO image.

The pre-stored information of the graphic card in the embodiment of the present invention may be obtained by previously capturing a character representing the LOGO from the complete image, capturing the character representing the LOGO in a rectangular manner, processing the captured character representing the LOGO and the remaining image except the character into RGB data, and storing the processed RGB data and the determined position of the character rectangle representing the LOGO in the LOGO image.

The pre-stored card information may be stored in any storage space. For example, it may be stored in a memory space outside the FPGA or within the FPGA.

When the graphic card generation module 101 generates a LOGO image according to the pre-stored graphic card information, the graphic card generation module 101 generates a complete LOGO image according to the position of the character rectangle in the LOGO image and the RGB data.

The graphic card generating module 101 may determine a display position of the generated LOGO image according to the position information, for example, the LOGO image may be located at the upper left corner, the upper right corner, or the center of the lower panel.

The graphics card generating module 101 may determine the shape of the generated LOGO image according to the shape information of the LOGO image stored in advance, for example, the shape of the generated LOGO image may be a regular shape or an irregular shape such as a rectangle, a circle, or a parallelogram, and the embodiment of the present invention is not limited to this.

The graphic card generation module 101 determines the brightness of the generated LOGO image according to the brightness information of the LOGO image stored in advance. Specifically, the brightness information of the pre-stored LOGO image includes brightness information of each character in the LOGO image. The graphic card generating module 101 may determine the brightness of the corresponding character in the generated LOGO image according to the brightness information of each character in the LOGO image stored in advance. For example, the LOGO is Hisense, and the graphics card generating module determines the brightness of the character H in the generated LOGO image according to the brightness information of the stored character H.

The graphic card generation module 101 determines the light transmittance of the generated LOGO image according to the light transmittance information of the LOGO image stored in advance. Specifically, the light transmittance information of the pre-stored LOGO image includes light transmittance information of each character in the LOGO image. The graphic card generating module 101 may determine the light transmittance of the corresponding character in the generated LOGO image according to the light transmittance information of each character in the LOGO image, which is stored in advance. For example, the LOGO is Hisense, and the graphic card generating module determines the light transmittance of the character H in the generated LOGO image according to the saved light transmittance information of the character H.

In the embodiment of the present invention, the light transmittance information of the LOGO image is determined in advance according to the known information of the graphic card and is stored, and the method for determining the light transmittance information is a method in the prior art.

In this embodiment of the present invention, the FPGA100 further includes an output end TX module 102, where the output end TX module 102 receives a LOGO image to be displayed on a lower panel sent by the graphics card generating module 101, and based on the received LOGO image, the output end TX module 102 sends the LOGO image to the lower panel, so that the lower panel displays the LOGO image.

Specifically, the output end TX module 102 may control the lower panel to display the LOGO image by using a method in the prior art, and in the embodiment of the present invention, the LOGO image output by the output end TX module 102 is an image in RGB format.

In the embodiment of the invention, when the VBO-RX module does not receive a stable image signal, the MCU controls the graphics card generating module to start, the started graphics card generating module can generate a LOGO image according to pre-stored graphics card information, and the LOGO image is displayed on a lower panel through the output end TX module, so that time buffering can be provided for stable connection of the image signal and the VBO-RX module, and the problems of black screen during startup display caused by disconnection and screen splash during startup caused by unstable connection are avoided.

Example 2:

in order to display a LOGO image more accurately, on the basis of the above embodiment, in an embodiment of the present invention, the graphic card generating module 101 includes:

the obtaining sub-module 1011 is configured to obtain the card information of the pre-stored LOGO image after receiving the start command sent by the MCU200, and send the card information to the timing control sub-module 1013;

a timing generation sub-module 1012, configured to generate a first timing signal for controlling display of the LOGO image according to the received clock signal sent by the MCU, and send the first timing signal to the timing control sub-module 1013;

the timing control sub-module 1013 is configured to determine each target time at which the LOGO image is displayed according to the received first timing signal, and send the LOGO image to be displayed on the lower panel generated according to the graphic card information to the output end TX module 102 at each target time.

In the embodiment of the present invention, fig. 2 is a schematic structural diagram of a card generating module according to the embodiment of the present invention, as shown in fig. 2, the card generating module 101 includes an obtaining sub-module 1011, a timing generating sub-module 1012 and a timing control sub-module 1013, and the timing control sub-module 1013 is connected to the obtaining sub-module 1011 and the timing generating sub-module 1012 respectively.

The obtaining sub-module 1011 is configured to obtain the graphics card information of the prestored LOGO image after receiving the start command, where the start command is sent by the MCU200, the MCU200 sends the start command for starting the graphics card generating module to the FPGA100 after determining that the FPGA100 finishes loading the netlist file and receives the first signal sent by the VBO-RX module 103, and the obtaining sub-module 1011 of the graphics card generating module receives the start command.

After receiving the start command, the obtaining sub-module 1011 obtains the card information of the LOGO image stored in advance, and then sends the card information to the timing control sub-module 1013.

The timing generation sub-module 1012 is further configured to receive a clock signal sent by the MCU200, where the clock signal CLK is used to control a display time of a LOGO image to be displayed on the lower panel, so that the LOGO image on the upper panel and the LOGO image on the lower panel can be displayed at the same time. After the MCU200 sends a start command to the obtaining sub-module 1011, the MCU200 sends a clock signal to the timing generation sub-module 1012.

The timing generation sub-module 1012 generates a first timing signal for controlling display of the LOGO image, based on the received clock signal. The first timing signal includes a horizontal synchronization signal HS, a frame synchronization signal VS and a data valid signal DE. Specifically, the process of generating the timing signal according to the clock signal belongs to the prior art, and is not described herein again.

The graphics card generation module 100 also includes a clock signal CLK input port 120, through which clock signal CLK is received by the timing generation submodule 1012.

To determine each first target time at which the LOGO image is displayed, the timing generation sub-module 1012 generates the first timing signal and then sends the first timing signal to the timing control sub-module 1013.

After the timing control sub-module 1013 receives the first timing signal and the graphics card information, the timing control sub-module 1013 may determine each first target time for displaying the LOGO image according to the first timing signal, and the timing control sub-module 1013 may generate the LOGO image to be displayed on the lower panel according to the graphics card information.

In order to enable the lower panel and the upper panel to synchronously display the LOGO image, in the embodiment of the present invention, the timing control sub-module 1013 sends, to the output end TX module 102, the generated LOGO image to be displayed on the lower panel at each first target time.

In order to determine whether a start command is received, on the basis of the foregoing embodiments, in an embodiment of the present invention, the graphics card generating module 101 further includes: MCU _ REG sub-module 110;

the MCU _ REG sub-module 110 is configured to receive target identification information that an identification configured by the MCU200 receives a start command;

the obtaining sub-module 1011 is configured to determine that the start command is received when the identification information of the MCU _ REG110 is monitored as the target identification information.

In the graphics card generation module 101 shown in fig. 2, the graphics card generation module 101 further includes an MCU _ REG sub-module 110. The MCU200 may control the value of the identification information within the MCU _ REG sub-module 110 to identify whether a start command is transmitted. In the embodiment of the present invention, the MCU _ REG sub-module 110 is actually a register, the identification information of the register MCU _ REG110 may be 1 or 0, and when the obtaining sub-module 1011 monitors that the identification information of the register MCU _ REG110 is 1, the obtaining sub-module 1011 determines to receive the start command sent by the MCU 200.

Example 3:

in order to establish a stable connection between the VBO-RX module 103 and an image signal, on the basis of the foregoing embodiments, in an embodiment of the present invention, the VBO-RX module 103 is further configured to control the VBO-RX module 103 to reset when receiving a first control signal sent by the MCU200, where the first control signal is sent after the MCU receives the first signal.

In this embodiment of the present invention, the VBO-RX module 103 resets after receiving a first control signal sent by the MCU200, where the first control signal is generated after the MCU200 receives the first signal.

In the embodiment of the present invention, after the FPGA100 finishes loading the netlist file, the MCU200 configures parameters for the VBO-RX module 103 in the FPGA100, and after a reset, the VBO-RX module 103 starts to establish connection with the image signal.

In order to reset itself when the VBO-RX module 103 determines that it does not receive a stable image signal. In the embodiment of the present invention, since the VBO-RX module 103 is controlled by the MCU200 to reset, the VBO-RX module 103 controls the VBO-RX module 103 to reset when receiving the first control signal transmitted by the MCU 200.

After the VBO-RX module 103 is reset, the VBO-RX module 103 receives the image signal again, if the VBO-RX module 103 still does not receive the stable image signal, the VBO-RX module 103 still sends the first signal to the MCU200, and resets after receiving the first control signal sent by the MCU200, and so on, until the VBO-RX module 103 receives the stable image signal.

In the embodiment of the present invention, the VBO-RX module 103 receiving the stable image signal includes: the VBO-RX module 103 receives an image signal after the FPGA100 is started up, and the received image signal is stabilized.

In the embodiment of the present invention, in order to accurately determine whether the VBO-RX module 103 receives a stable image signal, on the basis of the foregoing embodiments, in the embodiment of the present invention, the VBO-RX module 103 is specifically configured to determine whether an image signal received by itself is locked, and if not, determine that the stable image signal is not received; if so, analyzing each image to be displayed corresponding to the second time sequence signal according to the image signal, judging whether the number of pixel points in each image to be displayed is within a preset numerical range, and if not, determining that a stable image signal is not received; and if so, determining that the stable image signal is received.

In the embodiment of the present invention, the VBO-RX module 103 receives the stable image signal, which means that the VBO-RX module 103 can analyze the stable time sequence signal according to the received stable image signal, and the number of the pixel points in each image to be displayed corresponding to the time sequence signal is within the preset value range.

Therefore, in order for the VBO-RX module 103 to determine whether it receives a stable image signal, the VBO-RX module 103 first determines whether the image signal received by itself is locked, and when the image signal is not locked, the VBO-RX module 103 determines that it does not receive a stable image signal.

The image signal received by the VBO-RX module 103 is locked, which means that the VBO-RX module 103 can stably receive the image signal.

When the video signal is locked, the VBO-RX module 103 analyzes each to-be-displayed video corresponding to the second timing signal according to the video signal, and determines whether the number of pixels in each to-be-displayed video is within a preset value range, and if not, the VBO-RX module 103 determines that it does not receive a stable video signal.

Wherein, the preset numerical range is set according to the requirement of the image. When the number of the pixel points in each to-be-displayed image is within the preset value range, the VBO-RX module 103 determines that it receives a stable image signal.

In the embodiment of the present invention, the image corresponding to the image signal received by the VBO-RX module 103 is an image in RGB format.

Example 4:

in order to realize that the lower panel is controlled to display the main interface image, on the basis of the foregoing embodiments, in an embodiment of the present invention, the FPGA100 further includes: a screen folding algorithm processing module 104;

the screen folding algorithm processing module 104 is configured to determine each second target time of a display image according to the second timing signal analyzed by the VBO-RX module 103 and the image data of the image signal, and send the image data to the output end TX module 102 at each second target time;

the output end TX module 102 is further configured to send a second signal to the MCU200 after the LOGO image is displayed, and output the image data sent by the screen folding algorithm processing module;

the graphic card generating module 101 is further configured to stop generating a LOGO image to be displayed on the lower panel when receiving a close command sent by the MCU200, where the close command is sent by the MCU after receiving the second signal.

In this embodiment of the present invention, fig. 3 is a schematic structural diagram of an FPGA according to this embodiment of the present invention, and as shown in fig. 3, the FPGA further includes a screen folding algorithm processing module 104. The folding screen algorithm processing module 104 is connected to the VBO-RX module 103 and the output terminal TX module 102, respectively.

The graphic card generating module 101 may generate a LOGO image, and in a time range of displaying the LOGO image on the lower panel, the VBO-RX module 103 may have sufficient time to establish a stable connection with the image signal, so that in the time period of displaying the LOGO image, the VBO-RX module 103 sends the analyzed second timing signal and the image data of the image signal to the screen folding algorithm processing module 104.

The folding algorithm processing module 104 determines each second target time of the display image according to the second timing signal, and sends the image data to the output terminal TX module 102 at each second target time. The image data is in an RGB format.

In this embodiment of the present invention, the screen folding algorithm processing module 104 determines the light transmittance information of the image data of the image signal according to the second timing signal and the image data of the image signal.

The method for determining the light transmittance information according to the image data by the screen folding algorithm processing module 104 belongs to the prior art, and is the same as the method for determining the light transmittance according to the image data in the known image card information by the image card information.

The folding algorithm processing module 104 sends the image data added with the light transmittance information to the output terminal TX module 102 at each second target timing.

After the LOGO image is displayed, in order to complete the switching to the main interface, the output end TX module 102 is further configured to send a second signal to the MCU200 after it is determined that the LOGO image is displayed.

After receiving the second signal, the MCU200 determines that the LOGO image display is complete, and sends a second control signal to the output terminal TX module 102. The output end TX module 102 is further configured to receive the second signal sent by the MCU200, and output the image data sent by the screen folding algorithm processing module 104.

Specifically, in the embodiment of the present invention, the output end TX module 102 is configured to output a LOGO image and a main interface image to be displayed on the lower panel.

After the LOGO image is displayed, the graphic card generating module 101 needs to stop generating the LOGO image, so in the embodiment of the present invention, after receiving the second signal, the MCU200 determines that the LOGO image is displayed, and the MCU200 sends a close command to the graphic card generating module 101.

The graphic card generating module 101 is further configured to stop generating a LOGO image to be displayed on the lower panel when receiving a close command sent by the MCU 200.

Specifically, in the embodiment of the present invention, in the schematic structural diagram of the image card generating module shown in fig. 2, the image card generating module 101 further includes a reset signal RST input port 130, through the reset signal input port 130, after receiving a shutdown command, the image card generating module 101 stops generating a LOGO image, and shuts down the image card generating module 101 after restoring to an initial state.

Example 5:

in order to facilitate obtaining the pre-stored card information, on the basis of the foregoing embodiments, in an embodiment of the present invention, the FPGA100 further includes: a storage module 105.

The storage module 105 is used for storing the graphic card information of the LOGO image;

the image card generating module 101 is configured to obtain the image card information saved in advance from the storage module 105.

As a possible storage method, the card information of the LOGO image stored in advance may be stored in an internal ROM of the FPGA100, or may be stored in an external memory connected to the FPGA 100. Specifically, the embodiment of the present invention is not limited to this.

In order to conveniently acquire the stored card information, in the embodiment of the present invention, the FPGA100 further includes a storage module 105, and the storage module 105 is configured to store the card information of the LOGO image.

The card generating module 101 is used for acquiring the pre-saved card information from the storage module 105. Since the memory module 105 is located inside the FPGA100, storing the card information through the memory module 105 can simplify the complexity of the system and save the cost.

Example 6:

fig. 4 is a schematic structural diagram of a dual-screen television based on an FPGA according to an embodiment of the present invention, as shown in fig. 4:

the dual-screen television comprises an FPGA100 and also comprises: an MCU200 and a lower panel 300;

the FPGA100 is configured to send a first signal to the MCU200 when determining that a stable image signal is not received;

the MCU200 is used for generating a starting command and sending the starting command to the FPGA100 after receiving the first signal;

the FPGA100 is further configured to generate a LOGO image to be displayed on a lower panel according to picture card information of a pre-stored LOGO image after receiving the start command, and send the LOGO image to the lower panel 300, where the picture card information includes light transmittance information;

the lower panel 300 is configured to receive and display the LOGO image.

In the embodiment of the present invention, the MCU200 is connected to the FPGA100, and the FPGA100 is configured to receive an image signal. The FPGA100 transmits a first signal to the MCU200 when it determines that a stable image signal is not received.

After the MCU200 receives the first signal, the MCU200 determines that the FPGA100 does not receive a stable image signal, and therefore the FPGA100 cannot generate a LOGO image to be displayed on a lower panel through the received image signal, and the MCU200 generates a start command and transmits the start command to the FPGA100, wherein the start command is used to control the FPGA100 to generate the LOGO image to be displayed on the lower panel.

After receiving the start command, the FPGA100 generates a LOGO image to be displayed on the lower panel according to the graphics card information of the LOGO image stored in advance, and sends the LOGO image to the lower panel 300. The lower panel 300 receives the LOGO image sent by the FPGA100 and displays the LOGO image.

Specifically, the method for displaying the lower panel according to the received image belongs to the prior art, and the embodiment of the present invention is not limited thereto.

Example 6:

in order to display a main interface image after the LOGO image is displayed, on the basis of the above embodiment, in the embodiment of the present invention, the FPGA100 is specifically configured to send a second signal to the MCU200 after the LOGO image is displayed and when it is determined that a stable image signal is received;

the MCU200 is further configured to generate a close command for controlling the FPGA to stop generating the LOGO image after receiving the second signal, and send the close command to the FPGA 100;

the FPGA100 is specifically configured to stop generating the LOGO image after receiving the close command, generate a main interface image, and send the main interface image to the lower panel.

The lower panel 300 is further configured to receive and display the main interface image.

In the embodiment of the present invention, after the LOGO image is displayed and when a stable image signal is received, the FPGA100 sends a second signal to the MCU200 in order to complete the switching to the main interface image.

After receiving the second signal, the MCU200 determines that the LOGO image is displayed completely and can display the main interface image, and the MCU200 can control the FPGA to switch from generating the LOGO image to generating the main interface image, so that the MCU200 generates a close command for controlling the FPGA100 to stop generating the LOGO image and sends the close command to the FPGA 100.

After receiving the close command, the FPGA100 stops generating the LOGO image, generates the main interface image, and sends the main interface image to the lower panel 300. The lower panel 300 receives and displays the main interface image transmitted by the FPGA 100.

The dual-screen television further includes a logic board TCON500, a chip level system SOC600, an HDMI-VBO chip 700, and a display screen 800, which have the same functions as those in the prior art and are not described in detail in the embodiments of the present invention.

The dual-screen television of the present invention is described below with a specific embodiment, and fig. 5 is a schematic structural diagram of a dual-screen television provided in the embodiment of the present invention, as shown in fig. 5:

the dual-screen television includes: the system comprises an FPGA100, an MCU200, a lower panel 300, an upper panel 400, a logic board TCON500, a chip level system SOC600, an HDMI-to-VBO chip 700 and a display screen 800. The display screen 800 includes a lower panel 300 and an upper panel 400.

In the embodiment of the present invention, the logic board TCON500 is connected to the SOC600 and the upper board 400, respectively.

The FPGA100 is connected to the MCU200, the HDMI-VBO chip 700, and the lower panel 300, respectively.

The HDMI-VBO chip 700 is connected to the FPGA100 and the SOC600, respectively.

In the dual-screen television of the embodiment of the invention, after the dual-screen television is powered on, the SOC600 of the chip-level system loads a program, and the FPGA100 loads a netlist file. After the chip-level system SOC600 and the FPGA100 are loaded, the subsequent operations may be performed.

The chip level system SOC600 first loads the LOGO subprogram, so that the display screen 800 displays a LOGO image when the device is turned on, and then loads the main interface program, so that the display screen 800 displays a main interface image.

After the LOGO subprogram of the chip level system SOC600 is loaded, the chip level system SOC600 sends an image signal of a LOGO image to the logic board TCON500, the LOGO image to be displayed on the upper panel is output after being processed by the logic board TCON500, and the LOGO image to be displayed on the upper panel is sent to the upper panel 400 by the logic board TCON 500. The image signal transmitted to the logic board TCON500 is an image signal in VBO format.

The upper panel 400 receives and displays the LOGO image transmitted from the logic board TCON 500.

Meanwhile, the SOC600 also sends an image signal to the HDMI-to-VBO chip 700. The image signal is an image signal in a High Definition Multimedia Interface (HDMI) format, and after passing through the HDMI-to-VBO chip 700, the image signal is converted into an image signal in a digital display Interface (V-By-One, VBO) format.

The HDMI-to-VBO chip 700 transmits the converted image signal in the VBO format to the FPGA 100.

After the loading of the netlist file by the FPGA100 is completed, the MCU200 configures parameters for the FPGA100, and after the parameter configuration is completed, the FPGA100 receives the converted image signal in the VBO format. After determining that the stable image signal is not received, the FPGA100 transmits a first signal to the MCU 200.

After receiving the first signal, the MCU200 generates a start command and sends the start command to the FPGA 100.

After receiving the start command, the FPGA100 generates a LOGO image to be displayed on the lower panel according to the graphics card information of the LOGO image stored in advance, and sends the LOGO image to the lower panel 300.

The lower panel 300 receives and displays a LOGO image sent by the FPGA 100.

After the LOGO image is displayed, the chip level system SOC600 starts to load the main interface program, and the chip level system SOC600 respectively sends the image signal of the main interface image to the logic board TCON500 and the HDMI-to-VBO chip 700.

After the image signal of the main interface image is processed by the logic board TCON500, the LOGO image to be displayed on the upper panel is output, and the logic board TCON500 sends the LOGO image to be displayed on the upper panel to the upper panel 400.

The upper panel 400 receives and displays the main interface image transmitted from the logic board TCON 500.

After the image signal of the main interface image is converted by the HDMI-to-VBO chip 700, the image signal in the HDMI format is converted into an image signal in the VBO format. Since the FPGA100 has received the stable image signal within the time range of the LOGO image display, the FPGA100 generates the main interface image to be displayed on the lower panel 300 according to the received image signal of the main interface image, and outputs the main interface image to the lower panel 300.

Since the FPGA100 can switch to the main interface image after the LOGO image is displayed and it is determined that the stable image signal is received, the FPGA100 transmits the second signal to the MCU200 after the LOGO image is displayed and it is determined that the stable image signal is received.

After receiving the second signal, the MCU200 generates a close command for controlling the FPGA100 to stop generating the LOGO image, and sends the close command to the FPGA 100.

After receiving the close command, the FPGA100 stops generating the LOGO image, generates a main interface image, and sends the main interface image to the lower panel 300.

The lower panel 300 receives and displays the main interface image transmitted by the FPGA 100.

Example 7:

in order to solve the problem that a blank screen and a screen splash are generated when a screen folding television is started to display in the prior art, the embodiment of the invention provides a starting display method which is applied to the FPGA in any one of the embodiments, and the method comprises the following steps:

if the stable image signal is not received by the image signal, transmitting a first signal to the MCU;

and sending the LOGO image to a lower panel for display.

Further, the sending the LOGO image to a lower panel for display comprises:

Further, the method further comprises:

The specific implementation process of the power-on display method is described in the above embodiments, and is not described herein again.

Example 9:

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and on the basis of the foregoing embodiments, the embodiment of the present invention further provides an electronic device, which includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, where the processor 601, the communication interface 602, and the memory 603 complete communications therebetween through the communication bus 604;

the memory 603 has stored therein a computer program which, when executed by the processor 601, causes the processor 601 to perform the steps of:

and sending the LOGO image to a lower panel for display.

The processor 601 is specifically configured to receive a clock signal sent by the MCU and generate a first timing signal for controlling display of the LOGO image;

The processor 601 is specifically configured to send the LOGO image to be displayed to the lower panel for display at each first target time.

The processor 601 is further configured to send a second signal to the MCU after the LOGO image is displayed and when it is determined that a stable image signal is received;

The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface 602 is used for communication between the above-described electronic apparatus and other apparatuses.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Alternatively, the memory may be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, including a central processing unit, a Network Processor (NP), and the like; but may also be a Digital instruction processor (DSP), an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.

Example 10:

on the basis of the foregoing embodiments, an embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, where the computer program is executed by a processor to perform the following steps:

and sending the LOGO image to a lower panel for display.

Further, the sending the LOGO image to a lower panel for display comprises:

Further, the method further comprises:

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. The FPGA is characterized by comprising a graphic card generating module, an output end TX module and a VBO-RX module;

the output end TX module is used for receiving a LOGO image to be displayed on the lower panel and sending the LOGO image to the lower panel for display;

the VBO-RX module is specifically configured to determine whether an image signal received by the VBO-RX module is locked, and if not, determine that a stable image signal is not received; if so, analyzing each image to be displayed corresponding to the second time sequence signal according to the image signal, judging whether the number of pixel points contained in each image to be displayed is within a preset numerical range, and if not, determining that a stable image signal is not received; and if so, determining that the stable image signal is received.

2. The FPGA of claim 1, wherein said graphics card generation module comprises:

3. The FPGA of claim 2, wherein said graphics card generation module further comprises: an MCU _ REG sub-module;

4. The FPGA of claim 1, wherein the VBO-RX module is further configured to control the VBO-RX module to reset when receiving a first control signal sent by the MCU, wherein the first control signal is sent after the MCU receives the first signal.

5. The FPGA of claim 1, further comprising: a screen folding algorithm processing module;

the screen folding algorithm processing module is configured to determine each second target time for displaying an image according to the second timing signal analyzed by the VBO-RX module and the image data of the image signal, and send the image data to the output terminal TX module at each second target time;

6. The FPGA of claim 1, further comprising: a storage module;

7. A dual-screen television based on the FPGA of any one of claims 1-6, characterized in that the dual-screen television further comprises: an MCU and a lower panel;

the FPGA is used for sending a first signal to the MCU when determining that a stable image signal is not received; the image processing device is specifically used for judging whether the image signal received by the image processing device is locked or not, and if not, determining that the stable image signal is not received; if so, analyzing each image to be displayed corresponding to the second time sequence signal according to the image signal, judging whether the number of pixel points contained in each image to be displayed is within a preset numerical range, and if not, determining that a stable image signal is not received; if yes, determining that a stable image signal is received;

and the lower panel is used for receiving and displaying the LOGO image.

8. The dual-screen television of claim 7, wherein the FPGA is specifically configured to send a second signal to the MCU after the LOGO image is displayed and when it is determined that a stable image signal is received;

9. A boot display method, the method comprising:

sending the LOGO image to a lower panel for display;

wherein the process of determining that a stable image signal is not received comprises:

judging whether the image signal received by the MCU is locked or not, if not, determining that the stable image signal is not received, and transmitting a first signal to the MCU; if so, analyzing each image to be displayed corresponding to the second time sequence signal according to the image signal, judging whether the number of pixel points contained in each image to be displayed is within a preset numerical range, and if not, determining that the stable image signal is not received.

10. An electronic device, characterized in that the electronic device comprises a processor and a memory, the memory is used for storing computer programs, and the processor is used for implementing the steps of the power-on display method as claimed in claim 9 when executing the computer programs stored in the memory.

11. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the power-on display method according to claim 9.