JP2005252355A - Clock shaping device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable detecting frequency abnormalities of a reference signal which to be inputted. <P>SOLUTION: A clock shaping device 10 has a phase comparing section 14 for outputting a phase difference signal Sd, corresponding to a phase difference between a reference signal Sr and a comparing signal Sf; a loop filter 16 for outputting a control voltage Vc corresponding to the phase difference signal Sd; a voltage-controlled oscillator circuit 18 for generating a comparison signal Sf phase-controlled by the control voltage Vc; an out-of-synchronization detector 20 for comparing the phase difference signal Sd outputted from the section 14 with a reference phase difference signal to detect out-of-synchronization; a frequency abnormality detector 22 for comparing the control voltage Vc outputted from the loop filter 16 with a reference voltage to detect the frequency abnormality of the reference signal, and an abnormal signal output 24 for outputting an abnormality occurrence signal, when either of an out-of-synchronization detecting signal Es outputted from the section 20 or a frequency abnormality detecting signal Ef outputted from the section 22 is inputted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock shaping device using a PLL circuit that outputs a clock signal synchronized with an input reference clock signal.

  In a communication device using a communication network (network) such as a cellular phone, communication data is transmitted and received based on a clock signal from an oscillator. The role of the clock signal in the network is to distribute a common frequency in the network and to synchronize the network. The range in which the frequency is distributed depends on the basic configuration of the network. In the case of a long-distance communication system, a network synchronization type network is configured. In a network synchronous network, a clock signal having a reference frequency (hereinafter referred to as a reference clock signal) is distributed from one master station or a quasi-master station, and this reference clock signal is reproduced at all nodes in the network. Distribute to all of. In this method, all the circuits in the network operate with a clock signal having the same frequency accuracy, and transmission / reception processing such as data multiplexing / demultiplexing and information insertion / extraction using a memory can be performed very easily. .

Many clock shaping devices that regenerate a reference clock signal in a node or the like use a PLL circuit using a voltage-controlled oscillator. The PLL circuit is configured such that the voltage-controlled oscillator outputs a clock signal that is phase-synchronized with the reference clock signal. An electronic device having a clock shaping device operates using a clock signal output from the clock shaping device. Such an electronic device cannot operate normally if the clock signal output from the clock shaping device is not synchronized with the reference clock signal for some reason. For this reason, the clock shaping device is provided with a synchronization detection circuit, the signal output from the phase comparator of the PLL circuit is input to the synchronization detection circuit, and the clock signal output from the voltage controlled oscillator is phase-synchronized with the reference clock signal. There is one that detects whether or not (locked) (for example, Patent Document 1). When the PLL circuit is out of phase synchronization and unlocked, the electronic device sounds an alarm to notify the clock shaping device that an abnormality has occurred.
JP-A-10-322199

  By the way, the frequency of the reference clock signal has a certain allowable range with respect to the reference frequency in consideration of the operating environment of the oscillator that generates the reference clock signal or the characteristics of the individual oscillators. The PLL circuit is set with the voltage value of the control voltage output from the loop filter applied to the voltage controlled oscillator so that it can follow the reference clock signal in the allowable frequency range. On the other hand, voltage controlled oscillators, such as voltage controlled crystal oscillators (VCXOs), vary in the amount (rate of change) of the oscillation frequency with respect to changes in the control voltage due to characteristics of the crystal wafer and manufacturing errors. It depends on the oscillator.

FIG. 3 shows an example of the frequency control characteristics of the VCXO. When the control voltage applied to the VCXO changes from 0 [V] to the maximum value Vcmax [V], the reference frequency f ₀ of the reference signal (reference clock signal) when the control voltage is the center value Vcmax / 2 [V]. It is trying to become. Then, when the control voltage is changed from 0 [V] to the maximum value Vcmax [V], the control voltage is set so that a specified frequency fluctuation amount of ± δf is obtained. On the other hand, in the above-described synchronization detection circuit or the like, when the phase detector outputs a phase difference signal that changes the oscillation frequency of VCXO by exceeding ± δf, the clock signal is out of synchronization with the reference clock signal. The alarm is set to be issued. However, as described above, the frequency control characteristics differ depending on the individual VCXO, and even when the reference clock signal is out of the standard, the clock signal out of the standard is output in phase synchronization with the reference clock signal without any abnormality. There are things to do.

For example, the VCXO shown by the curve A in FIG. 3 has to change the control voltage from approximately 0 to Vcmax [V] in order to obtain the frequency fluctuation amount of −δf to + δf. On the other hand, the VCXO shown in the curve B can obtain the required frequency change amount by changing the control voltage smaller than that of the curve A. That is, the frequency of the VCXO of the curve B changes to a range far wider than ± δf when the control voltage is changed from 0 to Vcmax [V]. For this reason, the PLL circuit having the VCXO of the curve B has a reference clock signal of f ₀ +70 ppm due to some abnormality when, for example, the allowable range of the frequency of the reference clock signal is defined as ± 50 ppm with respect to the reference frequency f ₀ . Even when is input, a clock signal synchronized with this is output. For this reason, an electronic device using this clock signal cannot operate normally because the clock signal is out of the standard. In such a case, it may be difficult to grasp the cause of the failure, that is, based on the abnormality of the reference clock signal. Therefore, it is desired that the clock shaping device can detect the abnormality of the reference clock signal. However, in the clock shaping device described in Patent Document 1, although the PLL circuit can detect a synchronous (locked) or asynchronous (unlocked) state, it detects an abnormality in the frequency of the reference clock signal. Can not do it.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the prior art, and has an object to detect a frequency abnormality of an input reference signal.
Another object of the present invention is to make it possible to reliably know that a frequency abnormality of the reference signal has occurred.

  In order to achieve the above object, the present invention provides a phase comparison unit that receives a reference signal and a comparison signal and outputs a phase difference signal corresponding to the phase difference between the reference signal and the comparison signal, and the phase output by the phase comparison unit. A loop filter that outputs a control voltage according to a phase difference signal; a voltage-controlled oscillation circuit that generates a comparison signal phase-controlled by the control voltage output from the loop filter and inputs the comparison signal to the phase comparison unit; and the phase The phase difference signal output by the comparison unit is compared with a reference phase difference signal, and the out-of-synchronization detection unit detects the loss of synchronization of the comparison signal with respect to the reference signal, and the control voltage output by the loop filter is compared with the reference voltage. A frequency abnormality detection unit that detects a frequency abnormality of the reference signal, an out-of-synchronization detection signal output from the out-of-synchronization detection unit, and a frequency abnormality detection signal output from the frequency abnormality detection unit. Any of when you type is characterized by having a abnormal signal output unit that outputs an abnormality occurrence signal. The reference voltage to be compared with the control voltage is determined for each voltage control type oscillation circuit by measuring frequency control characteristics in advance for each voltage control type oscillation circuit.

  As described above, the oscillation frequency of a voltage controlled oscillation circuit such as a voltage controlled crystal oscillator (VCXO) changes depending on the control voltage. Therefore, by monitoring the control voltage, the frequency of the output signal of the voltage controlled oscillation circuit can be known. Therefore, the present invention detects the frequency abnormality of the reference signal by comparing the control voltage output from the loop filter with the reference voltage corresponding to the allowable frequency range of the reference signal (reference clock signal). . The abnormality signal output unit outputs an abnormality occurrence signal when the frequency abnormality detection unit detects a frequency abnormality of the reference signal. As a result, the voltage-controlled oscillation circuit has frequency control characteristics such as the curve B in FIG. 3 and can follow a wider frequency than necessary with respect to the upper limit value or lower limit value of the control voltage. Even so, it is possible to reliably detect that an abnormality has occurred in the frequency of the reference signal, and to know that the output signal (clock signal) is abnormal.

  The out-of-synchronization detection unit operates a synchronization abnormality display unit when detecting out-of-synchronization, and the frequency abnormality detection unit operates a frequency abnormality display unit when a frequency abnormality of the reference signal is detected. Can be configured to As a result, it is possible to easily and surely know whether the abnormality of the output signal of the clock shaping device is an abnormality due to loss of synchronization or the abnormality of the frequency of the reference signal.

A preferred embodiment of a clock shaping device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram of a clock shaping device according to the present invention. In FIG. 1, the clock shaping device 10 includes a PLL circuit 12. The PLL circuit 12 includes a phase comparison unit 14, a loop filter 16, and a voltage control type oscillation circuit 18. The phase comparison unit 14 receives a reference signal (reference clock signal) Sr and an output signal of the voltage controlled oscillation circuit 18 as a comparison signal Sf. Then, the phase comparison unit 14 obtains a phase difference between the two and outputs a phase difference signal Sd corresponding to the phase difference to the loop filter 16. The loop filter 16 smoothes the input phase difference signal Sd and outputs it to the voltage controlled oscillation circuit 18 as the control voltage Vc.

  In the embodiment, the voltage-controlled oscillation circuit 18 is a voltage-controlled crystal oscillator (VCXO) having an AT-cut crystal resonator, or a voltage-controlled type having a surface acoustic wave resonator. It is constituted by a SAW oscillator (VCSO). The voltage controlled oscillation circuit 18 is phase-controlled by the control voltage Vc output from the loop filter 16 and outputs a signal (clock signal) S synchronized with the reference signal Sr input to the phase comparison unit 14 to the outside. The signal S is input to the phase comparison unit 14 as a comparison signal Sf.

  The clock shaping device 10 further includes an out-of-synchronization detection unit 20 connected to the output side of the phase comparison unit 14, a frequency abnormality detection unit 22 connected to the output side of the loop filter 16, an out-of-synchronization detection unit 20, and a frequency abnormality detection unit 22. The abnormal signal output unit 24 to which the output signal is input is provided. The out-of-synchronization detection unit 20 is provided with a reference phase difference signal in advance, compares the phase difference signal Sd output from the phase comparison unit 14 with the reference phase difference signal, and the PLL circuit 12 enters a so-called unlocked state in which synchronization is lost. It is monitored whether or not. Further, the frequency abnormality detection unit 22 is provided with a reference voltage in advance, compares the control voltage Vc output from the loop filter 16 with the reference voltage, and monitors whether an abnormality has occurred in the frequency of the reference signal Sr. Yes.

  The abnormality signal output unit 24 outputs an abnormality occurrence signal to the alarm circuit 30 when the out-of-synchronization detection unit 20 outputs the out-of-synchronization detection signal Es or when the frequency abnormality detection unit 22 outputs the frequency abnormality detection signal Ef. To do. Further, the out-of-synchronization detection unit 20 operates by outputting a signal to the out-of-synchronization display unit (synchronization abnormality display unit) 32 when the comparison signal Sf is out of synchronization with the reference signal Sr. The fact that the PLL circuit 12 is in an unlocked state is notified by turning on the lamp or the like. Further, when the frequency abnormality detection unit 22 detects that the frequency of the reference signal Sr exceeds the allowable fluctuation range, the frequency abnormality detection unit 22 operates by giving a signal to the frequency abnormality display unit 34, for example, lighting a yellow lamp. To notify the frequency abnormality of the reference signal Sr.

  The operation of the clock shaping device 10 configured as described above is as follows. The phase comparison unit 14 of the PLL circuit 12 receives a reference signal (reference clock signal) Sr extracted from data input from the outside and a comparison signal (comparison clock signal) Sf output from the voltage controlled oscillation circuit 18. To do. The phase comparison unit 14 obtains a phase difference between the input reference signal Sr and the comparison signal Sf, and outputs a phase difference signal Sd corresponding to the phase difference to the loop filter 16. The loop filter 16 smoothes the phase difference signal Sd output from the phase comparison unit 14 and outputs it to the voltage controlled oscillation circuit 18 as the control voltage Vc. The voltage-controlled oscillation circuit 18 outputs a comparison signal Sf whose phase is controlled to match the phase of the reference signal Sr by the input control voltage Vc, and inputs the comparison signal Sf to the phase comparison unit 14. When the reference signal Sr is normal, the PLL circuit 12 repeats such an operation, and the voltage-controlled oscillation circuit 18 outputs a signal (clock signal) S whose phase is synchronized with the reference signal Sr to an external device or circuit. .

On the other hand, the detector 20 out of synchronization, the reference signal Sr reference frequency f ₀ is the frequency of -δf or + delta] f even when the offset, two such can oscillate to follow the voltage controlled oscillator 18, Reference phase difference signals -Sdr and + Sdr are preset. The out-of-synchronization detection unit 20 reads the phase difference signal Sd output from the phase comparison unit 14 and compares it with the reference phase difference signal ± Sdr. When the phase difference signal Sd output from the phase comparator 14 is smaller than the reference phase difference signal −Sdr or larger than the reference phase difference signal + Sdr, the out-of-synchronization detection unit 20 causes the voltage-controlled oscillation circuit 18 to change to the reference signal Sr. Since there is a possibility that the oscillation cannot be followed, the out-of-synchronization detection signal Es is output to the abnormal signal output unit 24 and the out-of-synchronization display unit 32.

  When the out-of-synchronization detection signal Es is input from the out-of-synchronization detection unit 20, the abnormal signal output unit 24 outputs an abnormality occurrence signal to the alarm circuit 30 to generate an alarm. Further, the out-of-synchronization display unit 32 turns on, for example, a red lamp in response to a signal from the out-of-synchronization detection unit 20, and displays that the PLL circuit 12 is out of synchronization and is unlocked. Thereby, the user of the electronic device can easily recognize that the signal S output from the voltage controlled oscillation circuit 18 is an abnormal lock signal that is not synchronized with the reference signal Sr.

A reference voltage to be compared with the control voltage Vc output from the loop filter 16 is given in advance to the frequency abnormality detection unit 22. The reference voltage corresponds to the reference frequency -δf against f ₀ or + control voltage for outputting a signal S of the frequency of the delta] f, of the reference signal Sr voltage controlled oscillator 18. The reference voltage is individually set corresponding to the frequency control characteristic of each voltage controlled oscillation circuit 18. That is, when the frequency control characteristic of the voltage-controlled oscillation circuit 18 by the control voltage Vc is as shown by the curve F in FIG. 2, for example, the frequency whose variation is −δf with respect to the reference frequency f ₀ is oscillated. V _F1 corresponding to the control voltage to be set and V _F2 corresponding to the control voltage for oscillating the frequency having the fluctuation amount of + δf are set. Further, when the voltage-controlled oscillation circuit 18 has frequency control characteristics as shown by the curve G in FIG. 2, V _G1 and V _G2 are set as reference voltages.

Then, the frequency abnormality detecting unit 22, _{if V G1, V G2} is set as the reference voltage, the output and the control voltage Vc of the loop filter 16 is a Vc _{<V G1,} or _{V> V G2,} the reference signal The frequency abnormality detection signal Ef is output to the abnormality signal output unit 24 and is output to the frequency abnormality display unit 34, assuming that the frequency of Sr is not within the range of the specified fluctuation amount ± δf. When the abnormality signal output unit 24 receives the frequency abnormality detection signal Ef from the frequency abnormality detection unit 22, the abnormality signal output unit 24 outputs an abnormality occurrence signal to the alarm circuit 30 to generate an alarm. Further, the frequency abnormality display unit 34 displays that a frequency abnormality has occurred in the reference signal Sr by, for example, turning on a yellow lamp by a signal from the frequency abnormality detection unit 22. As a result, the user of the device can easily recognize that an abnormality has occurred in the frequency of the reference signal Sr. Further, for example, it has a frequency control characteristic as shown by a curve G in FIG. 2 and follows a frequency much higher or lower than a specified frequency range by the control voltage Vc output from the loop filter 16. In addition, it is possible to reliably detect the frequency abnormality of the reference signal Sr.

  In the embodiment, the out-of-synchronization detection signal Es of the out-of-synchronization detection unit 20 is input to the out-of-synchronization display unit 32, and the frequency abnormality detection signal Ef of the frequency abnormality detection unit 22 is input to the frequency abnormality display unit 34. Although the case where the lamp is turned on has been described, these detection signals Es and Ef may be input to a display unit (not shown) to display out-of-synchronization or frequency abnormality.

1 is a block diagram of a clock shaping device according to an embodiment of the present invention. It is explanatory drawing of the reference voltage set to the frequency abnormality detection part which concerns on embodiment. It is explanatory drawing of the frequency control characteristic of a voltage control type oscillation circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ......... Clock shaping device, 12 ......... PLL circuit, 14 ......... Phase comparison unit, 16 ......... Loop filter, 18 ......... Voltage control type oscillation circuit, 20 ......... Out of synchronization detection unit, 22 ............ Frequency abnormality detection section 24... Abnormal signal output section 30... Alarm circuit 32... Synchronization abnormality display section (out-of-synchronization display section) 34.

Claims (2)

A phase comparator that receives a reference signal and a comparison signal and outputs a phase difference signal corresponding to the phase difference between the two;
A loop filter that outputs a control voltage according to the phase difference signal output by the phase comparator;
A voltage-controlled oscillation circuit that generates a comparison signal phase-controlled by the control voltage output by the loop filter and inputs the comparison signal to the phase comparison unit;
A phase loss detection unit that compares the phase difference signal output from the phase comparison unit with a reference phase difference signal and detects a loss of synchronization of the comparison signal with respect to the reference signal;
A frequency abnormality detection unit that compares the control voltage output by the loop filter with a reference voltage and detects a frequency abnormality of the reference signal;
An abnormality signal output unit that outputs an abnormality occurrence signal when any of the out-of-synchronization detection signal output from the out-of-synchronization detection unit and the frequency abnormality detection signal output from the frequency abnormality detection unit is input;
A clock shaping device comprising: The clock shaping device according to claim 1,
The out-of-synchronization detection unit operates a synchronization abnormality display unit when detecting out-of-synchronization,
The frequency abnormality detection unit operates a frequency abnormality display unit when detecting a frequency abnormality of the reference signal.
A clock shaping device.

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