KR100561637B1 - Apparatus for measuring distance of slave optical source and aligning phase of high speed incoming burst data received from slave optical source in passive optical network - Google Patents

Abstract

The present invention digitally phase-aligns the data so that a clock signal is located at the center of high-speed uplink burst data, and obtains a sub-bit / bit deviation value for a signal transmitted from a plurality of slave light sources. The present invention provides a device capable of measuring the position of each slave. To this end, the present invention receives high-speed burst received data received from a slave light source of a passive optical network and receives a phase of the burst received data in response to a master synchronization clock. An apparatus for aligning and outputting a byte synchronously and measuring a position of a slave light source, comprising: delay buffering means for delaying the multi-step by receiving the high-speed burst received data; Control signal processing means for generating and outputting a phase detection start signal from the distance measurement command in response to the reference synchronization signal; Output from the delay buffering means in response to preamble length information corresponding to a preamble signal in which '1' and '0' are alternating more than a predetermined number of bits from the master synchronous clock, the phase detection start signal, and a control processor matching unit. Phase aligning means for aligning the phase of the delay data; Dividing means for dividing a signal output from the phase aligning means in response to the master synchronous clock; Byte synchronization means for performing byte synchronization between the boundary signal of the burst received data and the signal received from the division means; Data extraction means for finally extracting the phase-aligned burst received data synchronized with the byte unit from the byte synchronized signal output from the byte synchronization means in response to a data read clock signal; Distance measurement data encoding means for outputting distance measurement information encoded in a data format desired by a user in response to a phase detection signal output from the phase alignment means and a bit detection signal output from the byte synchronization means; And generating an alarm signal in response to a signal loss alarm signal output from the phase alignment means and a byte synchronization failure alarm signal output from the byte synchronization means when the burst received data is not received, and outputting from the byte synchronization means. And an alarm signal generating means for generating the alarm signal in response to the normal position determination signal.

Passive optical network, slave light source, high speed burst reception data, optical receiver, delay buffer section, phase alignment section, 1: 8 divider, byte synchronizer section, ATM cell extraction section, distance measurement data encoding section, alarm signal generation section

Description

A device for phase alignment and position measurement of a slave light source for high speed burst received data received from slave light sources in a passive optical network. IN PASSIVE OPTICAL NETWORK}             

1 is a format diagram of 155 Mb / s uplink burst data (at ATM-PON recommended in ITU-T G.983).

2 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 3 is a detailed block diagram illustrating the phase aligning unit of FIG. 2 according to an embodiment of the present invention. FIG.

4 conceptually illustrates a pattern of electrical burst data extracted at an optical receiver;

5A to 5E are phase alignment timing diagrams for explaining a phase detection error that may occur when a delay signal is generated only within a clock period T time.

* Description of the main parts of the drawing

200: optical receiver 301: delay buffer unit

302: phase alignment unit 303: 1: 8 divider

304: byte synchronization unit 305: ATM cell extraction unit

306: control signal processing unit 307: distance measurement data encoding unit

308: alarm signal generator

TECHNICAL FIELD The present invention relates to passive optical network technology, and more particularly, to an apparatus for measuring phase alignment and position of a slave light source for high speed burst data transmitted by the slave light source.

Recently, with the rapid growth of the optical communication transmission technology, passive optical network technology that provides a point-to-multipoint time division multiple access (TDMA) optical transmission technology in order to provide a high-speed information communication service to the user at the lowest possible price has attracted attention.

In general, in a passive optical network, when a master signal transmits an allowance signal for accommodating only a signal of a desired slave light source to the corresponding slave light source, only the slave light source that receives the light signal transmits the optical signal. Has At this time, the master light source extracts the clock signal from the high-speed uplink burst data received from the slave light source, and aligns the phase of the data with the synchronous clock.

To this end, conventionally, the clock signal is extracted and the phases are aligned using the analog phase loopback locking (PLL) method. However, the clock signal is extracted for each burst data input at high speed (about 155 Mb / s) from each slave light source. This is not suitable because the locking time takes several hundreds of microseconds to perform the phase alignment.

Another conventional technique is to perform phase alignment and position measurements using upward serial 155 Mb / s data. However, such a conventional technology is not only difficult to use in a field programmable gate array (FPGA), which is commonly used by processing high speed signals in series, but also requires time and cost for development by using a high speed application specific integrated circuit (ASIC) device. This is not a lot.

An object of the present invention is to provide an apparatus for digitally aligning data in such a manner that a clock signal is located at the center of high-speed uplink burst data.

In addition, in the passive optical network technology, since the phase of the data is different according to the position of each slave light source, distance measurement is required to determine the position of the slave light source. To this end, the present invention provides a method for sub-signaling transmitted from various slave light sources. It is to provide a device that can measure the position of each slave by the error value of the sub-bit by obtaining the bit / bit deviation value.

In order to achieve the above object, the present invention receives high-speed burst reception data received from a slave light source of a passive optical network, and outputs the byte synchronization by aligning the phases of the burst reception data in response to a master synchronization clock. An apparatus for measuring the position of the apparatus, the apparatus comprising: delay buffering means for delaying a plurality of stages of the high-speed burst received data; Control signal processing means for generating and outputting a phase detection start signal from the distance measurement command in response to the reference synchronization signal; Output from the delay buffering means in response to preamble length information corresponding to a preamble signal in which '1' and '0' are alternating more than a predetermined number of bits from the master synchronous clock, the phase detection start signal, and a control processor matching unit. Phase aligning means for aligning the phase of the delay data; Dividing means for dividing a signal output from the phase aligning means in response to the master synchronous clock; Byte synchronization means for performing byte synchronization between the boundary signal of the burst received data and the signal received from the division means; Data extraction means for finally extracting the phase-aligned burst received data synchronized with the byte unit from the byte synchronized signal output from the byte synchronization means in response to a data read clock signal; Distance measurement data encoding means for outputting distance measurement information encoded in a data format desired by a user in response to a phase detection signal output from the phase alignment means and a bit detection signal output from the byte synchronization means; And generating an alarm signal in response to a signal loss alarm signal output from the phase alignment means and a byte synchronization failure alarm signal output from the byte synchronization means when the burst received data is not received, and outputting from the byte synchronization means. And an alarm signal generating means for generating the alarm signal in response to the normal position determination signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

The apparatus of the present invention aligns the phase of 155 Mb / s burst upstream data in the Asynchronous Transfer Mode-Passive Optical Network (ATM-PON) recommended in ITU-T G.983, and sub-bits / bits of the positions of several slave light sources. It can be used as a processing device for uplink burst data that locates and measures the position with the accuracy of.

First, the structure of the uplink burst data will be described.

FIG. 1 is a format diagram of 155 Mb / s uplink burst data 100 in ATM-PON recommended by ITU-T G.983, with a 3-byte overhead section 110 and a 53-byte ATM cell 120. It is composed. In the present invention, after collecting the phase alignment and distance position information of the data by using the three bytes of the overhead unit 110, 53 bytes of the ATM cell 120 is byte-synchronized is extracted.

In FIG. 1, the overhead portion 110 of 3 bytes is described in detail, and includes a guard time portion 112, a preamble portion 114, and a delimiter 116. At this time, the guard time unit 112 is a master clock and the slave clock is synchronized, but a bit required to compensate for jitter (jitter) and compensation according to the bit accuracy of the distance measurement coefficient composed of one master and several slaves In the point-to-multipoint TDMA scheme, it is used to avoid collisions between data coming from each slave side. It is assumed that there is no data during this time. And, the preamble section 114 is a bit necessary for the laser diode receiving the optical burst data to recover the extracted data amplitude, detect the phase difference of the various slave burst data reaching the master, and align the phase of the data with the synchronous clock. 1010 "pattern. In addition, the boundary unit 116 is a fixed pattern synchronization signal for detecting the starting point of the ATM cell 120. The boundary unit 116 performs byte synchronization after detecting at the boundary overhead.

The guard time section 112 and the preamble section constituting the overhead section 110 in ITU-T G.983 to extract the 53-byte ATM cell 120 from the uplink burst data shown in FIG. It is recommended to program the length of the 114 and the boundary 116 values respectively.

2 is a block diagram of an apparatus according to an embodiment of the present invention, which receives an up burst 155Mbs / s optical data, converts it into a serial signal of 155Mb / s, and then outputs the optical receiver 200 to the apparatus of the present invention. Shown).

Referring to FIG. 2, the apparatus of the present invention receives burst data at high speed (155 Mb / s), aligns phases of the burst data in response to the master synchronization clock (155 MHz), and performs byte synchronization. Delay buffer unit 301 for receiving the 155 Mb / s electrical burst data received from the receiver 100 and multi-stage delayed delayed data (DLY0 to DLYn) outputted from the delay buffer unit 301 to the master synchronous clock (155 MHz). Phase aligner 302 for aligning the phases of the phases), 1: 8 divider 303 for performing 1: 8 bit division using the master synchronous clock signal output from the phase aligner 302, and A byte synchronizer 304 for performing byte synchronization between the boundary portion 116 signal of the overhead portion 110 (110) and the signal received from the 1: 8 divider 303, and responds to the ATM cell read clock signal. Received from the byte synchronizer 304 An ATM cell extracting unit 305 for extracting an 53-byte ATM cell signal from the byte-synchronized signal, and generating a phase detection start signal from a distance measurement command in response to a reference synchronization signal; After the control signal processor 306 for outputting the data, the phase detection signal output from the phase alignment unit 302 and the bit detection signal output from the byte synchronizer 304 are encoded into a data format desired by the user. The signal loss alarm signal output from the phase alignment unit 302 and the byte synchronization failure alarm signal output from the byte synchronization unit 304 when there is no distance measurement data encoding unit 307 for outputting measurement information and electrical burst data. An alarm for generating an alarm signal in response, and for generating an alarm signal in response to the normal position determination signal output from the byte synchronizer 304 It comprises a number generator (308).

First, the delay buffer unit 301 for receiving the 155 Mb / s electrical burst data received from the optical receiver 100 and performing the multi-stage delay will be described.

The delay buffer unit 301 delays the electrical burst data in multiple stages by n divided delay times of a time (<T / 2) slightly larger than one clock cycle T time of the master synchronous clock (155 MHz). Since the delay time and routing delay time are 1 ~ 3nsec, you can adjust n value according to FPGA characteristics. For example, if the delay time of the FPGA internal buffer is 3 ns, two delay signals and one additional delay signal DLY0 (DLY0) within one period T time (6.43 ns) of the master synchronization clock (155 MHz) using three delay buffers are used. Input signal), DLY1, DLY2, and DLY3). Here, T / 2 may be "0" if the delay signal is exactly T / n within one period, but since the internal delay time of the FPGA may be different, the delay signal existing in the one period and the additional delay signal are added. The phase detection and phase alignment can be performed without using an error.

Next, the phase alignment unit 302 is driven in response to the master synchronous clock, and controls the phase detection start signal and the overhead data register output from the control signal processing unit 306 (not shown). A block for selecting delay data in which a synchronous clock rising edge portion is located at the center of data among a plurality of delay data input from the delay buffer unit 301 in response to a preamble signal specified and output from FIG. It will be described in more detail through.

FIG. 3 is a detailed block diagram of the phase aligning unit of FIG. 2 according to an embodiment of the present invention, in which a master synchronization clock is inputted to a clock stage and delay data input from the delay buffer unit 301 to a data stage. A retiming buffering unit 401 including four D flip-flops each receiving DLY0 to DLY3), and four delayed signals DLYQ0 to DLYQ3 clocked to the D flip-flop output from the retiming buffering unit 401. Are input to three exclusive logic gates 402 to 404 for exclusive logic sum, a master synchronous clock signal to a clock stage, and a phase detection start signal to a reset stage, respectively, and are set from the exclusive logic gates 402 to 404 for a set stage. An asynchronous reset synchronization unit 405 composed of three RS flip-flops each receiving an output signal, and an output from an output terminal of an RS flip-flop of the asynchronous reset synchronization unit 405 Are three logical multiply gates 406 through 408 for receiving and logically multiplying the signals and the signals output from the exclusive logical sum gates 402 through 404, a master synchronous clock as a clock stage, and a phase detection start signal as a reset stage, respectively. An asynchronous reset synchronization unit 409 composed of three RS flip-flops that receive input and output signals from the AND gates 406 through 408 in set stages, and RS flip-flops of the asynchronous reset synchronization unit 409. Phase-detection of a master synchronous clock with a clock stage and three logic multiply gates 410 through 412 for receiving and logically multiplying a signal output from an output stage and a signal output from the exclusive logic gates 402 through 404. A phase selection signal SEL0 is inputted to each of the start signals and the signals output from the logical multiplying gates 410 to 412 to the set stages. Asynchronous reset synchronous unit 413 composed of three RS flip-flops each outputting SEL2), and a phase selection signal SEL3 [0: 2] is inputted from the asynchronous reset synchronous unit 413 to perform a logical sum to detect a phase. Logic sum gate 414 for outputting the end signal and phase select signals SEL1 [0: 2] and SEL2 [0: respectively output from the three asynchronous reset synchronization units 405, 409, and 413 in response to the preamble length information. 2], SEL3 [0: 3]) to select the multiplexer 419 for outputting the phase selection signal SEL [0: 2], and to the D flip-flop output from the retiming buffering unit 401. A three-stage D flip-flop buffer 415 consisting of three D flip-flops that receive four clocked delay signals DLYQ0 to DLYQ3 as inputs and delay in multiple steps in response to the master sync clock, and input the master sync clock to the clock stage. Three outputted from the three-stage D flip-flop buffer 415 to the data stage. Two D flip-flops 416 and 417 respectively receiving two signals of a call and two D flip-flops 416 in response to a phase selection signal SEL [0: 2] output from the multiplexer 419. Multiplexer 418 for selecting one of the signal from 417 and the remaining one signal output from the three-stage D flip-flop buffer 415 and outputting the phase-aligned signal to the 1: 8 divider 303 Is made of.

Here, the three-stage asynchronous reset synchronization units 405, 409, and 413 reset all RS flip-flops when the phase detection start signal is received, clear all the flip-flop values, and then set the master synchronization clock according to the phase change. Set the RS flip-flop in synchronization.

The retiming buffering unit 401 receives the delay data DLY0 to DLY3 input from the delay buffer unit 301 in order to prevent metastability errors caused by data conversion at the edges of the digital logic. The re-timing is performed using the D flip-flop and the change of phase detection is detected from the re-timed signal using the exclusive logic gates 402 to 404. However, these detected signals (ie, output signals of the exclusive logic gate) may commit an error of phase detection according to the pattern of electrical burst data extracted from the optical receiver 200 as shown in FIG. 4.

4 is a diagram conceptually illustrating a pattern of electrical burst data extracted from the optical receiver 200. When the pattern of the electrical burst data is a normal data pattern as shown in (a), phase detection has been performed once, that is, Although the multiplexer 418 may be controlled by the output signals of the exclusive logic gates 402 through 404, the eye pattern of the electrical burst data is 50:50 tutu as shown in (b), (c), and (d). In case of not having, the output signal of the exclusive logic gate is used as the selection signal of the multiplexer 418, so that unwanted delay data can be selected. Therefore, the asynchronous reset synchronization units 405, 409, and 413 connected to the exclusive logic gates 402 to 404 can be configured to ensure the accuracy of edge detection.

For example, when a signal having a narrow data pattern is received as a delay signal as shown in FIG. 4C, the phase selection output from the asynchronous reset synchronization unit 413 by the multiplexer 419 in response to the preamble length information is performed. By selecting the signal SEL3 [0: 2] and the selected phase selection signal SEL3 [0: 2] controlling the multiplexer 418, it is possible to prevent the accuracy of the edge detection and the error of the noise application signal.

Therefore, when the phase selection signal is generated by using the three-stage asynchronous reset synchronization units 405, 409, and 413, the preamble signal is composed of alternating signals of '1' and '0' with at least 6 bits. The matching unit (not shown) provides 6 bits of preamble length information. That is, when the length of the preamble signal is 4 bits, the phase selection signal SEL2 [0: 2] output using only the asynchronous reset synchronization unit of two stages may be selected in response to the preamble length information. Since there may be inaccuracies in noise or edge detection, use preamble length information with a length of at least 6 bits.

Since the three-stage D flip-flop buffer 415 selects any one of the delay signals using the phase selection signals SEL0 to SEL2 output from the asynchronous reset synchronization unit 413 in the multiplexer 418, the retiming is performed. The delay signals DLYQ0 to DLYQ3 are delayed to match the delay signals DLYQ0 to DLYQ3 output from the buffering unit 401 to the timing at which the phase selection signals SEL0 to SEL2 are output.

5A to 5E are phase alignment timing diagrams for explaining a phase detection error that may occur when a delay signal is generated only within a clock period T time. The T time is 6.43 ns and the delay time dT of each internal buffer. Let's look at the phase detection error with 3nsec fixed.

The timing chart of FIG. 5A is a timing chart of delaying the delay signal within d time by dT. A signal delaying DLY0 (input signal) by dT is a DLY1 signal, a signal delaying the DLY1 signal by dT again is a DLY2 signal, and a signal delaying the DLY2 signal by dT again is a DLY3 signal. As described above, the phase selection signals SEL0, SEL1, and SEL2 are exclusive logical sums of delay signals output from the retiming buffering unit 401 using the clock rising signal.

In the period T of the master synchronous clock, each dT region is defined as A, B, and C, and when the rising edge of the master synchronous clock is present in the region A, the rising edge of the clock in the center of the DLY2 signal among the delay signals as shown in the figure. It can be seen that there exists. At this time, the SEL [0: 1] value is " 10 " as shown in FIG. 5B. Using this SEL value, DLYQ2 is selected. In the same manner, the DLYQ0 signal is selected when there is a rising edge of the master synchronization clock in the area B. However, when the rising edge of the master synchronous clock exists in the region C, and the DLY signal generates only a delay signal in the T region as shown in FIG. 5C (that is, when only DLY0, DLY1, and DLY2 are used), If the SEL [0: 1] value as shown in Fig. 5D is " 10 ", select &lt; RTI ID = 0.0 &gt; DLYQ2 &lt; / RTI &gt; It may also cause data errors due to external noise.

Therefore, as shown in FIG. 5E, when DLY0, DLY1, DLY2, and DLY3 are used, and the value of SEL [0: 2] is "001" or "101", data is selected by selecting DLY1 having the clock rising edge located at the center of the data. Ensure that processing is not subject to external noise or jitter.

Next, the 1: 8 divider 303 of FIG. 2 provided in the apparatus of the present invention performs simple 1: 8 bit division using the phase-aligned signal output from the phase aligner 302 and the master synchronous clock. The byte synchronizer 304 performs a byte between the boundary signal outputted from the processor controller (not shown in the drawing) and the signal divided from the 1: 8 divider 303 to control the overhead data register. In performing synchronization, the byte synchronization start is started in response to the phase detection end signal from the phase alignment unit 302. In addition, the byte synchronizer 304 outputs a normal position determination signal to the alarm signal generator 308 when electrical burst data exists at an unwanted position compared to the reference synchronization signal.

In the byte synchronization unit of the present invention, eight boundary signal patterns may exist in 8-bit parallel synchronization. The byte synchronization is performed by comparing eight patterns from the unaligned signal received from the 1: 8 divider 303. For example, when the boundary signal pattern is “11011000,” an eight-divided pattern has a pattern as shown in Table 1 below when two registers, that is, a 16-bit register, are used. In Table 1 below, the boundary signal is underlined, and the data before the boundary signal is preamble pattern data. The data behind the boundary signal becomes ATM cell data.

Here, since the distance can be extracted for each bit according to the signal synchronized with the eight patterns, the bit detection signal according to the eight boundary signal patterns can be extracted.

The ATM cell extracting unit 305 extracts an 53-byte ATM cell signal from the byte-synchronized signal, and extracts the byte cell in bytes in response to the ATM cell read clock.

In addition, the distance measurement data encoding unit 307 is a portion that encodes a format desired by a user by using a phase detection signal from the phase alignment unit 302 and a bit detection signal from the byte synchronization unit 304, and a reference synchronization signal. Compared with, the distance measurement information value is displayed and output in sub-bits (phases) and bit units.

Finally, when there is no electrical burst data, the alarm signal generator 308 generates a signal loss alarm signal in which the phase selection signals SEL0 to SEL2 are all “0” in the phase aligner 302, and the byte synchronizer ( When the byte synchronization failure alarm signal is sent in 304, an alarm signal is output, and when the electrical burst data signal exists in an unwanted position compared with the reference synchronization signal, the normal position determination signal output from the byte synchronization unit 304 In response to the alarm signal is output.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention made as described above, in a passive optical network, when an allow signal for accommodating only a signal of a desired slave light source from a master light source is transmitted to a corresponding slave light source, an optical signal is transmitted only from the slave light source that receives the ITU-T G.983. It can be used as a dedicated device to obtain the phase alignment of burst upstream 155Mb / s data and the position measurement of the slave light source in the ATM-PON recommended by.

Claims (5)

An apparatus for receiving high-speed burst received data received from a slave light source of a passive optical network, aligning the phases of the burst received data, outputting them in byte synchronization in response to a master synchronization clock, and measuring the position of the slave light source. Delay buffering means for receiving the high speed burst received data and delaying the data in multiple stages; Control signal processing means for generating and outputting a phase detection start signal from the distance measurement command in response to the reference synchronization signal; Output from the delay buffering means in response to preamble length information corresponding to a preamble signal in which '1' and '0' are alternating more than a predetermined number of bits from the master synchronous clock, the phase detection start signal, and a control processor matching unit. Phase aligning means for aligning the phase of the delay data; Dividing means for dividing a signal output from the phase aligning means in response to the master synchronous clock; Byte synchronization means for performing byte synchronization between the boundary signal of the burst received data and the signal received from the division means; Data extraction means for finally extracting the phase-aligned burst received data synchronized with the byte unit from the byte synchronized signal output from the byte synchronization means in response to a data read clock signal; Distance measurement data encoding means for outputting distance measurement information encoded in a data format desired by a user in response to a phase detection signal output from the phase alignment means and a bit detection signal output from the byte synchronization means; And When the burst reception data is not received, an alarm signal is generated in response to a signal loss alarm signal output from the phase alignment means and a byte synchronization failure alarm signal output from the byte synchronization means, and output from the byte synchronization means. Alarm signal generating means for generating the alarm signal in response to the determination whether the position is normal Device comprising a. The method of claim 1, wherein the delay buffering means, And outputting a plurality of delayed data obtained by multiplying the burst received data by an arbitrary delay time divided by n by a predetermined time greater than one clock period T time of the master synchronous clock. The method of claim 2, wherein the phase alignment means, A retiming buffering means including a plurality of first D flip-flops for receiving the master synchronous clock into a clock stage and receiving the plurality of delay data respectively input from the delay buffering means to a data stage; An exclusive logic sum circuit unit for receiving an exclusive OR of a plurality of delay signals clocked to the plurality of first D flip-flops as inputs; A plurality of RSs for receiving the master synchronous clock to a clock stage and the phase detection start signal to a reset stage, and a signal output from the exclusive logic circuit to a set stage, respectively, and outputting a first phase selection signal to each output stage; First asynchronous reset synchronization means including flip-flops; A first logical AND circuit unit for receiving and logically multiplying a signal output from the plurality of RS flip-flops of the first asynchronous reset synchronization means and a signal output from the exclusive logical sum circuit unit; A plurality of stages for receiving the master synchronous clock signal for a clock stage and the phase detection start signal for a reset stage, and a signal output from the first logical product circuit unit for a set stage, respectively, and outputting a second phase selection signal to each output stage; Second asynchronous reset synchronizing means including RS flip-flops of said second flip-flop; A second logical AND circuit unit for receiving and logically multiplying the signals output from the plurality of RS flip-flops of the second asynchronous reset synchronization means and the signals output from the exclusive logical sum circuit unit; A plurality of stages for receiving the master synchronous clock signal for a clock stage and the phase detection start signal for a reset stage, and receiving a signal output from the second logical product circuit portion for a set stage, and outputting a third phase selection signal to each output stage. Third asynchronous reset synchronizing means including RS flip-flops of the third unit; Logical sum means for receiving a plurality of phase selection signals outputted from the third asynchronous reset synchronization means and performing a logical sum to output a phase detection end signal; First selecting means for selecting and outputting any one of first to third phase selection signals output from the first to third asynchronous reset synchronization means in response to the preamble length information; Delay means including a plurality of second D flip-flops for receiving a plurality of delayed signals respectively clocked to the plurality of first D flip-flops output from the retiming buffering means and delaying the plurality of second D flip-flops in response to the master synchronization clock; A plurality of third D flip-flops that receive the master synchronous clock through a clock stage and receive an arbitrary signal among a plurality of delayed signals output from the delay means to a data stage; And In response to the phase selection signal selected and output from the first selection means, one of a signal from the third D flip-flop and the remaining signals output from the delay means is selected and output to the frequency division means as a phase aligned signal. Second selection means for Device comprising a. The method of claim 3, wherein the byte synchronization means, And a byte synchronous operation is started in response to the phase detection end signal output from the phase aligning means. The method of claim 3, wherein the byte synchronization means, And outputting said normal position determination signal to said alarm signal generating means when said burst received data exists in an unwanted position compared to said reference synchronization signal.

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