JPH01205643A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten the time of synchronizing step-out by providing a CRC check bit on the location of a frame bit, applying CRC check at every multi- frame, setting the forward protection stage number and discriminating the accuracy of a coincident pulse at hunting. CONSTITUTION:A CMI code 7 is separated into a main signal and a violation pulse by a decoder 1. The violation pulse is outputted at every 6-frame, the main signal includes a CRC check bit at every frame and a CRC check pattern consists of check bits C1-C6. A CRC checking circuit 5 uses a frame pulse outputted from a frame pulse generating circuit 3 to apply CRC check to a main signal outputted from the decoder 1 and the result is used as a protection stage number control signal to decide the number of stages of protection of the protection circuit 6. The protection stage number is less when no fault is recognized by the CRC check. Thus, the time of synchronizing step-out is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization circuit in a multiplexer that performs transmission using CMI codes.

(Prior art) Conventionally, this type of synchronization circuit has a 10,000-stage protection circuit of about 4.5 stages to suppress synchronization loss caused by code errors, and a 3- to 5-stage protection circuit to prevent erroneous synchronization when synchronization is restored. A rear protection circuit was also installed.

(Problem to be Solved by the Invention) Since conventional synchronous circuits are provided with about 4 to 5 stages of forward protection circuits and about 3 to 5 stages of backward protection circuits, synchronization actually occurs and a hunting condition occurs. It takes several frames at the shortest to enter the synchronization mode, and it also has the disadvantage that there is a possibility of erroneous synchronization when the synchronization is pulled in.

The object of the present invention is to overcome the above-mentioned drawbacks.

It is an object of the present invention to provide a frame synchronization circuit that can substantially shorten the time required for out-of-synchronization.

(Means for Solving the Problems) In order to achieve the above object, a frame synchronization circuit according to the present invention includes a decoder that separates a CMI code signal into a raw signal and a violation pulse, and a frame pulse generation circuit that generates a frame pulse. a frame pulse coincidence detection circuit that compares the violation pulse and the frame pulse output from the frame pulse generation circuit and outputs a coincidence pulse, and protects the coincidence pulse;
When synchronization is lost, a synchronization protection circuit outputs a counter set signal to the frame pulse generation circuit to shift the generation timing of the frame pulse, and a synchronization protection circuit outputs a counter set signal to the frame pulse generation circuit to shift the generation timing of the frame pulse. It consists of a CRC check circuit that performs a C check, outputs the result as a protection stage number control signal, and causes the synchronization protection circuit to protect the number of stages corresponding to the protection stage number control signal.

(Example) The present invention will be explained in more detail below with reference to one drawing.

FIG. 1 is a block diagram showing an embodiment of a frame synchronization circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1.

The CMI code 7 is separated into a signal and a violation pulse by a decoder l.

Since 6 frames constitute 1 multi-frame, a pulse is output every 6 frames as shown in Figure 2(a), and the raw signal is CRC'd every frame as shown in Figure 2(C). The CRC check pattern consists of check bits Cx-Cs.

The raw signal is supplied to a multiplex conversion circuit (DMUX) 2 and a CRC check circuit 5, and the violation pulse is supplied to a frame pulse coincidence detection circuit 4.

The frame pulse coincidence detection circuit 4 compares the frame pulses respectively output from the frame pulse generation circuit 3 and the decoder 1, and when the result shows a coincidence, sends a coincidence pulse to the synchronization protection circuit 6.

The protection circuit 6 protects against the coincidence pulse according to the sure protection stage number control signal output from the CRC check circuit 5,
The result is output to the frame pulse generation circuit 3.

The frame pulse generation circuit 3 generates a frame pulse according to the output of the protection circuit 6 and outputs it to the CRC check circuit 5.

The CR, C check circuit 5 performs a CRC check on the raw signal output from the decoder 1 using the frame pulse output from the frame pulse generation circuit 3, and uses the result as a protection stage number control signal for the protection circuit 6. Determine the number of protection stages.

The number of protection stages will be reduced if no abnormality is found in the C check.

(Effects of the Invention) As described above, the invention provides a CRC check bit at the frame bit position and performs a CRC check for each multiframe.

Based on the result, the number of protection stages is set and the accuracy of the coincidence pulse at the time of notching is determined, so that the time required for loss of synchronization can be effectively reduced.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of a frame synchronization circuit according to the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. 1. 1... CMI decoder 2... Multiplex converter fi (DMUX) 3... Frame pulse generation circuit 4... Frame pulse coincidence detection circuit 5... CRC check circuit 6... Synchronization protection circuit 7 ...CMI signal 8...
・DMUX output signal patent applicant Hisashi Ii Noro, agent for NEC Corporation and patent attorney

Claims (1)

[Claims] A decoder that separates a CMI code signal into a main signal and a violation pulse, a frame pulse generation circuit that generates a frame pulse, and the violation pulse and the frame pulse output from the frame pulse generation circuit are compared. , a frame pulse coincidence detection circuit that outputs a coincidence pulse when a coincidence occurs, and protects the coincidence pulse, and when the synchronization becomes out of synchronization, outputs a counter set signal to the frame pulse generation circuit and detects the frame pulse. A CRC check is performed on the main signal using a synchronization protection circuit that shifts the timing of generation and the frame pulse output from the frame pulse generation circuit, and the result is output as a protection stage number control signal to control the number of protection stages to the synchronization protection circuit. A frame synchronization circuit comprising a CRC check circuit that protects the number of stages corresponding to a control signal.