JPH01286620A - N-ary counter circuit - Google Patents

Abstract

PURPOSE:To ensure the propagation of an asynchronous counting signal by resetting a counter with either one of the asynchronous counting signal or the signal to have detected a counted value, and combining a logic circuit to output a carry signal. CONSTITUTION:When an n1-ary counter 3 is at a value (n1-1) and a clock signal 1 is inputted, the n1-ary counter 3 counts up the value to have the counted value n1. The value is detected by an n1 detecting circuit 4, the counter is reset, and a carry signal 71 to a next stage is outputted. Next, when a asynchronous counting signal 2 at the counter value n1 is inputted, the value n1 has been already detected by an (n1-1) detecting circuit 5, as soon as the counting signal 2 is inputted, the n1-ary counter 3 is reset at the initial value, and the carry signal to the next stage is outputted. An n2-ary counter 8 is operated in the same way to generated a carry signal 72 to the next stage. Thus, the width of the counting signal is not made smaller, only the propagation delay time of a reset/carry generating circuit is made smaller, and the asynchronous counting signal can be surely propagated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an n-ary counter, and particularly to an n-ary counter that detects the value n, resets the counter, and carries it to the next stage.

[Conventional technology]

By connecting multiple n-ary counters in series, which are not powers of 2 and not necessarily the same, a one-shot clock signal is created from an asynchronous signal other than the original clock signal using the propagation delay time of the element, and FIG. 2 shows an equivalent circuit diagram of a conventional n-ary up counter that can count up asynchronously.

If the value of the first nl counter 3 is (nt 1) and the asynchronous clock signal 2 is input, (nt 1
) is counted up to nl, and the nl detection circuit 4 detects the reset signal 61 of the n1 counter 3.
and a carry signal 51 to the next stage are generated by the RS latch. The values of the first and second counters 3 and 8 are (nt
1).

(nz 1), the first counter 3 operates as described above and generates a carry signal 51, and the second counter 8 similarly detects the value n2 and outputs the reset signal 62 and digit. A raise signal 52 is generated.

Similarly, when m stages are connected in series, the first counter sequentially generates its own reset signal and a carry signal to the next stage. Since the asynchronous count signal is also asynchronous with the original clock signal, the signal is created using the propagation delay time of the element from the original signal, and the counter is counted up using the same path as the original clock signal. It was outputting a carry signal to the next stage.

[Problem to be solved by the invention]

In the above-mentioned conventional n-ary counter, the carry signal for one counter to the next stage completes the carry of the counter based on the width of the clock signal that has entered the counter, passes through the n-detection circuit, and enters the RS latch. This is the signal width obtained by subtracting the sum of the propagation delay times of the elements that the signal passes through before being input. In other words, when counting asynchronously, separate from the original clock signal,
The final stage outputs a count signal width obtained by subtracting the sum of the propagation delay times of each counter in which a carry propagates from the asynchronous count signal width input to the first counter. Therefore, in order to reliably carry up to the final stage, it is necessary to make the first count signal width sufficiently long.

However, since the count signal width is determined by the propagation delay time of the elements, the effective signal width fluctuates due to variations in the manufacturing and characteristics of the elements, resulting in the disadvantage that the carry may not propagate reliably. Motsu.

[Means to solve the problem]

The configuration of the n-ary counter circuit of the present invention is an n-ary counter that detects a value n that is not a power of 2, resets the counter, and generates a carry signal to the next stage, and the n-ary counter circuit detects a value n that is not a power of 2, resets the counter, and generates a carry signal to the next stage. In a counter in which multiple counters are connected in series and count either the original clock signal or other asynchronous signals, the counter value (n-
The counter is reset by either the asynchronous count signal detected in 1) or the signal detected by the counter value n, and a logic circuit is combined to output a carry signal to the next stage.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention, in which 1 is the original clock signal, 2 is an asynchronous count signal created based on the propagation delay time of the element, 3 is an nl up counter, and 4 is n1 detection circuit, 5 is (n+1) detection circuit, 6
1 and 62 are counter reset signals, 71 and 72 are carry signals to the next stage, 8 is an n binary counter, 9 is an n2 detection circuit, 10 is a (nz 1) detection circuit, and 11 is an asynchronous count signal and n detection An embodiment of the present invention, which is a logic circuit that is combined so as to output a counter reset signal and a carry signal to the next stage with either signal, will be described with reference to FIG.

Here, n1 counter 3 is the first counter, n2
The advance counter 8 will be referred to as the second counter.

First, let's look at the operation when the original clock signal 1 is input when the first counter 3 has the value (nt 1 ).When the clock signal 1 is input, the first counter 3
is counted up and becomes the count value n1. This is n
The counter value (
Suppose that an asynchronous count signal 2 is inputted at (nl).

The value nl has already been detected by the (nt 1) detection circuit 5, and as soon as the count signal is input, the counter is reset to the initial value and a carry signal to the next stage is output. The second stage counter also operates in the same manner as the first stage and generates a carry signal 72 to the next stage.

This embodiment will be explained again with reference to FIG. 1 while comparing it with the conventional technology. In FIG. 1, if we look at the first counter, an asynchronous count signal is input and the value (nx 1) is The signal width of the next stage is the signal width obtained by subtracting the sum of the propagation delay time of the elements through which the signal passes until nl is detected, the counter is reset, and a carry signal to the next stage is output from the count signal. However, in this embodiment, since the value (nt 1) is detected, an asynchronous count signal is waited in that state. Here, when a count signal is input, the signal directly resets the counter and becomes a carry signal to the next stage. therefore,
In the conventional technology, the count signal width was reduced by the propagation delay time during which the count signal did not propagate through the n1 base counter + nl detection circuit and the reset/carry generation circuit. It can be seen that only the propagation delay time of the circuit becomes smaller.

〔Effect of the invention〕

As explained above, the present invention resets the counter using either the value (n-1) detection circuit immediately before the carry occurrence value of the counter, the asynchronous count signal, or the output value of the n detection circuit, and transfers the digit to the next stage. By adding a logic circuit combined to output a rising signal to a conventional n-ary counter, an asynchronous count signal can be propagated more reliably in a plurality of n-ary counters connected in series.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a conventional n-ary counter. 1... Original clock signal, 2... Asynchronous count signal, 3... NL counter, 4... NL detection circuit, 5... NL-1 detection circuit, 61.62... Counter reset signal, 71.72...Carry signal to next stage, 8...n binary counter, 9...n2 detection circuit,
10... n2-1 detection circuit, 11... logic circuit.

Claims (1)

[Claims] This is an n-ary counter that detects a value n that is not a power of 2, resets the counter, and generates a carry signal to the next stage.It is a n-ary counter that detects a value n that is not a power of 2, resets the counter, and generates a carry signal to the next stage. In a counter that counts either a clock signal or other asynchronous signal, the counter is reset by either the asynchronous count signal that detected the counter value (n-1) or the signal that detected the counter value n, and then An n-ary counter circuit characterized by a combination of logic circuits that output carry signals to stages.